JPH05283271A - Chip-shaped semiconductor porcelain component and its manufacture - Google Patents

Chip-shaped semiconductor porcelain component and its manufacture

Info

Publication number
JPH05283271A
JPH05283271A JP7690192A JP7690192A JPH05283271A JP H05283271 A JPH05283271 A JP H05283271A JP 7690192 A JP7690192 A JP 7690192A JP 7690192 A JP7690192 A JP 7690192A JP H05283271 A JPH05283271 A JP H05283271A
Authority
JP
Japan
Prior art keywords
chip
type semiconductor
semiconductor ceramic
groove
grain boundary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7690192A
Other languages
Japanese (ja)
Inventor
Toshiaki Iba
俊彰 射場
Goro Nishioka
吾朗 西岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP7690192A priority Critical patent/JPH05283271A/en
Publication of JPH05283271A publication Critical patent/JPH05283271A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize a chip-shaped semiconductor porcelain component wherein it can be surface-mounted, it can expand the effective area of a counter electrode, its reliability is high and its production efficiency is high. CONSTITUTION:In a chip-shaped semiconductor porcelain component, counter electrodes 13 are formed on both main faces of the surface and the rear of a grain-boundary-insulated semiconductor porcelain substrate 16. In the chip- shaped semiconductor porcelain component, corner parts between side faces on which external connection electrodes 14 have been formed are cut and grooves 12 are formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はチタン酸ストロンチウム
等を主成分とした粒界絶縁型半導体磁器を利用したチッ
プ型半導体磁器部品及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type semiconductor porcelain component using a grain boundary insulating type semiconductor porcelain containing strontium titanate as a main component and a method for manufacturing the same.

【0002】[0002]

【従来の技術】チタン酸ストロンチウムを主成分とする
粒界絶縁型半導体磁器は、小型大容量の半導体磁器コン
デンサや静電容量を有する電圧非直線性素子などの複合
機能素子としてすぐれた特性を有するため、広く利用さ
れている。
2. Description of the Related Art Grain boundary insulating semiconductor porcelain containing strontium titanate as a main component has excellent characteristics as a multi-functional element such as a small-sized and large-capacity semiconductor porcelain capacitor or a voltage non-linear element having an electrostatic capacity. Therefore, it is widely used.

【0003】その製品形態は、円板形状の磁器基板の両
面に電極が形成され、その全体に樹脂被覆が施され、外
部接続電極としてリード線を有するものであったが、近
年の機器の小型化・薄型化の要求及びIC回路の発達に
伴い、表面実装可能なチップ型の製品形態が望まれるよ
うになってきている。
In the product form, electrodes were formed on both sides of a disk-shaped porcelain substrate, the whole of which was coated with resin, and had lead wires as external connection electrodes. Along with the demand for thinning and thinning and the development of IC circuits, a surface mountable chip type product form has been desired.

【0004】このような要求に対し、チップ型コンデン
サとして、磁器素体内に対向電極を形成し、磁器と電極
とを同時焼結させて一体型とする積層型のものが提案さ
れている。
To meet such demands, a chip type capacitor has been proposed in which a counter electrode is formed in a porcelain body and the porcelain and the electrode are co-sintered to form a monolithic type capacitor.

【0005】しかしながら、チタン酸ストロンチウムを
主成分とする粒界絶縁型半導体磁器を用いて積層型のチ
ップ形状とすることは、焼成温度が1400℃以上と高
く、しかも粒界絶縁のための酸化処理を要するため、実
用化が困難であった。
However, the use of the grain boundary insulation type semiconductor porcelain containing strontium titanate as a main component to form a laminated chip shape results in a high firing temperature of 1400 ° C. or higher and an oxidation treatment for grain boundary insulation. Therefore, it was difficult to put it into practical use.

【0006】又、チタン酸ストロンチウムを主成分とす
る粒界絶縁型半導体磁器のチップ化のために、単層のチ
ップ形状の部品が提案されている。
Also, a single layer chip-shaped component has been proposed for chipping a grain boundary insulating semiconductor ceramic containing strontium titanate as a main component.

【0007】従来のこの種チップ型半導体磁器部品を図
18〜図20に示す。図18に示したものでは、半導体
磁器基板41の表裏両主面に対向電極43が形成されて
おり、表裏面のどちらか一方の対向電極43と接続され
る外部接続電極44が前後側面に全面的に形成されてい
る。
A conventional chip type semiconductor ceramic component of this type is shown in FIGS. In the structure shown in FIG. 18, the counter electrodes 43 are formed on both front and back main surfaces of the semiconductor porcelain substrate 41, and the external connection electrodes 44 connected to either one of the front and back counter electrodes 43 are entirely formed on the front and rear side surfaces. Have been formed in the same way.

【0008】あるいは図19に示したように、半導体磁
器基板41の表裏両主面の一部を除く略中央に対向電極
43が形成され、図18に示した上記従来例のものと同
様に外部電極44が前後側面に全面的に形成されたもの
もある。
Alternatively, as shown in FIG. 19, a counter electrode 43 is formed substantially at the center of the semiconductor porcelain substrate 41 except for a part of the front and back main surfaces thereof, and the same as in the conventional example shown in FIG. In some cases, the electrodes 44 are entirely formed on the front and rear side surfaces.

【0009】あるいは図20に示したように、半導体磁
器基板41の表裏両主面の一部を除く略中央に対向電極
43が形成され、図18に示した上記従来例のものと同
様に外部電極44が前後側面に全面的に形成され、さら
に両側面にガラス絶縁層45が形成されたものもある。
Alternatively, as shown in FIG. 20, a counter electrode 43 is formed substantially at the center of the semiconductor ceramic substrate 41 except for a part of the front and back main surfaces thereof, and the external electrode is formed in the same manner as the conventional example shown in FIG. In some cases, the electrodes 44 are entirely formed on the front and rear side surfaces, and the glass insulating layers 45 are further formed on both side surfaces.

【0010】[0010]

【発明が解決しようとする課題】しかしながら上記従来
例のものでは、大容量を得ようとすると対向電極43の
面積を広く形成しなければならず、対向電極43の面積
を広げた場合、半導体磁器基板41の側面との距離が短
くなってしまい信頼性が低下する。逆に信頼性を高めよ
うとすると対向電極43の面積を小さくしたり、絶縁の
ためのガラス絶縁層45を側面に形成したりする必要が
あり、大容量を得ることが困難となったり、あるいは製
造上の困難をともなうという課題があった。
However, in the above-mentioned conventional example, the area of the counter electrode 43 must be made large in order to obtain a large capacity, and when the area of the counter electrode 43 is widened, the semiconductor porcelain is increased. The distance from the side surface of the substrate 41 is shortened and reliability is reduced. On the contrary, in order to improve reliability, it is necessary to reduce the area of the counter electrode 43 or to form the glass insulating layer 45 for insulation on the side surface, which makes it difficult to obtain a large capacity, or There has been a problem in that there are manufacturing difficulties.

【0011】本発明は上記課題に鑑み発明されたもので
あって、表面実装が可能で、有効となる対向電極面積を
広く取ることができ、かつ信頼性の高く、しかも製造が
比較的容易なチップ型半導体磁器部品及びその製造方法
を提供することを目的としている。
The present invention has been invented in view of the above-mentioned problems, and can be surface-mounted, can have a large effective counter electrode area, is highly reliable, and is relatively easy to manufacture. It is an object of the present invention to provide a chip type semiconductor ceramic component and a method for manufacturing the same.

【0012】[0012]

【課題を解決するための手段】上記目的を達成するため
に本発明に係るチップ型半導体磁器部品は、粒界絶縁型
半導体磁器基板の表裏両主表面に対向電極が形成された
チップ型半導体磁器部品において、外部接続電極が形成
された側面間の角部に凹部が形成されていることを特徴
とし(1)、また上記(1)記載のチップ型半導体磁器
部品の製造方法において、表裏両主面に複数本の平行で
表裏相対向する溝が形成された半導体磁器基板に、粒界
絶縁化処理を施す工程を含んでいることを特徴とし
(2)、さらには上記(1)記載のチップ型半導体磁器
部品において、凹部にガラス絶縁層が形成されているこ
とを特徴とし(3)、また上記(3)記載のチップ型半
導体磁器部品の製造方法において、表裏両主面に複数本
の平行で表裏相対向する溝が形成された半導体磁器基板
に、粒界絶縁化処理を施した後、前記溝内にガラス絶縁
層を形成する工程を含んでいることを特徴としている
(4)。
To achieve the above object, a chip-type semiconductor ceramic component according to the present invention is a chip-type semiconductor ceramic in which counter electrodes are formed on both front and back main surfaces of a grain boundary insulating semiconductor ceramic substrate. In the component, recesses are formed in the corners between the side surfaces on which the external connection electrodes are formed (1), and in the method for manufacturing a chip type semiconductor ceramic component according to (1) above, both front and back main (2) The chip according to (1) above, further comprising a step of subjecting a semiconductor porcelain substrate having a plurality of parallel grooves facing each other to the front and back sides to each other to perform grain boundary insulation treatment. (3) In the method for manufacturing a chip type semiconductor ceramic component according to the above (3), a plurality of parallel surfaces are provided on both front and back main surfaces. Face to face The semiconductor ceramic substrate having a groove, after performing grain boundary insulation treatment, is characterized by comprising the step of forming the glass insulating layer in the groove (4).

【0013】また上記(1)記載のチップ型半導体磁器
部品において、外部接続電極と対向電極との接続側角部
と反対側角部近傍に溝が形成されていることを特徴とし
(5)、さらには上記(5)記載のチップ型半導体磁器
部品の製造方法において、表裏両主面に複数本の平行で
表裏相対向する溝が形成されると共に、前記溝に直交す
る複数本の表裏相対向しない溝が形成された半導体磁器
基板に、粒界絶縁化処理を施す工程を含んでいることを
特徴としている(6)。
Further, in the chip-type semiconductor porcelain component according to the above (1), a groove is formed in the vicinity of a corner opposite to a connecting side between the external connection electrode and the counter electrode (5), Furthermore, in the method for manufacturing a chip-type semiconductor ceramic component according to the above (5), a plurality of parallel grooves facing each other in the front and back sides are formed on both main surfaces, and a plurality of front and back surface facing each other orthogonal to the grooves. It is characterized in that it includes a step of performing grain boundary insulation treatment on the semiconductor porcelain substrate in which the groove not formed is formed (6).

【0014】また上記(5)記載のチップ型半導体磁器
部品において、凹部及び溝にガラス絶縁層が形成されて
いることを特徴とし(7)、また上記(7)記載のチッ
プ型半導体磁器部品の製造方法において、表裏両主面に
複数本の平行で表裏相対向する溝が形成されると共に、
前記溝に直交する複数本の表裏相対向しない溝が形成さ
れた半導体磁器基板に、粒界絶縁化処理を施した後、前
記溝内にガラス絶縁層を形成する工程を含んでいること
を特徴としている(8)。
Further, in the chip-type semiconductor ceramic component according to the above (5), a glass insulating layer is formed in the recess and the groove (7), and in the chip-type semiconductor ceramic component according to the above (7). In the manufacturing method, a plurality of parallel grooves facing the front and back sides are formed on both the front and back main surfaces,
The method includes a step of forming a glass insulating layer in the groove after performing a grain boundary insulating treatment on a semiconductor porcelain substrate in which a plurality of grooves which are orthogonal to the groove and do not face each other are formed. (8).

【0015】また上記(1)記載のチップ型半導体磁器
部品において、対向電極が形成された両主面間の角部に
凹部が形成されていることを特徴とし(9)、さらには
上記(9)記載のチップ型半導体磁器部品の製造方法に
おいて、表裏両主面に複数本の平行で表裏相対向する溝
が形成されると共に、これら溝間に複数個の孔が形成さ
れた半導体磁器基板に、粒界絶縁化処理を施す工程を含
んでいることを特徴としている(10)。
Further, in the chip-type semiconductor porcelain component according to the above (1), a recess is formed at a corner between both main surfaces on which the counter electrodes are formed (9), and further, the above (9) ) In the method for manufacturing a chip-type semiconductor porcelain component described above, a semiconductor porcelain substrate in which a plurality of parallel parallel front and back grooves are formed on both main surfaces and a plurality of holes are formed between these grooves. The method is characterized in that it includes a step of performing grain boundary insulation treatment (10).

【0016】また上記(5)記載のチップ型半導体磁器
部品において、対向電極が形成された両主面間の角部に
凹部が形成されていることを特徴とし(11)、さらに
は上記(11)記載のチップ型半導体磁器部品の製造方
法において、表裏両主面に複数本の平行で表裏相対向す
る溝が形成されると共に、前記溝に直交する複数本の表
裏相対向しない溝が形成され、さらに表裏相対向する前
記溝間に複数個の孔が形成された半導体磁器基板に、粒
界絶縁化処理を施す工程を含んでいることを特徴として
いる(12)。
Further, the chip-type semiconductor ceramic component according to the above (5) is characterized in that a recess is formed at a corner between both main surfaces on which the counter electrodes are formed (11), and further, the above (11). ) In the method for manufacturing a chip-type semiconductor ceramic component as described above, a plurality of parallel parallel grooves facing each other are formed on both main surfaces of the front and back surfaces, and a plurality of grooves perpendicular to the groove are formed so as not to face each other. The method further comprises the step of subjecting the semiconductor ceramic substrate having a plurality of holes formed between the grooves facing each other to the grain boundary insulating treatment (12).

【0017】また上記(9)または(11)記載のチッ
プ型半導体磁器部品において、凹部及び溝にガラス絶縁
層が形成されていることを特徴とし(13)、また上記
(13)記載のチップ型半導体磁器部品の製造方法にお
いて、溝及び孔が形成された半導体磁器基板に、粒界絶
縁化処理を施した後、前記溝内及び前記孔内にガラス絶
縁層を形成する工程を含んでいることを特徴としている
(14)。
Further, in the chip-type semiconductor ceramic component according to (9) or (11), a glass insulating layer is formed in the recess and the groove (13), and the chip-type according to (13) above. The method for manufacturing a semiconductor porcelain component includes a step of forming a glass insulating layer in the groove and the hole after performing a grain boundary insulating treatment on the semiconductor porcelain substrate in which the groove and the hole are formed. (14).

【0018】[0018]

【作用】上記した(1)、(5)、(9)及び(11)
の構成によれば、外部接続電極が形成された側面間の角
部が切削されて凹部が形成されており、または前記凹部
に加えて外部接続電極と対向電極との接続側角部と反対
側角部近傍に溝が形成されており、または、前記凹部に
加えて対向電極が形成された両主面間の角部が切削され
て凹部が形成されており、または前記凹部及び前記溝部
に加えて対向電極が形成された両主面間の角部が切削さ
れて凹部が形成されているので、これら凹部及び溝の部
分において絶縁性が確保される。
(Function) The above (1), (5), (9) and (11)
According to the configuration, the corners between the side surfaces on which the external connection electrodes are formed are cut to form recesses, or in addition to the recesses, the side opposite to the connection side corner between the external connection electrode and the counter electrode is formed. A groove is formed in the vicinity of the corner, or a corner is cut by cutting the corner between both main surfaces where the counter electrode is formed in addition to the recess, or in addition to the recess and the groove. Since the corners between the two main surfaces on which the opposing electrodes are formed are cut to form the recesses, the insulation is ensured in the recesses and the grooves.

【0019】また上記した(2)、(6)、(10)及
び(12)の製造方法によれば、前記凹部及び前記溝が
形成された半導体磁器基板に、粒界絶縁化処理を施す工
程を含んでいるので、これら凹部及び溝の表面は確実に
絶縁処理される。
Further, according to the manufacturing methods of (2), (6), (10) and (12) described above, a step of subjecting the semiconductor porcelain substrate having the recess and the groove formed to grain boundary insulation treatment. Therefore, the surfaces of these recesses and grooves are reliably insulated.

【0020】さらに上記した(3)、(7)及び(1
3)の構成によれば、前記凹部及び前記溝にガラス絶縁
層が形成されているので、信頼性がさらに向上するだけ
でなく、前記凹部及び前記溝を小さく設計することが可
能となり、対向電極等の面積を広くとることが可能とな
る。
Further, the above (3), (7) and (1
According to the configuration of 3), since the glass insulating layer is formed in the recess and the groove, not only the reliability is further improved, but also the recess and the groove can be designed small, and the counter electrode can be formed. It becomes possible to take a large area such as.

【0021】また上記した(4)、(8)及び(14)
の製造方法によれば、前記粒界絶縁化処理を施した後、
前記溝内にガラス絶縁層を形成しているので、粒界絶縁
化処理のみを行なう場合よりもより一層絶縁性の確保が
容易となる。
Further, the above (4), (8) and (14)
According to the manufacturing method of, after performing the grain boundary insulation treatment,
Since the glass insulating layer is formed in the groove, it becomes easier to secure the insulating property as compared with the case where only the grain boundary insulating treatment is performed.

【0022】[0022]

【実施例】以下、本発明に係るチップ型半導体磁器部品
及びその製造方法の実施例を図面に基づいて説明する。
Embodiments of a chip type semiconductor ceramic component and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

【0023】(実施例1)図1〜図4は本発明に係るチ
ップ型半導体磁器部品の製造方法の一実施例を工程順に
示した模式的斜視図及び側面図である。
(Embodiment 1) FIGS. 1 to 4 are schematic perspective views and side views showing an embodiment of a method of manufacturing a chip type semiconductor ceramic component according to the present invention in the order of steps.

【0024】本実施例に係るチップ型半導体磁器部品を
製造する場合、まずチタン酸ストロンチウムを主成分と
する半導体磁器用原料粉末を用意し、バインダを混合し
た後プレス成形で表裏両主面に相対向する互いに平行な
複数個の溝12を有した1枚のシート状成形体を形成す
る。このシート状成形体に空気中で800〜1000℃
の温度範囲で脱バインダ処理を施した後、窒素85〜9
9%と水素15〜1%よりなる還元雰囲気中で1450
〜1500℃の温度範囲で焼成し、半導体磁器基板11
を作製する(図1)。
In the case of manufacturing the chip type semiconductor porcelain component according to this embodiment, first, a raw material powder for semiconductor porcelain containing strontium titanate as a main component is prepared, and a binder is mixed, and then press molding is performed to make the front and back main surfaces relative to each other. A sheet-shaped molded body having a plurality of grooves 12 facing each other and parallel to each other is formed. This sheet-shaped molded body is 800 to 1000 ° C. in air.
After removing the binder in the temperature range of
1450 in a reducing atmosphere consisting of 9% and 15-1% hydrogen
The semiconductor porcelain substrate 11 is fired in a temperature range of up to 1500 ° C.
Are produced (FIG. 1).

【0025】得られた半導体磁器基板11を溝12と直
交する鎖線で示した切断線で所望の寸法に切断し、短冊
状の基板を形成する。ついでその両主表面にBi2O3 を主
成分とする拡散剤を塗布し、空気中で1100〜125
0℃の温度範囲で粒界絶縁化のための熱処理を行ない、
粒界絶縁型半導体磁器基板16を作成する(図2)。
The obtained semiconductor porcelain substrate 11 is cut to a desired size along a cutting line shown by a chain line orthogonal to the groove 12 to form a strip-shaped substrate. Then, a diffusing agent containing Bi 2 O 3 as a main component is applied to both of the main surfaces, and 1100 to 125 in air.
Heat treatment for grain boundary insulation is performed in the temperature range of 0 ° C,
The grain boundary insulating type semiconductor ceramic substrate 16 is prepared (FIG. 2).

【0026】粒界絶縁型半導体磁器基板16の表裏両主
表面の溝12を除く平面上に、所望の形状に銀ペースト
を印刷し、空気中で750〜860℃の温度範囲で焼き
付けを行ない、対向電極13を形成する(図3)。
Silver paste is printed in a desired shape on the planes of both main surfaces of the front and back surfaces of the grain boundary insulating semiconductor ceramic substrate 16 excluding the grooves 12, and baking is performed in the temperature range of 750 to 860 ° C. in air. The counter electrode 13 is formed (FIG. 3).

【0027】次に溝12を割り溝として、個々の素体に
分割する。そして最後に表裏主表面上の対向電極13の
各々片方に接続する外部接続電極14を所望の形状に、
溝12と直交する側面に形成してチップ型半導体磁器部
品17を作製する(図4)。
Next, the groove 12 is used as a split groove and divided into individual element bodies. Finally, the external connection electrodes 14 connected to one of the counter electrodes 13 on the front and back main surfaces are formed into a desired shape.
The chip type semiconductor ceramic component 17 is formed by forming it on the side surface orthogonal to the groove 12 (FIG. 4).

【0028】このように本実施例にあっては、溝12を
形成した後に粒界絶縁化処理を施しているので、溝12
を割り溝として粒界絶縁型半導体磁器基板16を後の工
程で切断しても、対向電極13間は確実に絶縁され、信
頼性の高いチップ型半導体磁器部品を製作することがで
きる。また溝12を形成することにより対向電極13の
面積を広く取ることが可能となり、容量を増大させるこ
とができる。さらには溝12を割り溝として利用するこ
とができ、チップ型半導体磁器部品17の製作が容易と
なる。
As described above, in this embodiment, since the grain boundary insulating treatment is performed after forming the groove 12, the groove 12 is formed.
Even if the grain boundary insulation type semiconductor ceramic substrate 16 is cut in a later step using the groove as a split groove, the opposing electrodes 13 are surely insulated from each other, and a highly reliable chip type semiconductor ceramic component can be manufactured. In addition, by forming the groove 12, it is possible to increase the area of the counter electrode 13 and increase the capacitance. Furthermore, the groove 12 can be used as a split groove, and the chip-type semiconductor ceramic component 17 can be easily manufactured.

【0029】(実施例2)図5(a)、(b)は本発明
に係るチップ型半導体磁器部品及びその製造方法の別の
実施例を示した模式的斜視図及び側面図である。
(Embodiment 2) FIGS. 5 (a) and 5 (b) are a schematic perspective view and a side view showing another embodiment of the chip type semiconductor ceramic component and the manufacturing method thereof according to the present invention.

【0030】実施例1の場合と同様にして、表裏両主表
面上に銀ペストを焼き付けて形成した対向電極13を有
した短冊状の粒界絶縁型半導体磁器基板16を作製し
(図3)、さらに粒界絶縁型半導体磁器基板16の表裏
両主面の相対向する溝12内に絶縁性のB2O3、SiO2、Zn
O を主成分とするガラスペーストを印刷塗布し、空気中
で750〜870℃の温度範囲で焼き付けを行なう。次
に溝12を割り溝として、個々の素体に分割する。最後
に表裏主表面上の対向電極13の各々片方に接続する外
部接続電極14を所望の形状に溝12と直交する側面に
形成してチップ型半導体磁器部品18を作製する(図
5)。
In the same manner as in Example 1, a strip-shaped grain boundary insulation type semiconductor porcelain substrate 16 having counter electrodes 13 formed by baking silver plague on both front and back main surfaces was prepared (FIG. 3). In addition, insulating B 2 O 3 , SiO 2 and Zn are provided in the grooves 12 on the front and back main surfaces of the grain boundary insulating semiconductor ceramic substrate 16 which face each other.
A glass paste containing O 2 as a main component is applied by printing, and baking is performed in the temperature range of 750 to 870 ° C. in air. Next, the groove 12 is used as a split groove and divided into individual element bodies. Finally, an external connection electrode 14 connected to one of the counter electrodes 13 on the front and back main surfaces is formed in a desired shape on the side surface orthogonal to the groove 12 to produce a chip-type semiconductor ceramic component 18 (FIG. 5).

【0031】このように本実施例にあっては、溝12を
形成した後に粒界絶縁化処理を施し、さらに溝12内に
絶縁性のガラスペーストを印刷塗布しているので、溝1
2を割り溝として粒界絶縁型半導体磁器基板16を後の
工程で切断しても、対向電極13間は確実に絶縁され、
信頼性の高いチップ型半導体磁器部品を製作することが
できる。また溝12にガラス絶縁層15を印刷塗布する
ことにより実施例1よりさらに対向電極13の面積を広
く取ることが可能となり、容量を増大させることができ
る。
As described above, in this embodiment, since the grain boundary insulating treatment is performed after the groove 12 is formed and the insulating glass paste is applied by printing in the groove 12, the groove 1 is formed.
Even if the grain boundary insulating semiconductor ceramic substrate 16 is cut in a later step using 2 as a split groove, the opposing electrodes 13 are surely insulated from each other,
It is possible to manufacture a highly reliable chip type semiconductor ceramic component. Further, by printing and coating the glass insulating layer 15 on the groove 12, the area of the counter electrode 13 can be made larger than that of the first embodiment, and the capacitance can be increased.

【0032】(実施例3)図6(a)、(b)は本発明
に係るチップ型半導体磁器部品及びその製造方法のさら
に別の実施例を示した模式的斜視図及び側面図である。
(Embodiment 3) FIGS. 6A and 6B are a schematic perspective view and a side view showing still another embodiment of a chip type semiconductor ceramic component and a method for manufacturing the same according to the present invention.

【0033】実施例1の場合と同様にして表裏両主表面
上に銀ペーストを焼き付けて形成した対向電極13を有
した短冊状の粒界絶縁型半導体磁器基板16を作製し
(図3)、さらに粒界絶縁型半導体磁器基板16の表裏
両主面の相対向する溝12内及び対向電極13上に絶縁
性のB2O3、SiO2、ZnO を主成分とするガラスペーストを
印刷塗布し、空気中で750〜870℃の温度範囲で焼
き付けを行ない、チップ型半導体磁器部品19を作製す
る(図6)。
In the same manner as in Example 1, a strip-shaped grain boundary insulating semiconductor ceramic substrate 16 having counter electrodes 13 formed by baking a silver paste on both front and back main surfaces was prepared (FIG. 3). Further, an insulating glass paste containing B 2 O 3 , SiO 2 , and ZnO as main components is printed and applied in the grooves 12 on the front and back main surfaces of the grain boundary insulating semiconductor ceramic substrate 16 facing each other and on the counter electrode 13. Then, baking is performed in the air in the temperature range of 750 to 870 ° C. to produce the chip-type semiconductor ceramic component 19 (FIG. 6).

【0034】このように本実施例にあっては、溝12を
形成した後に粒界絶縁化処理を施し、さらに溝12内及
び対向電極上13に絶縁性のガラスペーストを印刷塗布
しているので、溝12を割り溝として粒界絶縁型半導体
磁器基板16を後の工程で切断しても、対向電極13間
は確実に絶縁され、信頼性の高いチップ型半導体磁器部
品を製作することができる。また溝12内及び対向電極
13上にガラス絶縁層15を印刷塗布することによりさ
らに対向電極13の面積を広く取ることが可能となり、
容量を増大させることができる。さらに、実施例2に比
べ、対向電極13間の絶縁化を高めることができる。
As described above, in this embodiment, the grain boundary insulating treatment is performed after the groove 12 is formed, and the insulating glass paste is printed and applied in the groove 12 and on the counter electrode 13. Even if the grain boundary insulating semiconductor porcelain substrate 16 is cut in a later step using the groove 12 as a split groove, the opposing electrodes 13 are surely insulated from each other, and a highly reliable chip type semiconductor porcelain component can be manufactured. .. Further, by printing and coating the glass insulating layer 15 in the groove 12 and on the counter electrode 13, it is possible to further increase the area of the counter electrode 13.
The capacity can be increased. Further, the insulation between the counter electrodes 13 can be enhanced as compared with the second embodiment.

【0035】(実施例4)図7〜図10は本発明に係る
チップ型半導体磁器部品及びその製造方法のさらに別の
実施例を示した模式的斜視図及び側面図である。
(Embodiment 4) FIGS. 7 to 10 are schematic perspective views and side views showing still another embodiment of the chip type semiconductor ceramic component and the method for manufacturing the same according to the present invention.

【0036】本実施例に係るチップ型半導体磁器部品を
製造する場合、まずチタン酸ストロンチウムを主成分と
する半導体磁器用原料粉末を用意し、バインダを混合し
た後プレス成形で表裏両主表面に相対向する互いに平行
な複数個の溝22a及び溝22aに直交する表裏相対向
しない互いに平行な複数個の溝22bを有する1枚のシ
ート状成形体を形成する。このシート状成形体に空気中
で800〜1000℃の温度範囲で脱バインダ処理を施
した後、窒素85〜99%と水素15〜1%よりなる還
元雰囲気中で1450〜1500℃の温度範囲で焼成
し、半導体磁器基板21を作製する(図7)。
In the case of manufacturing the chip-type semiconductor porcelain component according to the present embodiment, first, a raw material powder for semiconductor porcelain containing strontium titanate as a main component is prepared, mixed with a binder, and then press-molded so as to be opposed to both front and back main surfaces. One sheet-shaped molded product is formed having a plurality of parallel grooves 22a facing each other and a plurality of parallel grooves 22b orthogonal to the grooves 22a and not facing each other. This sheet-shaped molded product was subjected to binder removal treatment in air at a temperature range of 800 to 1000 ° C., and then at a temperature range of 1450 to 1500 ° C. in a reducing atmosphere composed of 85 to 99% nitrogen and 15 to 1% hydrogen. Firing is performed to produce the semiconductor ceramic substrate 21 (FIG. 7).

【0037】得られた半導体磁器基板21を表裏両主表
面で相対向しない溝22bと平行な鎖線で示した切断線
で所望の寸法に切断し、短冊状の基板を形成する。その
両主表面にBi2O3 を主成分とする拡散剤を塗布し、空気
中で1100〜1250℃の温度範囲で粒界絶縁化のた
めの熱処理を行ない、粒界絶縁型半導体磁器基板26を
作成する(図8)。
The obtained semiconductor porcelain substrate 21 is cut to a desired size along a cutting line shown by a chain line parallel to the grooves 22b which do not face each other on the front and back main surfaces to form a strip-shaped substrate. A diffusing agent containing Bi 2 O 3 as a main component is applied to both main surfaces and heat treatment for grain boundary insulation is performed in the temperature range of 1100 to 1250 ° C. in the air. Is created (FIG. 8).

【0038】粒界絶縁型半導体磁器基板26の表裏両主
表面の溝22a、22bを除く平面上に所望の形状に銀
ペーストを印刷し、空気中で750〜860℃の温度範
囲で焼き付けを行ない対向電極23を形成する(図
9)。
Silver paste is printed in a desired shape on the planes of both main surfaces of the front and back surfaces of the grain boundary insulation type semiconductor ceramic substrate 26 excluding the grooves 22a and 22b, and baking is performed in the air at a temperature range of 750 to 860 ° C. The counter electrode 23 is formed (FIG. 9).

【0039】次に表裏相対向する溝22aを割り溝とし
て、個々の素体に分割する。最後に表裏主表面上の対向
電極23の各々片方に接続する外部接続電極24を所望
の形状に、溝22bを平行な側面に形成して、チップ型
半導体磁器部品27を作製する(図10)。
Next, the groove 22a facing the front and back is used as a split groove to divide the element into individual bodies. Finally, the external connection electrode 24 connected to one of the opposing electrodes 23 on the front and back main surfaces is formed in a desired shape, and the groove 22b is formed on the parallel side surfaces to produce a chip-type semiconductor ceramic component 27 (FIG. 10). ..

【0040】このように本実施例にあっては、溝22a
を形成した後に粒界絶縁化処理を施しているので、溝2
2aを割り溝として粒界絶縁型半導体磁器基板26を後
の工程で切断しても、対向電極23間は確実に絶縁さ
れ、信頼性の高いチップ型半導体磁器部品を製作するこ
とができる。また溝22bを形成することにより対向電
極23と外部接続電極24間は確実に絶縁されることか
ら、対向電極23の面積を広く取ることが可能となり、
容量を増大させることができる。さらには溝22aを割
り溝として利用することができ、チップ型半導体磁器部
品27の製作が容易となる。
As described above, in this embodiment, the groove 22a is formed.
Since the grain boundary insulation treatment is performed after the formation of the
Even if the grain boundary insulating semiconductor ceramic substrate 26 is cut in a later step by using the groove 2a as a split groove, the opposing electrodes 23 are surely insulated from each other, and a highly reliable chip type semiconductor ceramic component can be manufactured. Further, since the counter electrode 23 and the external connection electrode 24 are reliably insulated by forming the groove 22b, it is possible to make the area of the counter electrode 23 large.
The capacity can be increased. Furthermore, the groove 22a can be used as a split groove, and the chip-type semiconductor ceramic component 27 can be easily manufactured.

【0041】(実施例5)図11(a)、(b)は本発
明に係るチップ型半導体磁器部品及びその製造方法のさ
らに別の実施例を示した模式的斜視図及び側面図であ
る。
(Embodiment 5) FIGS. 11A and 11B are a schematic perspective view and a side view showing still another embodiment of the chip type semiconductor ceramic component and the method for manufacturing the same according to the present invention.

【0042】実施例4の場合と同様にして表裏両主表面
上に銀ペーストを焼き付けて形成した対向電極23を有
した短冊状の粒界絶縁型半導体磁器基板26を作製し
(図9)、粒界絶縁型半導体磁器基板26の表裏両主面
の相対向する溝22a内及び溝22aに直交する溝22
b内に絶縁性のB2O3、SiO2、ZnO を主成分とするガラス
ペースト25を印刷塗布し、空気中で750〜870℃
の温度範囲で焼き付けを行なう。次に表裏両主面の相対
向する溝22aを割り溝として個々の素体に分割する。
最後に表裏主表面上の対向電極23の各々片方に接続す
る外部接続電極24を所望の形状に溝22bと平行な側
面に形成してチップ型半導体磁器部品28を作製する
(図11)。
In the same manner as in Example 4, a strip-shaped grain boundary insulation type semiconductor porcelain substrate 26 having counter electrodes 23 formed by baking silver paste on both front and back main surfaces was prepared (FIG. 9). Grooves 22 in the grooves 22a facing each other on the front and back main surfaces of the grain boundary insulating type semiconductor ceramic substrate 26 and perpendicular to the grooves 22a.
A glass paste 25 containing insulating B 2 O 3 , SiO 2 , and ZnO as main components is printed and applied in b, and the temperature is 750 to 870 ° C. in air.
Bake in the temperature range of. Next, the grooves 22a facing each other on the front and back main surfaces are divided into individual elements as split grooves.
Finally, an external connection electrode 24 connected to one of the opposite electrodes 23 on the front and back main surfaces is formed in a desired shape on the side surface parallel to the groove 22b to produce a chip-type semiconductor ceramic component 28 (FIG. 11).

【0043】このように本実施例にあっては、溝22a
を形成した後に粒界絶縁化処理を施しているので、溝2
2aを割り溝として粒界絶縁型半導体磁器基板26を後
の工程で切断しても、対向電極23間は確実に絶縁さ
れ、実施例4に比べ、さらに信頼性の高いチップ型半導
体磁器部品を製作することができる。また溝22bを形
成することにより対向電極23と外部接続電極24間は
確実に絶縁されるだけでなく、対向電極23の面積を広
く取ることが可能となり、容量を増大させることができ
る。
As described above, in this embodiment, the groove 22a is formed.
Since the grain boundary insulation treatment is performed after the formation of the
Even if the grain boundary insulating semiconductor ceramic substrate 26 is cut in a later step using 2a as a split groove, the opposing electrodes 23 are surely insulated from each other, and a chip type semiconductor ceramic component having higher reliability than that of the fourth embodiment is provided. Can be manufactured. Further, by forming the groove 22b, not only the counter electrode 23 and the external connection electrode 24 are reliably insulated, but also the counter electrode 23 can have a large area and the capacity can be increased.

【0044】(実施例6)図12〜図15は本発明に係
るチップ型半導体磁器部品及びその製造方法のさらに別
の実施例を示した模式的斜視図及び側面図である。
(Embodiment 6) FIGS. 12 to 15 are schematic perspective views and side views showing still another embodiment of the chip type semiconductor ceramic component and the manufacturing method thereof according to the present invention.

【0045】本実施例に係るチップ型半導体磁器基板を
製造する場合、まずチタン酸ストロンチウムを主成分と
する半導体磁器用原料粉末を用意し、バインダを混合し
た後プレス成形で表裏両主表面に相対向する互いに平行
な複数個の溝32aおよび溝32aに直交する表裏相対
向しない互いに平行な複数個の溝32bを有し、また図
中鎖線で示した切断線と溝32aとの交点の溝32a内
に孔37を有する1枚のシート状成形体を形成する。こ
のシート状成形体に空気中800〜1000℃の温度範
囲で脱バインダ処理を施した後、窒素85〜99%と水
素15〜1%よりなる還元雰囲気中で1450〜150
0℃の温度範囲で焼成し、半導体磁器基板31を作製す
る(図12)。
In the case of manufacturing the chip type semiconductor porcelain substrate according to this example, first, a raw material powder for semiconductor porcelain containing strontium titanate as a main component is prepared, and a binder is mixed, followed by press molding so that the front and back main surfaces are opposed to each other. A plurality of parallel grooves 32a facing each other and a plurality of parallel grooves 32b orthogonal to the grooves 32a that do not face each other are provided, and the groove 32a at the intersection of the cutting line and the groove 32a shown by the chain line in the figure. A sheet-shaped molded body having a hole 37 therein is formed. This sheet-shaped molded product was subjected to binder removal treatment in the temperature range of 800 to 1000 ° C. in air, and then 1450 to 150 in a reducing atmosphere containing 85 to 99% of nitrogen and 15 to 1% of hydrogen.
Firing is performed in the temperature range of 0 ° C. to manufacture the semiconductor ceramic substrate 31 (FIG. 12).

【0046】得られた半導体磁器基板31の両主表面に
Bi2O3 を主成分とする拡散剤を塗布し、空気中で110
0〜1250℃の温度範囲で粒界絶縁化のための熱処理
を行ない、その後溝32bと平行な鎖線で示した切断線
で所望の寸法に切断し、粒界絶縁型半導体磁器基板36
を作製する(図13)。
On both main surfaces of the obtained semiconductor porcelain substrate 31,
Apply a diffusing agent containing Bi 2 O 3 as the main component, and use 110 in air.
A heat treatment for grain boundary insulation is performed in a temperature range of 0 to 1250 ° C., and thereafter, the grain boundary insulation type semiconductor porcelain substrate 36 is cut to a desired size by a cutting line shown by a chain line parallel to the groove 32b.
Are produced (FIG. 13).

【0047】粒界絶縁型半導体磁器基板36の表裏両主
表面の溝32a、32bを除く平面上に所望の形状に銀
ペーストを印刷し、空気中で750〜860℃の温度範
囲で焼き付けを行ない、対向電極33を形成する(図1
4)。
Silver paste is printed in a desired shape on the planes of both main surfaces of the front and back surfaces of the grain boundary insulating semiconductor ceramic substrate 36 except the grooves 32a and 32b, and baking is performed in the air at a temperature range of 750 to 860 ° C. , Counter electrode 33 is formed (FIG. 1
4).

【0048】次に表裏相対向する溝32aを割り溝とし
て切断し、個々の素体に分割する。最後に表裏両主表面
上の対向電極33の各々片方に接続する外部接続電極3
4を所望の形状に、溝32bと平行な側面に形成してチ
ップ型半導体磁器部品38を作製する(図15)。
Next, the grooves 32a facing each other on the front and back sides are cut as split grooves and divided into individual element bodies. Finally, the external connection electrode 3 connected to one of the opposite electrodes 33 on both the front and back main surfaces
4 is formed in a desired shape on the side surface parallel to the groove 32b to produce the chip-type semiconductor ceramic component 38 (FIG. 15).

【0049】このように本実施例にあっては、溝32
a、32bを形成した後に粒界絶縁化処理を施している
ので、溝32aを割り溝として粒界絶縁型半導体磁器基
板36を後の工程で切断しても、対向電極33間は確実
に絶縁され、さらに対向電極33と外部接続電極34間
においても確実に絶縁化されるため、さらに信頼性の高
いチップ型半導体磁器部品を製作することができる。ま
た孔37を形成することにより外部接続電極34間は確
実に絶縁され、さらに信頼性の高いものになる。
Thus, in this embodiment, the groove 32
Since the grain boundary insulating treatment is performed after forming a and 32b, even if the grain boundary insulating semiconductor ceramic substrate 36 is cut in a later step using the groove 32a as a split groove, the opposing electrodes 33 are reliably insulated. Further, since the counter electrode 33 and the external connection electrode 34 are also reliably insulated, it is possible to manufacture a more reliable chip type semiconductor ceramic component. Further, by forming the holes 37, the external connection electrodes 34 are reliably insulated from each other, and the reliability is further enhanced.

【0050】(実施例7)図16(a)、(b)は本発
明に係るチップ型半導体磁器部品及びその製造方法のさ
らに別の実施例を示した模式的斜視図及び側面図であ
る。
(Embodiment 7) FIGS. 16A and 16B are a schematic perspective view and a side view showing still another embodiment of a chip type semiconductor ceramic component and a method for manufacturing the same according to the present invention.

【0051】実施例6の場合と同様にして表裏両主表面
上に銀ペーストを焼き付けて形成した対向電極33を有
する粒界絶縁型半導体磁器基板36を作製し(図4)、
粒界絶縁型半導体磁器基板36の表裏両主面の相対向す
る溝32a内及び溝32aに直交する溝32b内さらに
表裏貫通する孔37内に絶縁性のB2O3、SiO2、ZnO を主
成分とするガラスペースト35を印刷塗布し、空気中で
750〜870℃の温度範囲で焼き付けを行なう。次に
表裏相対向する溝32aを割り溝として個々の素体に分
割した。最後に表裏両主表面上の対向電極33の各々片
方に接続する外部接続電極34を所望の形状に溝32b
と平行な側面に形成してチップ型半導体磁器部品39を
作製する(図16)。
In the same manner as in Example 6, a grain boundary insulating semiconductor ceramic substrate 36 having counter electrodes 33 formed by baking silver paste on both front and back main surfaces was prepared (FIG. 4).
Insulating B 2 O 3 , SiO 2 , and ZnO are provided in the grooves 32a facing each other on the front and back main surfaces of the grain boundary insulating semiconductor ceramic substrate 36, in the grooves 32b orthogonal to the grooves 32a, and in the holes 37 penetrating the front and back. The glass paste 35 as a main component is applied by printing, and baking is performed in the air at a temperature range of 750 to 870 ° C. Next, the grooves 32a facing the front and back sides were divided into individual element bodies as split grooves. Finally, the external connection electrode 34 connected to one of the counter electrodes 33 on the front and back main surfaces is formed into a groove 32b having a desired shape.
The chip-type semiconductor porcelain component 39 is formed by forming it on the side surface parallel to (FIG. 16).

【0052】このように本実施例にあっては、溝32
a、32b及び孔37を形成した後に粒界絶縁化処理を
施し、さらにガラス絶縁層35で印刷塗布しているの
で、溝32aを割り溝として粒界絶縁型半導体磁器基板
36を後の工程で切断しても、対向電極33間は確実に
絶縁され、対向電極33と外部接続電極34間において
も確実に絶縁化され、さらに外部接続電極34間も確実
に絶縁され、実施例6に比べ、さらに信頼性の高いチッ
プ型半導体磁器部品を製作することができる。また対向
電極33の面積を広く取ることが可能となり、容量を増
大させることができる。
Thus, in this embodiment, the groove 32
Since the grain boundary insulating treatment is performed after the formation of the holes a, 32b and the holes 37, and the glass insulating layer 35 is applied by printing, the grain boundary insulating semiconductor ceramic substrate 36 is used as a split groove in the subsequent step. Even when cut, the counter electrodes 33 are reliably insulated, the counter electrodes 33 and the external connection electrodes 34 are also reliably insulated, and the external connection electrodes 34 are also reliably insulated. Furthermore, a highly reliable chip-type semiconductor ceramic component can be manufactured. Further, the area of the counter electrode 33 can be widened, and the capacitance can be increased.

【0053】図17は本発明に係るチップ型半導体磁器
部品及びその製造方法のさらに別の実施例を示した模式
的斜視図である。
FIG. 17 is a schematic perspective view showing still another embodiment of the chip type semiconductor ceramic component and the manufacturing method thereof according to the present invention.

【0054】本実施例に係るチップ型半導体部品では、
図17に示したように、外部接続電極34と対向電極3
3との接続側角部と反対側角部近傍を切除し、また、対
向電極33が形成された両主面間の角部に溝32aを、
および外部接続電極34の両側角部に孔37を形成して
いる。
In the chip type semiconductor component according to this embodiment,
As shown in FIG. 17, the external connection electrode 34 and the counter electrode 3
3 is cut off in the vicinity of the corner on the side opposite to the corner on the side of connection with 3, and a groove 32a is formed in the corner between both main surfaces on which the counter electrode 33 is formed.
Also, holes 37 are formed at both corners of the external connection electrode 34.

【0055】このように本実施例にあっては、溝32
a、32b及び孔37を形成した後に粒界絶縁化処理を
施しているので、溝32aを割り溝として粒界絶縁型半
導体磁器基板36を後の工程で切断しても、対向電極3
3間は確実に絶縁され、対向電極33と外部接続電極3
4間においても確実に絶縁化され、さらに外部接続電極
34間も確実に絶縁され、信頼性の高いチップ型半導体
磁器部品を製作することができる。また実施例7に比
べ、対向電極33の面積を広く取ることが可能となり、
容量を増大させることができる。
Thus, in this embodiment, the groove 32
Since the grain boundary insulating treatment is performed after the formation of the holes a, 32b and the holes 37, even if the grain boundary insulating semiconductor ceramic substrate 36 is cut in a later step by using the groove 32a as a split groove, the counter electrode 3
3 is surely insulated, and the counter electrode 33 and the external connection electrode 3
It is possible to manufacture a highly reliable chip-type semiconductor porcelain component because insulation is surely made between the four parts and also between the external connection electrodes 34. Further, as compared with the seventh embodiment, the area of the counter electrode 33 can be increased,
The capacity can be increased.

【0056】[0056]

【発明の効果】以上の説明により明らかなように、上記
した請求項(1)、(5)、(9)及び(11)のチッ
プ型半導体磁器部品にあっては、外部接続電極が形成さ
れた側面間の各部が切削されて凹部が形成されており、
または前記凹部に加えて外部接続電極と対向電極との接
続側各部と反対側角部近傍に溝が形成されており、また
は、前記凹部に加えて対向電極が形成された両主面間の
角部が切削されて凹部が形成されており、または前記凹
部及び前記溝に加えて対向電極が形成された両主面間の
角部が切削されて凹部が形成されてるので、これら凹部
及び溝の部分において絶縁性が確保される。
As is apparent from the above description, in the chip-type semiconductor ceramic component according to the above-mentioned claims (1), (5), (9) and (11), the external connection electrode is formed. Each part between the side surfaces is cut to form a recess,
Or, in addition to the concave portion, a groove is formed in the vicinity of a corner on the side opposite to the connection side between the external connection electrode and the counter electrode, or a corner between both main surfaces in which the counter electrode is formed in addition to the concave portion. The part is cut to form a recess, or the corner between both main surfaces on which the counter electrode is formed in addition to the recess and the groove is cut to form a recess. Insulation is secured in the part.

【0057】また請求項(2)、(6)、(10)及び
(12)の製造方法によれば、前記凹部及び前記溝が形
成された半導体磁器基板に、粒界絶縁化処理を施す工程
を含んでいるので、これら凹部及び溝の表面は確実に絶
縁処理される。
According to the manufacturing method of claims (2), (6), (10) and (12), the step of subjecting the semiconductor porcelain substrate having the recess and the groove formed to grain boundary insulation treatment. Therefore, the surfaces of these recesses and grooves are reliably insulated.

【0058】さらに請求項(3)、(7)及び(13)
のチップ型半導体磁器部品にあっては、前記凹部及び前
記溝にガラス絶縁層が形成されているので、信頼性がさ
らに向上するだけでなく、前記凹部及び前記溝を小さく
設計することが可能となり、対向電極等の面積を広くと
ることが可能となる。
Further, claims (3), (7) and (13)
In the chip type semiconductor porcelain component, since the glass insulating layer is formed in the recess and the groove, not only the reliability is further improved, but also the recess and the groove can be designed small. It is possible to increase the area of the counter electrode and the like.

【0059】また請求項(4)、(8)及び(14)の
製造方法によれば、前記粒界絶縁化処理を施した後、前
記溝内にガラス絶縁層を形成しているので、粒界絶縁化
処理のみを行なう場合よりもより一層絶縁性の確保が容
易となる。
Further, according to the manufacturing method of claims (4), (8) and (14), since the glass insulating layer is formed in the groove after the grain boundary insulating treatment is performed, It becomes easier to secure the insulation property than the case where only the field insulation treatment is performed.

【0060】従って表面実装が可能で、有効となる対向
電極面積を広く取得することでき、しかも信頼性の高い
生産効率の高いチップ型半導体磁器部品を容易に製造す
ることができる。
Therefore, surface mounting is possible, a large effective counter electrode area can be acquired, and a highly reliable chip-type semiconductor ceramic component with high production efficiency can be easily manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るチップ型半導体磁器部品の製造方
法の一実施例における一工程を示した模式的斜視図であ
る。
FIG. 1 is a schematic perspective view showing one step in one embodiment of a method for manufacturing a chip-type semiconductor ceramic component according to the present invention.

【図2】本発明に係るチップ型半導体磁器部品の製造方
法の一実施例における一工程を示した模式的斜視図であ
る。
FIG. 2 is a schematic perspective view showing one step in one embodiment of the method for manufacturing the chip-type semiconductor ceramic component according to the present invention.

【図3】本発明に係るチップ型半導体磁器部品の製造方
法の一実施例における一工程を示した模式的斜視図であ
る。
FIG. 3 is a schematic perspective view showing one step in one embodiment of the method for manufacturing a chip-type semiconductor ceramic component according to the present invention.

【図4】(a)、(b)は本発明に係るチップ型半導体
磁器部品の一実施例を示した模式的斜視図及び側面図で
ある。
4 (a) and 4 (b) are a schematic perspective view and a side view showing an embodiment of a chip type semiconductor ceramic component according to the present invention.

【図5】(a)、(b)は本発明に係るチップ型半導体
磁器部品の別の実施例を示した模式的斜視図及び側面図
である。
5 (a) and 5 (b) are a schematic perspective view and a side view showing another embodiment of the chip-type semiconductor ceramic component according to the present invention.

【図6】(a)、(b)は本発明に係るチップ型半導体
磁器部品のさらに別の実施例を示した模式的斜視図及び
側面図である。
6 (a) and 6 (b) are a schematic perspective view and a side view showing still another embodiment of the chip-type semiconductor ceramic component according to the present invention.

【図7】本発明に係るチップ型半導体磁器部品の製造方
法の別の実施例における一工程を示した模式的斜視図で
ある。
FIG. 7 is a schematic perspective view showing a step in another embodiment of the method for manufacturing the chip-type semiconductor ceramic component according to the present invention.

【図8】本発明に係るチップ型半導体磁器部品の製造方
法の別の実施例における一工程を示した模式的斜視図で
ある。
FIG. 8 is a schematic perspective view showing a step in another embodiment of the method for manufacturing a chip-type semiconductor ceramic component according to the present invention.

【図9】本発明に係るチップ型半導体磁器部品の製造方
法の別の実施例における一工程を示した模式的斜視図で
ある。
FIG. 9 is a schematic perspective view showing a step in another embodiment of the method for manufacturing the chip-type semiconductor ceramic component according to the present invention.

【図10】(a)、(b)は本発明に係るチップ型半導
体磁器部品の別の実施例を示した模式的斜視図及び側面
図である。
10 (a) and 10 (b) are a schematic perspective view and a side view showing another embodiment of the chip type semiconductor ceramic component according to the present invention.

【図11】(a)、(b)は本発明に係るチップ型半導
体磁器部品のさらに別の実施例を示した模式的斜視図及
び側面図である。
11A and 11B are a schematic perspective view and a side view showing still another embodiment of the chip-type semiconductor ceramic component according to the present invention.

【図12】本発明に係るチップ型半導体磁器部品の製造
方法のさらに別の実施例における一工程を示した模式的
斜視図である。
FIG. 12 is a schematic perspective view showing a step in yet another embodiment of the method for manufacturing a chip-type semiconductor ceramic component according to the present invention.

【図13】本発明に係るチップ型半導体磁器部品の製造
方法の別の実施例における一工程を示した模式的斜視図
である。
FIG. 13 is a schematic perspective view showing a step in another embodiment of the method for manufacturing the chip-type semiconductor ceramic component according to the present invention.

【図14】本発明に係るチップ型半導体磁器部品の製造
方法の別の実施例における一工程を示した模式的斜視図
である。
FIG. 14 is a schematic perspective view showing a step in another embodiment of the method for manufacturing the chip-type semiconductor ceramic component according to the present invention.

【図15】(a)、(b)は本発明に係るチップ型半導
体磁器部品の別の実施例を示した模式的斜視図及び側面
図である。
15 (a) and 15 (b) are a schematic perspective view and a side view showing another embodiment of the chip type semiconductor ceramic component according to the present invention.

【図16】(a)、(b)は本発明に係るチップ型半導
体磁器部品のさらに別の実施例を示した模式的斜視図及
び側面図である。
16 (a) and 16 (b) are a schematic perspective view and a side view showing still another embodiment of the chip-type semiconductor ceramic component according to the present invention.

【図17】本発明に係るチップ型半導体磁器部品の製造
方法の別の実施例を示した模式的側面図である。
FIG. 17 is a schematic side view showing another embodiment of the method for manufacturing a chip-type semiconductor ceramic component according to the present invention.

【図18】従来のチップ型半導体磁器部品を示した模式
的斜視図である。
FIG. 18 is a schematic perspective view showing a conventional chip type semiconductor ceramic component.

【図19】従来のチップ型半導体磁器部品を示した模式
的斜視図である。
FIG. 19 is a schematic perspective view showing a conventional chip-type semiconductor ceramic component.

【図20】従来のチップ型半導体磁器部品を示した模式
的斜視図である。
FIG. 20 is a schematic perspective view showing a conventional chip-type semiconductor ceramic component.

【符号の説明】[Explanation of symbols]

11、21、31 半導体磁器基板 12、22a、32a 溝(凹部) 22b、32b 溝 13、23、33 対向電極 14、24、34 外部接続電極 15、25、35 ガラス絶縁層 16、26、36 粒界絶縁型半導体磁器基板 37 孔 11, 21, 31 Semiconductor porcelain substrate 12, 22a, 32a Groove (recess) 22b, 32b Groove 13, 23, 33 Counter electrode 14, 24, 34 External connection electrode 15, 25, 35 Glass insulating layer 16, 26, 36 grains Field-insulating semiconductor porcelain substrate 37 holes

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】 粒界絶縁型半導体磁器基板の表裏両主表
面に対向電極が形成されたチップ型半導体磁器部品にお
いて、外部接続電極が形成された側面間の角部に凹部が
形成されていることを特徴とするチップ型半導体磁器部
品。
1. A chip-type semiconductor ceramic component in which opposing electrodes are formed on both front and back main surfaces of a grain boundary insulating semiconductor ceramic substrate, and recesses are formed at corners between side surfaces on which external connection electrodes are formed. Chip type semiconductor porcelain parts characterized by the above.
【請求項2】 表裏両主面に複数本の平行で表裏相対向
する溝が形成された半導体磁器基板に、粒界絶縁化処理
を施す工程を含んでいることを特徴とする請求項1記載
のチップ型半導体磁器部品の製造方法。
2. The method according to claim 1, further comprising a step of subjecting a semiconductor porcelain substrate having a plurality of parallel grooves facing the front and back sides to each other on the front and back main surfaces to grain boundary insulating treatment. For manufacturing a chip-type semiconductor porcelain component.
【請求項3】 凹部にガラス絶縁層が形成されている請
求項1記載のチップ型半導体磁器部品。
3. The chip type semiconductor ceramic component according to claim 1, wherein a glass insulating layer is formed in the recess.
【請求項4】 表裏両主面に複数本の平行で表裏相対向
する溝が形成された半導体磁器基板に、粒界絶縁化処理
を施した後、前記溝内にガラス絶縁層を形成する工程を
含んでいることを特徴とする請求項3記載のチップ型半
導体磁器部品の製造方法。
4. A step of forming a glass insulating layer in the groove after subjecting a semiconductor porcelain substrate having a plurality of parallel grooves facing the front and back sides to each other on the front and back main surfaces to grain boundary insulation treatment. The method for manufacturing a chip-type semiconductor ceramic component according to claim 3, further comprising:
【請求項5】 外部接続電極と対向電極との接続側角部
と反対側角部近傍に溝が形成されている請求項1記載の
チップ型半導体磁器部品。
5. The chip-type semiconductor porcelain component according to claim 1, wherein a groove is formed in the vicinity of a corner on the side opposite to the corner on the side of connection between the external connection electrode and the counter electrode.
【請求項6】 表裏両主面に複数本の平行で表裏相対向
する溝が形成されると共に、前記溝に直交する複数本の
表裏相対向しない溝が形成された半導体磁器基板に、粒
界絶縁化処理を施す工程を含んでいることを特徴とする
請求項5記載のチップ型半導体磁器部品。
6. A semiconductor porcelain substrate having a plurality of parallel grooves facing each other on the front and back sides and facing each other, and a plurality of grooves not intersecting with each other perpendicular to the grooves are formed on the semiconductor ceramic substrate. The chip-type semiconductor porcelain component according to claim 5, including a step of performing an insulation treatment.
【請求項7】 凹部及び溝にガラス絶縁層が形成されて
いる請求項5記載のチップ型半導体磁器部品。
7. The chip type semiconductor ceramic component according to claim 5, wherein a glass insulating layer is formed in the recess and the groove.
【請求項8】 表裏両主面に複数本の平行で表裏相対向
する溝が形成されると共に、前記溝に直交する複数本の
表裏相対向しない溝が形成された半導体磁器基板に、粒
界絶縁化処理を施した後、前記溝内にガラス絶縁層を形
成する工程を含んでいることを特徴とする請求項7記載
のチップ型半導体磁器部品の製造方法。
8. A grain boundary is formed on a semiconductor ceramic substrate in which a plurality of parallel grooves facing each other in the front and back sides are formed on both front and back main surfaces, and a plurality of grooves not intersecting the front and back sides orthogonal to the grooves are formed. 8. The method for manufacturing a chip-type semiconductor ceramic component according to claim 7, further comprising the step of forming a glass insulating layer in the groove after performing an insulating treatment.
【請求項9】 対向電極が形成された両主面間の角部に
凹部が形成されている請求項1記載のチップ型半導体磁
器部品。
9. The chip-type semiconductor ceramic component according to claim 1, wherein a recess is formed at a corner between both main surfaces on which the counter electrodes are formed.
【請求項10】 表裏両主面に複数本の平行で表裏相対
向する溝が形成されると共に、これら溝間に複数個の孔
が形成された半導体磁器基板に、粒界絶縁化処理を施す
工程を含んでいることを特徴とする請求項9記載のチッ
プ型半導体磁器部品の製造方法。
10. A grain boundary insulating treatment is applied to a semiconductor porcelain substrate having a plurality of parallel grooves facing each other and facing each other and having a plurality of holes formed between the grooves. The method for manufacturing a chip-type semiconductor ceramic component according to claim 9, which includes a step.
【請求項11】 対向電極が形成された両主面間の角部
に凹部が形成されている請求項5記載のチップ型半導体
磁器部品。
11. The chip-type semiconductor ceramic component according to claim 5, wherein a recess is formed at a corner between both main surfaces on which the counter electrodes are formed.
【請求項12】 表裏両主面に複数本の平行で表裏相対
向する溝が形成されると共に、前記溝に直交する複数本
の表裏相対向しない溝が形成され、さらに表裏相対向す
る前記溝間に複数個の孔が形成された半導体磁器基板
に、粒界絶縁化処理を施す工程を含んでいることを特徴
とする請求項11記載のチップ型半導体磁器部品の製造
方法。
12. A plurality of parallel grooves that face each other and face each other are formed on both main surfaces of the front and back, and a plurality of grooves that are orthogonal to each other and do not face each other are formed. The method of manufacturing a chip-type semiconductor ceramic component according to claim 11, further comprising a step of subjecting a semiconductor ceramic substrate having a plurality of holes formed therein to grain boundary insulation treatment.
【請求項13】 凹部及び溝にガラス絶縁層が形成され
ている請求項9または請求項11記載のチップ型半導体
磁器部品。
13. The chip type semiconductor ceramic component according to claim 9, wherein a glass insulating layer is formed in the recess and the groove.
【請求項14】 溝及び孔が形成された半導体磁器基板
に、粒界絶縁化処理を施した後、前記溝内及び前記孔内
にガラス絶縁層を形成する工程を含んでいることを特徴
とする請求項13記載のチップ型半導体磁器部品の製造
方法。
14. A step of forming a glass insulating layer in the groove and in the hole after subjecting a semiconductor ceramic substrate having the groove and the hole to grain boundary insulation treatment. The method for manufacturing a chip-type semiconductor ceramic component according to claim 13.
JP7690192A 1992-03-31 1992-03-31 Chip-shaped semiconductor porcelain component and its manufacture Pending JPH05283271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7690192A JPH05283271A (en) 1992-03-31 1992-03-31 Chip-shaped semiconductor porcelain component and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7690192A JPH05283271A (en) 1992-03-31 1992-03-31 Chip-shaped semiconductor porcelain component and its manufacture

Publications (1)

Publication Number Publication Date
JPH05283271A true JPH05283271A (en) 1993-10-29

Family

ID=13618571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7690192A Pending JPH05283271A (en) 1992-03-31 1992-03-31 Chip-shaped semiconductor porcelain component and its manufacture

Country Status (1)

Country Link
JP (1) JPH05283271A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100865183B1 (en) * 2005-01-31 2008-10-23 캐논 가부시끼가이샤 Semiconductive element, ink jet head substrate and manufacturing method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100865183B1 (en) * 2005-01-31 2008-10-23 캐논 가부시끼가이샤 Semiconductive element, ink jet head substrate and manufacturing method therefor
US7591071B2 (en) 2005-01-31 2009-09-22 Canon Kabushiki Kaisha Manufacturing Method of Semiconductive Element and Ink Jet Head Substrate

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