JPH0528115U - Emitter feedback type differential 1x gain amplifier circuit - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To realize an emitter feedback type differential 1x gain amplifier circuit with stable gain that is not easily affected by the IC manufacturing process. [Structure] Transistors Q1 and Q2 and a resistor RE whose one end is connected to the emitters of these two transistors, respectively.
1, RE2 and an emitter feedback type differential stage consisting of a current source IO connected to the other ends of these two resistors RE1 and RE2, a negative side power source VEE connected to the other end of the current source IO, and its collector The positive side power source Vcc has its bases connected to resistors R1 and R2, respectively, and the positive side power source Vcc has its load resistors RL1 and
A load circuit composed of transistors Q3 and Q4 connected to RL2 and load resistors RL1 and RL2 having the other ends connected to the collectors of transistors Q1 and Q2 of the emitter feedback type differential stage, and a transistor of the emitter feedback type differential stage. Q1, Q
It is composed of inputs Vin1 and Vin2 connected to the base 2 and outputs VOUT1 and VOUT2 taken from the connection point of the emitter feedback type differential stage and the load circuit.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to high accuracy gain of an emitter feedback type differential 1 × gain amplifier circuit.

[0002]

[Prior Art]

 FIG. 3 is a circuit diagram showing an example of a conventional emitter feedback type differential 1 × gain amplifier circuit. In FIG. 3, V CC is a positive power supply and V EE is a negative power supply. The emitters of the transistors Q1 and Q2 and the emitters of the two transistors Q1 and Q2 are connected to the emitters RE, respectively, and the other end of the two resistors RE is connected to the current source I0. A differential stage is constructed. The other end of the current source IO is connected to the negative power source. The inputs to the emitter feedback type differential stage are connected to the bases of the transistors Q1 and Q2, respectively. The load resistor RL is a load resistor, one end of which is connected to the positive power source and the other end of which is connected to the collectors of the transistors Q1 and Q2. The connection points between the load resistance RL and the emitter feedback type differential stage are outputs VOUT1 and VOUT2, respectively.

In such a configuration, the small signal gain G of the above circuit is given by the following equation. G = RL / [RE + re + {rb / (1 + hFE)} + (2kT / qIO) * 1 / {1 + 1 / hFE)} ² ] * {1 / (1 + 1 / hFE)} where rE: transistors Q1 and Q2 Emitter resistance rb: base resistance of transistors Q1 and Q2 T: absolute temperature hFE: forward current gain of transistors Q1 and Q2 k: Boltzmann constant q: electron charge amount. Here, if the resistance values RE and RL are sufficiently larger than rE of the transistors Q1 and Q2, G = (RL / RE) .multidot. (1 + 1 / hFE). If the resistance values RE and RL are made in the same IC manufacturing process, RL / RE will be almost constant and the gain will be stable, but if RE and RL cannot be made sufficiently large to speed up the amplifier. , The resistances RE, RL and re, rb, hFE, etc. are independently dispersed due to variations in the IC manufacturing process, so that the gain is also varied and the gain accuracy is lowered.

[0004]

[Problems to be solved by the device]

 The present invention has been made in view of the above problems of the prior art, and uses a resistor and a base-grounded transistor with a resistor attached to the base as a load of an emitter feedback type differential 1 × gain amplifier circuit. Therefore, it is an object of the present invention to provide an emitter feedback type differential 1 × gain amplifier circuit which has a stable gain and is hardly affected by the IC manufacturing process.

[0005]

[Means for Solving the Problems]

 The constitution of the present invention for solving the above-mentioned problems is to provide transistors Q1 and Q2, resistors RE1 and RE2 whose one ends are respectively connected to the emitters of these two transistors, and the other ends of these two resistors RE1 and RE2. An emitter feedback type differential stage consisting of a connected current source IO, a negative side power source VEE connected to the other end of the current source IO, its collector is a positive side power source VCC, and its base is a resistor R1. , R2 to the positive side power supply VCC, the emitters of which are connected to load resistors RL1 and RL2, respectively, and the collectors of the transistors Q1 and Q2 of the emitter feedback type differential stage are connected to the other ends. A load circuit comprising the connected load resistors RL1 and RL2; inputs Vin1 and Vin2 connected to the bases of the transistors Q1 and Q2 of the emitter feedback type differential stage; It is characterized in that it has a structure by the limiter feedback output VOU T1, taken out from the connection point of the differential stage and the load circuit VOUT2.

[0006]

[Action]

 According to the present invention, as the load circuit of the emitter feedback type differential gain amplifier circuit, a base-grounded transistor with a resistor and a load resistor are used. Therefore, the voltage drop due to the base-emitter voltage of the base grounded transistor and the added base resistance is caused by the emitter operation resistance, the emitter resistance, and the base resistance of the emitter feedback differential stage. Since the effect is compensated, the gain is not easily influenced by the fluctuation of the IC manufacturing process, and the manufacturing can be performed with high accuracy.

[0007]

【Example】

 Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a circuit configuration diagram showing an embodiment of an emitter feedback type differential 1 × gain amplifier circuit of the present invention. In FIG. 1, the same elements as those in FIG. 3 are designated by the same reference numerals and overlapping description is omitted. However, the difference between FIG. 1 and FIG. 3 is that the configuration of the load circuit in FIG. The power supply Vcc is composed of transistors Q3 and Q4 and load resistors RL1 and RL2 whose bases are connected to the power supply Vcc through resistors R1 and R2, respectively, and whose emitters are connected to load resistors RL1 and RL2, respectively. That is the point.

In such a configuration, the operation thereof is the same as that of FIG. 3 and thus the description thereof is omitted, but here, the gain of this circuit is obtained below. The transistors Q1 to Q4 have the same shape, and the base resistance rb, emitter resistance re, forward current gain hFE, and reverse saturation current Is are equal. Also regarding the resistance value, if RE1 = RE2 = RE, RL1 = RL2 = RL, and R1 = R2 = R, then Vin1−V0 = (I3 / hFE) · rb + I1 (re + RE) + as shown in FIG. (KT / q) .lnI4 / Is (1) Vin2-V0 = (I4 / hFE) .rb + I2 (re + RE) + (kT / q) .lnI4 / Is ... (2) VOUT1 = VCC- (I6 / hFE). (rb + R)-(kT / q) lnI6 / Is-I4 (RL + re) ... (3) VOUT2 = VCC- (I5 / hFE). (rb + R)-(kT / q) lnI5 / Is- I3 (RL + re) (4) I1 + I2 = I0 (5) I1 = I3 (1 + 1 / hFE) (6) I2 = I4 (1 + 1 / hFE) (7) I3 = I5 (1 + 1 / hFE) ... (8) I4 = I6 (1 + 1 / hFE) (9) is given. Using the above equations (1) to (9) and the small signal approximation of (kT / q) · lnI3 / I4 = (2kT / q) (I3−I4) / (I3 + I4), the small signal gain G is , G = (VOUT1-VOUT2) / (Vin1-Vin2) = RL + re + {1 / (1 + hFE) ■ rb + (kT / qI0) (1-3 / hFE) / [RE + re + {1 / (1 + hFE)) ■ rb + (kT / qI0) (1-2 / hFE)] + [(-1 / hFE) [RL + re + {1 / (1 + hFE) ■ rb + (kT / qI0) (1-3 / hFE)] + (1 / hFE) (1-2 / hFE) R] / [RE + re + {1 / (1 + hFE)) rb + (kT / qI0) (1-2 / hFE)] (10). In this equation (10), if the first term is designed as RE = RL, even if RE, RL, re, rb, hFE, etc. vary due to variations in the IC manufacturing process, they become almost equal to 1. If RE and RL are manufactured in the same process, RE = RL can always be realized. Also, the second term is R = RL + re + {1 / (1 + hFE) ■ rb + (kT / qI0) (1-3 / hFE), so that RE, RL, re, rb, hFE Even if there are variations, the value will be small. Thus, in FIG. 1, if the values R of the resistors R1 and R2 are designed as described above, it is possible to suppress the influence of variations in the IC manufacturing process and manufacture a differential gain amplifier with a gain of 1 with high accuracy. ..

Further, in the emitter feedback type differential 1 × gain amplifier circuit improved in FIG. 1, since the gain thereof is given by the equation (10), temperature coefficients such as RE, RL, re, rb, hFE, etc. However, the gain has less temperature dependence and has the effect of achieving a gain of 1 times with high accuracy in a wide temperature range.

FIG. 2 is a circuit diagram showing another embodiment of the emitter feedback type differential 1 × gain amplifier circuit of the present invention. The configuration shown in FIG. 2 has a configuration in which base ground transistors Q5 and Q6 are added between the differential stage and the load circuit of the emitter feedback type differential gain amplifier circuit of FIG. The emitters of the base-grounded transistors Q5 and Q6 are connected to the collectors of the transistors Q1 and Q2 in the differential stage, and the collectors of Q5 and Q6 are connected to the resistors RL1 and RL2 of the load circuit. The bases of Q5 and Q6 are connected to a low output impedance voltage source VB.

Here, the gain G of the emitter feedback type differential 1 × gain amplifier circuit with the base ground transistor shown in FIG. 2 is obtained in the same manner as that of FIG. That is, G = RL + re + {1 / (1 + hFE) ■ rb + (kT / qI0) (1-4 / hFE) / [RE + re + {1 / (1 + hFE) ■ rb + (kT / qI0) (1- 2 / hFE)] + [(-2 / hFE) [RL + re + {1 / (1 + hFE)] rb + (kT / qI0) (1-4 / hFE)] + (1 / hFE) (1-3 / hFE) R] / [RE + re + {1 / (1 + hFE) ■ rb + (kT / qI0) (1-2 / hFE)] (11) Therefore, in this case, R = 2 [RL + re + {1 By designing / (1 + hFE) * rb + (kT / qI0) (1-4 / hFE)], the same effect as the circuit of FIG. 1 can be obtained.

When N stages of base-grounded transistors are added, R = (N + 1). [RL + re + {1 / (1 + hFE) .rb + (kT / qI0) {1- (N + 3) By designing / hFE ■], the same effect can be obtained.

[0013]

[Effect of the device]

 As described above in detail with reference to the embodiments, according to the present invention, a base-grounded transistor with a resistor and a load resistor are used as a load circuit of an emitter feedback type differential 1 × gain amplifier circuit. It is configured. Therefore, the voltage drop between the base-emitter voltage of the base-grounded transistor and the added base resistance affects the effects of the emitter operation resistance, emitter resistance, and base resistance of the emitter feedback differential stage. Since the gain is compensated, the gain is not easily influenced by the fluctuation of the IC manufacturing process, the gain can be manufactured with high accuracy, and the gain temperature dependence is small. Can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of an emitter feedback type differential 1 × gain amplifier circuit of the present invention.

FIG. 2 is a circuit configuration diagram showing another embodiment of an emitter feedback type differential 1 × gain amplifier circuit of the present invention.

FIG. 3 is a circuit configuration diagram showing an example of a conventional emitter feedback type differential 1 × gain amplifier circuit.

[Explanation of symbols]

 IO Current source Q1 to Q4 Transistors R1, R2, RE1, RE2 Resistance RL1, RL2 Load resistance VCC Positive power supply VEE Negative power supply Vin1, Vin2 Input signal VOUT1, VOUT2 Output

Claims (1)

[Scope of utility model registration request] 1. Transistors Q1 and Q2, resistors RE1 and RE2 each having one end connected to the emitters of the two transistors, and a current source IO connected to the other ends of the two resistors RE1 and RE2. An emitter feedback type differential stage, a negative side power source VEE connected to the other end of the current source IO, its collector is a positive side power source VCC, and its base is the positive side via resistors R1 and R2, respectively. The power source Vcc has its emitters connected to load resistors RL1 and RL2, respectively, and transistors Q3 and Q4 are connected to the collectors of the emitter feedback type differential stage transistors Q1 and Q2. A load circuit composed of RL2, and the transistors Q1 and Q of the emitter feedback type differential stage
An emitter-feedback-type differential circuit characterized by comprising inputs Vin1 and Vin2 connected to the base 2 and outputs VOUT1 and VOUT2 taken out from the connection point of the emitter-feedback-type differential stage and the load circuit. Dynamic 1x gain amplifier circuit.