JPH05275991A - Phase comparator circuit - Google Patents

Abstract

PURPOSE:To provide the phase comparator of an optical frequency offset lock loop which is used in a transmission equipment or a coherent light measuring instrument on an optical wave communication network by detecting the sign of the frequency difference between first and second input signals. CONSTITUTION:If the output of a pulse number difference counting means 3 which subtracts the number of pulses of the second input signal from that of the first input signal to calculate the difference between them is larger than a prescribed upper limit value by an upper limit value detecting means 4 which compares the output of the means 3 with this upper limit value, a first switch 1 breaks the first input signal. If the output of the pulse number difference counting means 3 is smaller than a prescribed lower limit value by a lower limit value detecting means 5 which compares the output of the means 3 with this lower limit value, a second switch 2 breaks the second input signal. An analog signal conversion means 6 converts the output of the pulse number difference counting means 3 to an analog signal. Consequently, this circuit is operated as a phase frequency comparator(PFC) which outputs the output corresponding to the sign of the frequency difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparison circuit,
Especially, in the lightwave communication technology such as coherent optical communication and optical frequency multiplex communication, the phase comparison used for the optical frequency offset lock loop that can change the frequency with high accuracy based on the frequency of the frequency-stabilized master laser. Regarding the circuit.

[0002]

2. Description of the Related Art An optical frequency offset lock loop is considered to be an important component in lightwave communication technology.

FIG. 10 shows the structure of an optical frequency offset lock loop. The optical frequency offset lock loop shown in the figure includes optical fiber couplers 82 and 84 to which a laser is input.
A photoelectric converter 85 that detects a beat signal, a prescaler 86 that divides an input frequency by an accurate value and divides the frequency, a phase comparator circuit 88 that compares the phases of the output signals of the prescaler 86 and the synthesizer 87, and the frequency is fed back. It is composed of a loop filter 89 for controlling.

The output of the slave laser 81 is branched by the optical fiber coupler 82, and the branched one is output as output light. The other is mixed with the output of the master laser 83 by the optical fiber coupler 84. The signal mixed by the optical fiber coupler 84 is input to the photoelectric converter 85, and the beat signal is detected by the photoelectric converter 85. The frequency f _M of the master laser 83 is stabilized with reference to absorption lines of atomic molecules and optical resonators. The following methods are available for stabilizing the frequency of the master laser. i) Master laser 8 in a glass container containing atoms and molecules
The output light of No. 3 is input, and the injection current of the laser is controlled so that the intensity of the transmitted light becomes minimum. ii) The beam of atoms and molecules is irradiated with the output light of the master laser 83, and the injection current of the laser is controlled so that the intensity of fluorescence from the beam becomes maximum. iii) The output light of the master laser 83 is input to the Fabry-Perot resonator or the ring resonator, and the injection current and temperature of the laser are controlled so that the intensity of the transmitted light becomes maximum. iv) Confocal Fabry-Perot resonator with master laser 8
The output light of No. 3 is input, and the reflected light is returned to the master laser 83.

The beat signal is frequency-divided by the prescaler 86 and then phase-compared with the output signal of the synthesizer 87 in the phase comparison circuit 88. Loop filter 89
Indicates that the phase error signal output from the phase comparison circuit 88 is 0.
The frequency of the slave laser 81 is feedback-controlled so that For example, it is assumed that the instantaneous frequency f _L of the output light of the slave laser 81 is higher than the instantaneous frequency f _M of the output light of the master laser 83. In this case, the instantaneous frequency of the beat signal outputted from the photoelectric converter 85 is f _L -f _M, the instantaneous frequency of the output of the prescaler 86 is the _{(f L -f M) / K} . When the output frequency of the synthesizer 87 is f _S , the phase error signal output from the phase comparison circuit 88 is given by D {(f _L −f _M ) / K−f _S } t. However, D represents a coefficient (here, D> 0), and t represents time.

When the phase error signal is positive, the instantaneous frequency is (f _L -f _M ) / K> f _S , so the injection current of the slave laser 81 is increased and the output light of the slave laser 81 is increased. The instantaneous frequency f _{L of} is reduced. On the contrary, when the output of the phase error signal is negative, the instantaneous frequency is (f _L −f _M ) / K <f _S , so that the injection current of the slave laser 81 is decreased and the output light of the slave laser 81 is decreased. Increase the instantaneous frequency f _L of.

By such feedback control, the phase error signal has a value of 0 on average. At this time, (f _L −
Since f _M ) / K = f _S holds, the slave laser 81
The frequency of the output light is f _L = f _M + K · f _S. Similarly, if instantaneous frequency f _L <instantaneous frequency f _M , then f
_L = f _M · K · f _S.

Assuming that the frequency division ratio of the prescaler 86 is K and the frequency of the synthesizer 87 is f _S , the slave laser 81
Since the frequency f _M ± K · f _S, it is possible to change the frequency of the slave laser 81 with high precision by the frequency f _S.

In this optical frequency offset lock loop, the phase comparison circuit 88 is an important component. In a phase locked loop for normal electric signals, a double balanced mixer, an EX-OR gate, an RS flip, etc. are used as a phase comparison circuit. These are circuits that detect a phase difference of ± π in principle. When the phase difference between the input signals is Δφ, the phase comparison circuit 88 outputs a phase error signal proportional to the phase difference Δφ within a range of −π ≦ Δφ ≦ + π. When the range of ± π is exceeded, the output of the phase comparison circuit oscillates with a period of 2π.

On the other hand, a semiconductor laser or the like has a very large phase noise as compared with an ordinary oscillator for electric signals, so that it is not easy to detect the phase difference by the above phase comparison circuit.

FIG. 11 shows the structure of a conventional phase comparison circuit. The phase comparison circuit (Kuboki and Ohtsu, “Fr
equency Offset Locking of AlGaAs Semiconductor Las
ers ", IEEE J. Quantum Electron., QE-23, pp. 388-39
3, 1987, Ishida, “Lightwave Frequency Tracking wi
th a Tunable DBR Laser ", J. Lightwave Technol., 9, p
p. 1083-1093, 1991) can detect very wide phase. The phase comparison circuit shown in FIG.
1, a down counter 102, a full adder 103, an inverter 104 and a D / A converter 105.

The operation of the circuit shown in FIG. 10 is such that, in FIG. 10, the number of pulses of the input A which is an output obtained by dividing the beat signal by the prescaler 86 when used as the phase comparison circuit 88 of the optical frequency offset fock loop is increased. The input B, which is the output of the synthesizer 87, counted by the counter 101
The number of pulses is counted by the down counter 102, and the results are added by the full adder 103 and converted into an analog voltage by the D / A converter 105. At that time, when the output of the full adder 103 is ALL 0 “000 ... 000”, the most significant bit (MSB) is set to the inverter 104 so that the bipolar output voltage of the D / A converter 105 becomes 0.
To flip.

FIG. 12 shows the input / output characteristics of the conventional phase comparator. In the figure, the vertical axis shows the output of the phase comparison circuit, and the horizontal axis shows the difference Δφ≡Δφ _A −Δφ _B (rad between the phase difference φ _A of the input _A and the phase difference φ _B of the input B shown in FIG. ) Is shown. The phase comparison circuit shown in FIG. 11 outputs a phase error signal proportional to the phase difference Δφ in the range of −2 ^N π ≦ Δφ ≦ + 2 ^N π. However, the output change is not continuous but changes stepwise in steps of 2π as shown by a '. The conventional phase comparator has a substantially sawtooth type input / output characteristic as shown in FIG. Further, in FIG. 11, N is an up counter 101, a down counter 102, a full adder 10
3 represents the number of bits of the D / A converter 105. In the example of FIG. 9, N = 8 bits. Although this phase comparison circuit has a resolution of 2π for a phase difference, it can detect phase fluctuations in a very wide range of ± 2 ^N π.

Assuming that the frequency of the input A is f _A and the frequency of the input B is f _B , in the case of a phase locked loop using a phase comparison circuit having no frequency difference detection function, the output of the phase comparison circuit is | f _A It vibrates at a frequency of −f _B | / 2 ^N. If the frequency difference in the initial state is smaller than a certain value determined by the characteristics of the loop, the loop filter 89 responds and feedback control is performed to reduce the frequency difference f _A −f _B , and finally the synchronization state is changed. Establish. When the frequency difference in the initial state is large, the output of the phase comparison circuit becomes 0 on average, and the loop filter 89 does not respond. The maximum frequency difference that enables this feedback control operation is the frequency pull-in range. When there is a frequency detection function, the phase comparison circuit outputs a DC value even if the frequency difference in the initial state is large. Therefore, the feedback control operation can be performed so that the loop filter 89 responds to reduce the frequency difference. Therefore, the frequency pull-in range becomes wider than that without the frequency difference detection function. In general, it is known that a phase frequency comparator (PFC) capable of detecting whether the frequency difference is positive or negative is effective for further widening the frequency pull-in range of the phase locked loop.

[0015]

However, the conventional phase comparison circuit described above has a problem that the phase fluctuation can be detected but the phase frequency comparison operation cannot be performed.

The present invention has been made in view of the above points,
An object of the present invention is to provide a phase frequency comparator (PFC) type phase comparison circuit capable of widening the frequency pull-in range of an optical frequency offset lock loop.

[0017]

FIG. 1 shows the first principle configuration of the present invention.

According to the present invention, a pulse number difference counting means 3 for calculating a difference obtained by subtracting the number of pulses of the second input signal from the number of pulses of the first input signal, and an output of the pulse number difference counting means 3. The upper limit value detecting means 4 for comparing a predetermined upper limit value, the lower limit value detecting means 5 for comparing the output of the pulse number difference counting means 3 with a predetermined lower limit value, and the upper limit value detecting means 4 for the pulse number difference counting means 3 If the output is larger than the predetermined upper limit value, the first
When the output of the pulse number difference counting means 3 by the lower limit value detecting means 5 is smaller than a predetermined lower limit value, the second switch 1 which disconnects the second input signal is disconnected. 2 switches 2 and an analog signal conversion means 6 for converting the output of the pulse number difference counting means 3 into an analog signal,
Whether the frequency difference between the first input signal and the second input signal is positive or negative is detected.

FIG. 2 shows a second principle configuration of the present invention.
In the figure, the same components as those in FIG. 1 are designated by the same reference numerals.

According to the present invention, a pulse number difference counting means 3 for calculating a difference obtained by subtracting the number of pulses of the second input signal from the number of pulses of the first input signal, and an output of the pulse number difference counting means 3. The upper limit value detecting means 4 for comparing a predetermined upper limit value, the lower limit value detecting means 5 for comparing the output of the pulse number difference counting means 3 with a predetermined lower limit value, and the upper limit value detecting means 4 for the pulse number difference counting means 3 If the output is larger than the predetermined upper limit value, the first
When the output of the pulse number difference counting means 3 by the lower limit value detecting means 5 is smaller than a predetermined lower limit value, the second switch 1 which disconnects the second input signal is disconnected. And a switch 2 for detecting the frequency difference between the first input signal and the second input signal.

FIG. 3 is a block diagram of the third principle of the present invention.
In the figure, the same components as those in FIG. 1 are designated by the same reference numerals.

According to the present invention, the pulse number difference counting means 3 for calculating the difference obtained by subtracting the number of pulses of the second input signal from the number of pulses of the first input signal and the output of the pulse number difference counting means 3 are calculated. The analog signal conversion means 6 for converting into an analog signal, the upper limit value detection means 7 for comparing the output of the analog signal conversion means 6 with a predetermined upper limit value, and the output of the analog signal conversion means 6 for comparison with a predetermined lower limit value Lower limit value detection means 8 and upper limit value detection means 7 when the output of the analog signal conversion means 6 is larger than a predetermined upper limit value, the first switch 1 for disconnecting the first input signal, and the analog signal conversion A second switch 2 for disconnecting the second input signal when the output of the means 6 is smaller than a predetermined lower limit value, the frequency difference between the first input signal and the second input signal Positive / negative is detected.

[0023]

The phase comparator circuit according to the present invention provides an upper limit value and a lower limit value for the phase difference, and when the phase difference exceeds these values, one of the inputs is switched off by a switch to respond to the positive or negative of the frequency difference. It operates as a phase frequency comparator (PFC) that outputs the output. As a result, the output from the phase comparison circuit outputs a positive voltage or a negative voltage having a substantially constant value according to the phase frequency difference, so that the frequency pull-in range of the optical frequency offset lock group can be widened.

[0024]

FIG. 4 shows the structure of a phase comparison circuit according to the first embodiment of the present invention. In the figure, the same components as those in FIG. 11 are designated by the same reference numerals. The phase comparison circuit shown in the figure has AND gates 106 and 107 for disconnecting inputs by logical product, an up counter 101 and a down counter 1 for counting the difference in pulse number.
02, full adder 103, inverter 104, NAND gate 108 for detecting an upper limit value, OR gate 109 for detecting a lower limit value, and D / A converter 105.

AND gate 1 for input A and input control signal C
In addition to 06, the number of pulses of the logical product output is input to the up counter 101. The up counter 101 counts the number of pulses. In addition, input B and input control signal D are
In addition to the ND gate 107, the number of pulses of the logical product output is input to the down counter 102. Down counter 1
02 counts the number of input pulses. The outputs of the up counter 101 and the down counter 102 are added to the full adder 103.
To the D / A converter 105. At that time, the most significant bit (MSB) is inverted by the inverter 104. When all the upper M (≦ N) bits of the output (inversion of MSB) of full adder 103 become 1, the output of NAND gate 108 (input control signal C) becomes 0. On the other hand, the output of the full adder 103 (MS
When all the upper M (≦ N) bits of B inversion) become 0, the output (input control signal D) of the OR gate 109 becomes 0. The D / A converter 105 converts a digital signal into an analog voltage.

The specific circuit operation of the phase comparison circuit of FIG. 4 will be described below.

The frequency comparison operation will be described with N = 8 and M = 7. When the frequency of the input A is higher than the frequency of the input B, the output (MSB inversion) of the full adder 103 is added with the number of pulses and becomes “11111110”, the input control signal C becomes 0, and the addition is performed. Stops. Next, the value of the down counter 102 is decreased by 1 by the input B, and the output (MSB inversion) of the full adder 103 is “11”.
111101 ″ and the input control signal D becomes 1.
Thus, the D / A converter 105 outputs a positive voltage having a substantially constant value.

When the frequency of the input A is lower than the frequency of the input B, the output of the full adder 103 (MSB inversion) becomes "00000001" by subtracting the number of pulses, and the input control signal D becomes 0. And the subtraction stops. Next, the value of the up counter 101 is increased by 1 by the input A, and the output (MSB inversion) of the full adder 103 is "0.
0000010 ", the input control signal D becomes 1. In this way, the D / A converter 105 outputs a substantially constant negative voltage.

Table 1 shows the outputs of the up counter 101, the down counter 102, the full adder 103, and the MSB inverted.

[0030]

[Table 1] In the above table, * indicates full adder 1 at the timing immediately before that.
Since the upper 7 bits of the MSB inversion of the output of 03 becomes 1, the output of the NAND gate 108 becomes 0 and the output of the AND gate 106 also becomes 0.
01 indicates that the pulse was not counted.

FIG. 5 shows the input / output characteristics of the phase locked loop circuit according to the first embodiment of the present invention. In the figure, the vertical axis represents the output of the phase locked loop, and the horizontal axis represents the phase difference (rad) between the input A and the input B. As shown in the figure, according to the first embodiment of the present invention, the waveform is not saw-tooth like the conventional configuration,
A negative output changes to a positive output depending on the frequency difference between 2 × (2 ^N −2 ^{N−M + 1} +2) π.

FIG. 6 shows a configuration in which the phase comparison circuit and the loop filter of the first embodiment of the present invention are connected. In the figure, the phase comparison circuit 88 of the present embodiment is connected to a loop filter 120 which is an analog filter. Further, the output of the loop filter 120 is input to an adder 121 together with a bias voltage, and as a result of addition, injection current control is performed. It is output as a signal.

FIG. 7 shows the configuration of the phase comparison circuit according to the second embodiment of the present invention. In the figure, parts that are the same as the parts shown in FIG. 4 are given the same reference numerals, and descriptions thereof will be omitted. The phase comparison circuit shown in the figure has AND gates 106, 1 that disconnect the input by logical product.
07, an up counter 10 that counts the difference in the number of pulses
1, a down counter 102, a full adder 103, an inverter 104, a NAND gate 108 for detecting an upper limit value, and an OR gate 109 for detecting a lower limit value.

In the operation of this embodiment, the input A and the input B are input, and the up counter 101 and the down counter 10
The operation of counting the number of pulses by 2 and outputting from the full adder 103 is the same as that of the first embodiment.
Of the outputs of the full adder 103, the output of which the MSB is inverted by the inverter 104 is output to the digital processing loop filter without using the D / A converter 105 used in the embodiment.

The full adder 103, inverter, NA
A configuration in which the functions of the ND circuit 108 and the OR gate 109 are realized using software is also possible.

An example represented by software will be shown below.

Step 0: 0 → W, 1 / τ → a, exp (−T / τ)
→ b Step 1: Read the output X of the up counter 101 Step 2: Read the output Y of the down counter 102 Step 3: X + Y → Z Step 4: Z + 10000000 → Z Step 5: IF Z> 11111101 THEN
0 → A ELSE → A Step 6: Output A to AND gate 106 Step 7: IF Z <00000010 THEN
0 → B ELSE 1 → B Step 8: Output B to AND gate 107 Step 9: a × Z + b × W → W Step 10: Output W to D / A converter Step 11: Return to Step 1 Software described above In the example, τ represents the time constant of the filter, and T represents the sampling period. Also, step 3
Corresponds to the full adder 103, step 4 is to the inverter 104, step 5 is to the NAND gate 108,
Step 7 corresponds to the OR gate 109 and step 9 corresponds to the loop filter.

FIG. 8 shows a configuration in which the phase comparison circuit and the loop filter of the second embodiment of the present invention are connected. In the figure, τ
Is a time constant of the filter, T is a sampling period, and corresponds to a and b in step 9 when the present embodiment is realized by the above software. In step 9, a is 1 / τ and b is exp (−T / τ). In the figure, the phase comparison circuit 88 of this embodiment is the multiplier 1
The digital filter 122 includes 23, 126, an adder 124, and a delay device 125. The phase comparison circuit of the present embodiment is connected to the loop filter 122, and the output of the loop filter 122 is input to the D / A converter 127, converted into an analog signal, input to the adder 128 together with the bias voltage, and added. As a result, it is output as an injection control signal.

FIG. 9 shows the configuration of the phase comparison circuit according to the third embodiment of the present invention. In the figure, the same components as those of FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.

The configuration of this embodiment is the same as that of the first embodiment except that the comparator 11 for detecting the upper limit value and the lower limit value is used.
1, 113, an upper limit voltage generation circuit 110, and a lower limit voltage generation circuit 112 are added.

In this embodiment, the analog output voltage of the D / A converter 105 and the output voltage of the upper limit voltage generating circuit 110 are input to the comparator 111. The comparator 111 is
The analog output voltage of the D / A converter 105 is compared with the output voltage of the upper limit voltage generation circuit 110, and the input control signal C is output. When the output voltage of the D / A converter 105 is higher, the input control signal C which is the output of the comparator 111 becomes 0, the output of the AND gate 106 becomes 0, and the up counter 101 stops counting pulses. ..

On the other hand, the analog output voltage of the D / A converter 105 and the output voltage of the lower limit voltage generation circuit 112 are input to the comparator 113. Comparator 113 is D / A
Analog output voltage of converter 105 and lower limit voltage generation circuit 1
The output voltages of 12 are compared, and the input control signal D is output.
When the output voltage of the D / A converter 105 is smaller, the input control signal D, which is the output of the comparator 113, becomes 0, the output of the AND gate 107 becomes 0, and the down counter 102 stops counting pulses. ..

As described above, the phase difference has the predetermined upper limit value and the lower limit value, and when the phase difference exceeds these values, one of the inputs is cut off to make the phase frequency difference positive or negative. The corresponding output is obtained.

[0044]

As described above, according to the present invention, the phase comparison circuit can be used as a phase comparison circuit of a transmission device in a lightwave communication network or an optical frequency offset lock loop in a coherent optical measuring device.

[Brief description of drawings]

FIG. 1 is a first principle configuration diagram of the present invention.

FIG. 2 is a second principle configuration diagram of the present invention.

FIG. 3 is a third principle configuration diagram of the present invention.

FIG. 4 is a configuration diagram of a phase comparison circuit according to a first embodiment of the present invention.

FIG. 5 is a diagram showing input / output characteristics of the phase locked loop circuit according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram in which the phase comparison circuit and the loop filter of the first exemplary embodiment of the present invention are connected.

FIG. 7 is a configuration diagram of a phase comparison circuit according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram in which a phase comparison circuit according to a second embodiment of the present invention and a loop filter are connected.

FIG. 9 is a configuration diagram of a phase comparison circuit according to a third embodiment of the present invention.

FIG. 10 is a configuration diagram of an optical frequency offset lock loop.

FIG. 11 is a configuration diagram of a conventional phase comparison circuit.

FIG. 12 is a diagram showing input / output characteristics of a conventional phase comparator.

[Explanation of symbols]

 1 1st switch 2 2nd switch 3 Pulse counting means 4, 7 Upper limit value detection means 5, 8 Lower limit value detection means 6 Analog signal conversion means 81 Slave laser 82 Optical fiber coupler 83 Master laser 84 Optical fiber coupler 85 Photoelectric conversion Unit 86 prescaler 87 synthesizer 88 phase comparator circuit 89 loop filter 101 up counter 102 down counter 103 full adder 104 inverter 105 D / A converter 106 AND gate 107 AND gate 108 NAND gate 109 OR gate 110 upper limit voltage generation circuit 111 comparator 112 Lower limit voltage generation circuit 113 Comparator 120 Analog loop filter 121 Adder 122 Digital loop filter 123 Multiplier 124 Adder 125 Delay device 126 Multiplication Unit 127 D / A converter 128 Adder

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04L 27/14 Z 9297-5K

Claims (3)

[Claims] 1. A pulse number difference counting means for calculating a difference obtained by subtracting the number of pulses of the second input signal from the number of pulses of the first input signal, and an output of the pulse number difference counting means and a predetermined upper limit. An upper limit value detecting means for comparing values, a lower limit value detecting means for comparing an output of the pulse number difference counting means with a predetermined lower limit value, and an output of the pulse number difference counting means for the upper limit value by the upper limit value detecting means. If the output of the pulse number difference counting means is smaller than the lower limit value by the first switch for disconnecting the first input signal and the lower limit value detecting means, A second switch for disconnecting the second input signal; and an analog signal conversion means for converting the output of the pulse number difference counting means into an analog signal, the first input signal and the second input signal Phase comparison circuit characterized by detecting the positive and negative of the frequency difference of . 2. A pulse number difference counting means for calculating a difference obtained by subtracting the number of pulses of the second input signal from the number of pulses of the first input signal, an output of the pulse number difference counting means, and a predetermined upper limit. An upper limit value detecting means for comparing values, a lower limit value detecting means for comparing an output of the pulse number difference counting means with a predetermined lower limit value, and an output of the pulse number difference counting means for the upper limit value by the upper limit value detecting means. If the output of the pulse number difference counting means is smaller than the lower limit value by the first switch for disconnecting the first input signal and the lower limit value detecting means, A second switch that disconnects the second input signal, and detects whether the frequency difference between the first input signal and the second input signal is positive or negative. 3. A pulse number difference counting means for calculating a difference obtained by subtracting the number of pulses of the second input signal from the number of pulses of the first input signal, and an output of the pulse number difference counting means into an analog signal. An analog signal converting means for converting, an upper limit value detecting means for comparing an output of the analog signal converting means with a predetermined upper limit value, and a lower limit value detecting means for comparing an output of the analog signal converting means with a predetermined lower limit value. A first switch for disconnecting the first input signal when the output of the analog signal converting means by the upper limit value detecting means is larger than a predetermined upper limit value; and the analog signal converting by the lower limit value detecting means. A second switch for disconnecting the second input signal when the output of the means is smaller than a predetermined lower limit value, and a second switch for disconnecting the frequency difference between the first input signal and the second input signal. Characterized by detecting positive and negative The phase comparator circuit.