JP3164160B2 - Frequency synthesizer and pulse train generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer in a microwave band and a pulse train generator for generating a plurality of pulses from one pulse in the frequency synthesizer.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a configuration example of a conventional frequency synthesizer. In the figure, a reference signal input from an input terminal 41 is input to one input terminal of a phase comparator 42, and the output thereof is
Is input to a frequency control terminal of a voltage controlled oscillator (VCO) 44 through The output of the voltage controlled oscillator 44 is taken out from the output terminal 45 as a microwave output and is input to the variable frequency divider 46. The signal whose frequency has been frequency-divided by the variable frequency divider 46 is fed back to the other input terminal of the phase comparator 42 to form a phase locked loop.

As described above, the frequency of the output of the voltage controlled oscillator 44 is divided, the phase is compared with the reference signal, and an output proportional to the error is given as the frequency control input of the voltage controlled oscillator 44 via the loop filter 43. With this configuration, a highly stable microwave output synchronized with the reference signal can be extracted from the output terminal 45. That is, for example, even if the voltage controlled oscillator 44 has jitter whose oscillation frequency or oscillation phase fluctuates finely on the time axis, feedback is applied in a direction in which the jitter is suppressed by this phase locked loop.
In the synchronized state, a microwave output with little jitter (low phase noise) can be obtained at the output terminal 45.

Since the microwave output frequency has a relation of microwave output frequency = reference signal frequency × division ratio, the switching of the microwave output frequency is achieved by switching the frequency division ratio N of the variable frequency divider 46. Will be possible. Here, since the division ratio N is an integer, the resolution as a frequency synthesizer, that is, the frequency variable minimum step width is equal to the reference signal frequency. Therefore, in order to reduce the frequency variable minimum step width, the reference signal frequency may be lowered and the frequency division ratio N may be set to a large value.

[0005]

However, when the reference signal frequency is lowered, the same jitter becomes a relatively small value when converted into a phase angle, and the detection sensitivity of the phase comparator deteriorates in effect. And the phase noise of the frequency synthesizer increases. It is experimentally known that when the reference signal frequency is halved, the phase noise is degraded by 6 dB (T. Ohira et al: "Dual-chip GaAs monolit
hic integration Ku-band phase-locked-loop microwav
e synthesizer ", IEEE Trans. MicrowaveTheory & Tec
h., vol. 38, no. 9, pp. 1204-1209, Sept. 1990.).

That is, in a frequency synthesizer,
By reducing the frequency division ratio of the variable frequency divider and increasing the reference signal frequency to be compared by the phase comparator, the phase noise is reduced, but the minimum frequency variable step width is increased. On the other hand, when obtaining the same output frequency, the frequency division ratio of the variable frequency divider is increased to reduce the frequency variable minimum step width, and the reference signal frequency is reduced, but the phase noise increases. Thus, there is a trade-off between the reduction of the phase noise and the reduction of the frequency variable minimum step width in the frequency synthesizer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a frequency synthesizer capable of reducing a frequency variable minimum step width while keeping a reference signal frequency input to a phase comparator high, and a pulse train generator used therefor.

[0008]

A pulse according to claim 1
The column generator captures the input pulse at one terminal and
Logical OR of input pulse and pulse input to the other terminal
And outputs a logical sum pulse of the logical sum and a predetermined delay.
And input it to the other terminal.
A pulse train generation loop that fills the pulse and a pulse train
Count the number of pulses traversing the raw loop and reach the desired value.
After a predetermined time elapses after the next input pulse is given
Mask the pulse train going around the pulse train generation loop until
Pulse train interrupting means.

According to a second aspect of the present invention, there is provided a pulse train generator comprising:
A pulse is input to one terminal, and the input pulse and the other
The first one that performs a NOR operation with the pulse input to the terminal
NOR circuit means for providing a predetermined delay to the input pulse
Output from the first delay means and the first NOR circuit
A NOR pulse and a pulse output from the first delay means.
And the logical sum of the pulse and the logical OR pulse
Second negating-or means, and second negating-or means
A predetermined delay to the NOR pulse output from
A second input to the other terminal of the first NOR circuit
And delay means.

The frequency synthesizer according to claim 3 is
The oscillation frequency is controlled by the control signal input to the frequency control terminal.
A voltage whose number is controlled and outputs a signal of the set frequency
The control oscillator and the output signal of the voltage-controlled oscillator
And the frequency of the corresponding frequency according to the set dividing ratio.
Variable frequency divider to convert to pulse and output pulse of variable frequency divider
Output the signal corresponding to the phase difference between the reference signal and the reference signal
The output signals of the comparator and phase comparator are
Loop filter with a feedback connection to the number control terminal.
In a wave number synthesizer, a variable frequency divider and a phase comparator
Generating a pulse train according to claim 1 or 2.
And one output pulse of the variable frequency divider is input.
In particular, it is a configuration that generates a plurality of pulses.
Sign.

[0011]

The pulse train generator according to claim 1 is a pulse train generator.
New pulse generated from input pulse by generation loop
And make a pulse train including the input pulse. However,
The delay time to make the next pulse from the force pulse
It is difficult to make the relationship an integral multiple of the period.
If left as is, the newly generated pulse fills the interval between input pulses.
The pulse train is exhausted. So the pulse
The column interrupting means controls the pulse flow of the pulse train generation loop.
Temporarily mask, always new pulse based on input pulse
To generate a constant pulse train
Can be

According to a second aspect of the present invention, there is provided a pulse train generator comprising:
OR, first delay and second NOT
The width determined by the delay time of the first delay means by the logical sum means
The first pulse with is generated. Hereinafter, the first negation
OR means, second NOT OR means, and second delay means
First, a pulse train generation loop composed of stages
Generate a new pulse based on the generated pulse
A pulse train is created. Here, via the first delay means
When an input pulse is given to the second NOR circuit,
Reset to the pulse train generated by the pulse train generation loop
Is applied, and the above-mentioned pulse
The column generation process is repeated. Therefore, constant pal
Can be generated.

[0013] The frequency synthesizer according to claim 3 is
Even if the division ratio of the variable divider is set to a large value,
Variable frequency divider by the pulse train generator according to claim 1 or 2
New M pulses are buried between the output pulses of
M + 1 pulse train for one output pulse of frequency divider
Become. At this time, the frequency division ratio is substantially reduced to 1 / (M + 1).
And the reference signal
The frequency can be set higher and the frequency
The variable minimum step width is 1 / (M + 1) of the reference signal frequency.
It becomes possible to make it smaller. That is, the phase comparator
Frequency can be maintained while the input reference signal frequency is kept high
The variable minimum step width can be reduced.

[0014]

FIG. 1 is a block diagram showing the configuration of an embodiment of a frequency synthesizer according to the present invention. In the figure, a reference signal input from an input terminal 41 is input to one input terminal of a phase comparator 42, and the output thereof is
Is input to a frequency control terminal of a voltage controlled oscillator (VCO) 44 through The output of the voltage controlled oscillator 44 is taken out from the output terminal 45 as a microwave output and is input to the variable frequency divider 46. The signal frequency-divided by the variable frequency divider 46 is feedback-connected to the other input terminal of the phase comparator 42 via the pulse train generator 11, which is a feature of the present invention, to form a phase locked loop.

The pulse train generator 11 provided between the variable frequency divider 46 and the phase comparator 42 has M pulses (M is an integer of 1 or more) between output pulses of the variable frequency divider 46. , The frequency division ratio N is set to 1 / (M +
This is equivalent to increasing the frequency by 1). That is, if the oscillation frequency of the voltage controlled oscillator 44 is f _VCO and the reference signal frequency is f _REF , then f _VCO = (N / (M + 1)) · f _REF . This is achieved by changing the frequency division ratio N to obtain f
_This shows that the oscillation frequency f _VCO can be varied in units of _REF / (M + 1), and even if the frequency division ratio N of the variable frequency divider 46 is equivalently reduced to N / (M + 1), the frequency variable minimum step width can be increased. 3 illustrates a feature of the invention that does not grow.
Therefore, as compared with the conventional frequency synthesizer that realizes the same frequency variable minimum step width, the reference signal frequency f
_In the frequency synthesizer of the present invention capable of _{increasing REF} by M + 1 times, the detection sensitivity of the phase comparator 42 becomes M + 1 times, and good phase noise characteristics can be obtained.

FIG. 2 is a block diagram showing the configuration of a first embodiment of the pulse train generator according to claim 1 used in the frequency synthesizer of the present invention. In the figure, a pulse input from an input terminal 21 is input to a first NOR gate 22, and a NOR output (NOR) of the pulse is input to a first delay line 2.
3, and an OR output (OR) is output to the output terminal 24. The output of the first delay line 23 is input to a second NOR gate 25, and its NOR output (NOR) is output to the first NOR gate 25.
Is input to the NOR gate 22. The pulse is the second
, And its output is input to the reset terminal of the counter 27. The counter 27 counts up by the output of the first delay line 23 and outputs the counter output to the second NOR gate 25.

Here, the pulse train generating loop formed by the first NOR gate 22, the first delay line 23, and the second NOR gate 25 forms a pulse train that fills the interval between the pulses input from the input terminal 21 together with the pulses. Output from the output terminal 24. However, the first delay line 2
Since it is extremely difficult to set the delay time 3 to exactly an integral multiple of the pulse period, the shifts overlap by going around the pulse train generation loop, and the OR output output to the output terminal 24 eventually becomes “high”. It will be fixed. The second delay line 26 and the counter 27 are connected to the first delay line 2 to prevent the OR output from being fixed to “high”.
The counter output is set to "high" for a certain period of time from the time when the output of the second delay line 26 is counted to the time when the counter 27 is reset by the output of the second delay line 26 after the output of the counter 27 is counted. To mask the pulse train generation loop so that the pulse train is not transmitted.

The operation of each section will be described below based on specific numerical values with reference to a time chart shown in FIG. The frequency of the pulse input from the input terminal 21 is 20 MHz, and the duty ratio is 5%. The delay time of the first delay line 23 is 17.5 ns, the delay time of the second delay line 26 is 10 ns, and the counter 27 is a binary counter of an up-edge operation and has a reset function. Every time the up edge of the output of the line 23 is input, an up-count is performed. When it counts "2" and "1" is placed on the digit immediately above the least significant digit, it is taken out as a counter output. .

While the pulse is input and the counter output is “low”, a new pulse is generated by the pulse train generation loop at 17.5 ns and 17.5 × 2 = 35 ns from the input timing of the first pulse (a, a in the figure). b pulse).
When these two new pulses are generated, the counter output becomes “high”, and the pulse of 17.5 × 3 = 52.5 ns becomes the second pulse.
Output terminal 2 of the NOR gate 25
At 4, the next pulse input every 50 ns appears as the OR output of the first NOR gate 22 (pulse c in the figure). The counter 27 is reset by the output of the second delay line 26 that delays the next pulse by 10 ns, and the counter output becomes “low”. Therefore, the pulse train generation loop is in a state where the pulse is transmitted, and 17.5 ns and 17.5 × 2 = 35 ns from the input timing of the next pulse (50 + 17.5 = 6 from the input timing of the first pulse).
A new pulse is generated at 7.5 ns and 50 + 17.5 × 2 = 85 ns (d and e pulses in the figure). The same applies hereinafter.

In the numerical example shown here, the input terminal 2
Each time one pulse is input from 1, two new pulses can be generated between the next pulse and this new number of generated pulses is equal to the delay time of the first delay line 23. It depends. Therefore, for example, to increase the number of generated pulses, the delay time of the first delay line 23 may be reduced. It is necessary to appropriately set the delay time of the delay line 26.

FIG. 4 is a diagram showing the results of an experiment in which the first embodiment of the pulse train generator was constructed using an actual IC. Here, as the NOR gates 22 and 25, “MC” of MECL is used.
10102 "and" MC10H016 "as the binary counter 27. The pulse input from the input terminal 21 is
The delay time of the first delay line 23 was 36 ns, and the delay time of the second delay line 26 was 25 ns.

In the figure,, and are respectively shown in FIG.
, A pulse input from the input terminal 21, a counter output, and an OR output of the first NOR gate 22 extracted to the output terminal 24. As shown here, it can be seen that every time a pulse is input, two pulses are newly generated and output to the output terminal 24.

Note that the interval between the last pulse newly inserted between the pulses input from the input terminal 21 and the next input pulse is narrower than that between the other pulses, and as shown in FIG. 3 or FIG. A phase shift occurs for each pulse input.

Here, the first signal output to the output terminal 24 is
FIG. 5 shows the result of measuring the frequency spectrum of the OR output of the NOR gate 22 by the spectrum analyzer.
Since the component at 30 MHz of the third harmonic of (MHz) is the largest, it can be seen that the intended function is achieved even if the above-described pulse train generator is used in the frequency synthesizer of the present invention.

In this embodiment, two NOR gates 22 and 25 are used as a logic circuit for forming a pulse train generation loop.
However, even if another logic circuit is used, a pulse train generation loop that performs the same function can be formed. Here, FIG. 6 shows the configuration of the second embodiment of the pulse train generator obtained by converting the logical relationship of the first embodiment according to De Morgan's theorem, and FIG. 7 shows a time chart for explaining the operation thereof.

In FIG. 6, the first NOR gate 22 and the second NOR gate 25 shown in the first embodiment are replaced with an OR gate 31 and an AND gate 32, respectively, and the counter 27 shown in the first embodiment is reset by a down-edge operation. Counter 3 that makes the counter output "high" at the time
3, the OR output of the OR gate 31 is taken out to the output terminal 24 and input to the first delay line 23, whereby a pulse train generator equivalent to the first embodiment can be realized.

The operation is exactly the same as shown in FIG. 7 except that the logic of the output of the first delay line 23 and the counter output of the counter 33 are inverted with respect to the first embodiment. Every time one pulse is input from the terminal 21, two new pulses can be generated between the next pulse and the next pulse.

FIG. 8 is a block diagram showing an embodiment of a pulse train generator according to claim 2 used in the frequency synthesizer of the present invention. In the figure, a pulse input from an input terminal 21 is input to a first delay line 35 and also to a first NOR gate 36. The output of the first delay line 35 is input to the second NOR gate 37, and its NOR output (NOR) is output to the output terminal 24 and is input to the second delay line 38. The output of the second delay line 38 is input to the first NOR gate 36, and its NOR output (NOR) is output to the second NOR gate 37.
Is input to Here, a plurality of pulses are generated in response to a pulse input from the input terminal 21 by a pulse train generation loop formed by the first NOR gate 36, the second NOR gate 37, and the second delay line 38, and the output terminal 2
4 is output.

Hereinafter, the operation will be described with reference to a time chart shown in FIG. The pulse input from the input terminal 21 has a duty ratio having a width determined by the delay time of the first delay line 35 by the first delay line 35, the first NOR gate 36, and the second NOR gate 37. It is converted to a small pulse (Nor output) (the shaded pulse in the figure). The pulse goes through a pulse train generation loop at a time interval determined by the delay time of the second delay line 38, and is taken out from the second NOR gate 37 to the output terminal 24 as a NOR output. Here, when the next pulse is input from the input terminal 21, the output of the first NOR gate 36 becomes "low", and the pulse train is not transmitted through the pulse train generating loop. As a result, every time one pulse is input from the input terminal 21, a plurality of new pulses can be generated between the next pulse.

[0030]

As described above, according to the present invention, the frequency variable minimum step width can be reduced while the reference signal frequency input to the phase comparator is kept high, and the frequency synthesizer with low phase noise and high resolution can be obtained. Can be realized. Therefore, even when a small channel interval is required as in a local oscillation circuit mounted on a wireless communication device, good phase noise characteristics can be realized by using the frequency synthesizer of the present invention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a frequency synthesizer according to the present invention.

FIG. 2 shows a claim used in the frequency synthesizer of the present invention.
FIG. 2 is a block diagram showing a configuration of a first embodiment of the pulse train generator described in item 1 .

FIG. 3 is a time chart for explaining the operation of the first embodiment of the pulse train generator according to claim 1 ;

4 is a diagram showing experimental results constructed using the actual IC a first embodiment of a pulse train generator according to claim 1.

5 is a diagram showing the frequency spectrum of the output signal of the first embodiment of the pulse train generator according to claim 1.

FIG. 6 shows a claim used in the frequency synthesizer of the present invention.
FIG. 5 is a block diagram showing a configuration of a second embodiment of the pulse train generator described in item 1 .

7 is a time chart for explaining the operation of the second embodiment of the pulse train generator according to claim 1.

FIG. 8 shows a claim used in the frequency synthesizer of the present invention.
It is a block diagram which shows the Example structure of the pulse train generator of item 2 .

FIG. 9 is a time chart for explaining the operation of the embodiment of the pulse train generator according to claim 2 ;

FIG. 10 is a block diagram illustrating a configuration example of a conventional frequency synthesizer.

[Explanation of symbols]

 Reference Signs List 11 pulse train generator 21 input terminal 22 first NOR gate 23 first delay line 24 output terminal 25 second NOR gate 26 second delay line 27 counter 31 OR gate 32 AND gate 33 counter 35 first delay line 36 first NOR gate 37 Second NOR gate 38 Second delay line 41 Input terminal 42 Phase comparator 43 Loop filter 44 Voltage controlled oscillator (VCO) 45 Output terminal 46 Variable frequency divider

Continuation of the front page (56) References JP-A-62-43216 (JP, A) JP-A-56-72544 (JP, A) JP-A-1-261027 (JP, A) JP-A-50-116265 (JP) (A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03L 7/18 H03K 3/64 H03L 7/08 Practical file (PATOLIS) Patent file (PATOLIS)

Claims (3)

(57) [Claims] 1. An input pulse is taken into one terminal, and
Between the input pulse of the input and the pulse input to the other terminal
Take the sum, output the logical sum pulse, and
A delay is applied to input the other terminal, and the input pulse
A pulse train generation loop that fills a new pulse between pulses, and the number of pulses passing through the pulse train generation loop are counted.
When the next input pulse is given after
Go around the pulse train generation loop until the fixed time elapses
That a pulse train interruption means for masking the pulse train
A pulse train generator. 2. An input pulse is taken into one terminal, and
Negation between the input pulse of and the pulse input to the other terminal
First NOR circuit for performing an OR operation, and first delay unit for applying a predetermined delay to the input pulse
And a NOR gate output from the first NOR circuit.
Between the pulse and the pulse output from the first delay means.
The NOR that takes the NOR and outputs the NOR pulse
2 NOR operation means and a NOR operation circuit output from the second NOR operation means.
A predetermined delay to the first NOR
Having second delay means for inputting to the other terminal
A pulse train generator. 3. A control signal input to a frequency control terminal.
Therefore, the oscillation frequency is controlled, and the signal of the set frequency is
A voltage-controlled oscillator that outputs a signal, and an output signal of the voltage-controlled oscillator.
Converts to a pulse of the corresponding frequency according to the specified dividing ratio
A variable frequency divider which, against the phase difference between the output pulse and the reference signal of the variable frequency divider
A phase comparator for outputting a response signal, frequency of the voltage controlled oscillator output signal of the phase comparator
Zhou and a loop filter for feeding back connected to several control terminals
2. The wave number synthesizer according to claim 1 , wherein said variable frequency divider and said phase comparator are provided between said variable frequency divider and said phase comparator.
Or a pulse train generator according to claim 2, wherein
Each time one frequency divider output pulse is input, multiple
A frequency characterized by generating pulses
Synthesizer.