JPH05275930A - Multiplier - Google Patents

Abstract

PURPOSE:To reduce the area and to facilitate a highly integrated monolithic structure of a multiplier by constructing a BPF with use of the concentrated constant type capacity elements whose values are decided from a prescribed transmission characteristic and an inductance element. CONSTITUTION:A BPF 1 consists of an inductance element L1 and the concentrated constant type capacity elements C2 and C3 whose values are decided from the transmission characteristic including the parasitic capacity of a field effect transistor FET Q2 and the input capacity of a matching circuit 2. That is, the element C2 which is connected in series between the drain of an FET Q1 and an earth potential point and has the serial resonance at frequency f0 is used together with the element L1, together with the element C3 whose value is decided from the transmission characteristic including the parasitic capacity of the FET Q2 and the input capacity of the circuit 2 and which has the resonance parallel to the element L1 at frequency 2f0. In such a constitution of the BPF 1 using only the concentrated constant L1, C2 and C3, a circuit can be miniaturized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier, and more particularly to a microwave multiplier having a structure in which a field effect transistor is used as a non-linear element.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional multiplier (for example, a doubler) includes a field effect transistor Q1 that non-linearly amplifies an input signal Vin having a frequency fo and an active load of the field effect transistor Q1. At the same time, the field-effect transistor Q2 that serves as a DC bias circuit for the field-effect transistor Q1 and the band-pass filter 1 that cuts the signal of the frequency fo and passes the signal of the doubled frequency 2fo.
x, an output matching circuit 2 for taking out a passed signal having a frequency of 2fo to the outside, and a resistor R1 of a gate bias circuit. The capacitive element C1
Is for DC cutting of the input signal Vin.

In this multiplier, the input signal Vin having the frequency fo is amplified by the field effect transistor Q1. Since this field effect transistor operates in the non-linear region by the resistance I1 of the gate bias circuit, the input signal Vin of the input signal Vin Generates a second harmonic with twice the frequency 2fo. A signal including a harmonic component is extracted by the band-pass filter 1x only in the frequency component of 2fo, and the output matching circuit 2
And output (Vout).

The bandpass filter 1x is usually a distributed constant type circuit using a microstrip line as a half-wavelength resonance element.

[0005]

In the above-mentioned conventional multiplier, the area of the resonance element and the like is increased because the bandpass filter 1x is a distributed constant type circuit using a microstrip line as a half-wavelength resonance element. High integration,
It has a drawback that it is difficult to make it monolithic (MMIC).

An object of the present invention is to provide a multiplier which can easily realize high integration and monolithic by reducing the area of the bandpass filter.

[0007]

According to the multiplier of the present invention, the source is connected to a ground potential point, and a predetermined bias potential is supplied to the drain and the gate, respectively, and the first frequency of the input signal transmitted to the gate. A first field-effect transistor that outputs a signal including a second frequency that is multiplied by, a second field-effect transistor that supplies the bias potential to the drain of the first field-effect transistor, and the supplied signal A matching circuit that matches and outputs to an external circuit,
An output signal of the first field effect transistor, which is formed by a lumped constant type capacitive element and an inductance element whose values are determined from the transfer characteristics including the parasitic capacitance of the second field effect transistor and the input capacitance of the matching circuit. A band pass filter for removing at least the first frequency component and extracting the second frequency component and supplying the second frequency component to the matching circuit.

Also, the matching circuit is formed by a source follower circuit having a predetermined input capacitance.

Further, a bandpass filter is connected in series between the drain of the first field effect transistor and a ground potential point, and a first capacitance element and a first inductance element which are in series resonance at a first frequency, And a second capacitance element whose value is determined so as to resonate in parallel with the first inductance element at a second frequency including the parasitic capacitance of the second field effect transistor and the input capacitance of the matching circuit. To be done.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The difference between this embodiment and the conventional multiplier shown in FIG. 4 is that the bandpass filter 1 has a value based on the transfer characteristics including the parasitic capacitance of the field effect transistor Q2 and the input capacitance of the matching circuit 2. Is formed by the lumped-constant type capacitance elements C2 and C3 and the inductance element L1 which are determined, and more specifically, the capacitance connected in series between the drain of the field effect transistor Q1 and the ground potential point and having the frequency fo series resonance. A capacitance element whose value is determined so as to resonate in parallel with the inductance element L1 at a frequency of 2fo, including the element C2 and the inductance element L1, the parasitic capacitance (C _Q2 ) of the field effect transistor Q2, and the input capacitance (Cin1) of the matching circuit. And C3.

Since the input signal Vin of the frequency fo is amplified by the field effect transistor Q1 and is biased in a distorted state at the same time, a second (or higher) harmonic wave (here, the second order is particularly taken as an example). Generate 2fo.

FIG. 2 is an equivalent circuit diagram of a portion related to the bandpass filter 1 of FIG. The capacitance C _Q2 is an equivalent capacitance of the field effect transistor Q2. Of the frequency components of the frequencies fo and 2fo generated by the field effect transistor Q1, the value of the component of the frequency fo is selected so as to be short-circuited to the ground potential point due to the series resonance of the inductance element L1 and the capacitance element C2. The signal of frequency fo does not propagate to the subsequent stages. On the other hand, the value of the capacitance element C3 is the capacitance C _Q2
It is determined that the combined capacitance with the input capacitance Cin1 of the matching circuit 2 and the inductance element L1 resonate in parallel at the frequency 2fo. Therefore, the signal of frequency 2fo is propagated to the matching circuit 2 without being attenuated. In the matching circuit 2, the constants are set so as to match the signal of the frequency 2fo and to match with the external circuit, and as a result, only the signal of the frequency 2fo is output as the output signal Vout.

As described above, in this embodiment, since the bandpass filter 1 can be realized only by the lumped constants (L1, C2, C3), the circuit can be downsized, and the multiplier can be highly integrated and monolithic. it can. Further, since the field effect transistor Q2 is used as the active load in this embodiment, the power feeding circuit to the field effect transistor Q1 is realized by only one field effect transistor Q2, and there is an advantage that the bias circuit can be downsized. The circuit is suitable for high integration and monolithic.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram of the second embodiment of the present invention.

In this embodiment, the matching circuit 2a is connected to the source,
One of the drains is connected to the power supply terminal, the gate is connected to the drain of the field effect transistor Q1, the field effect transistor Q3 having the input capacitance Cin2, and the gate and the source are connected to the ground potential point and the drain is the field effect transistor Q3.
3 is formed of a source follower circuit including a field effect transistor Q4 connecting the other of the source and the drain, and the band pass filter 1a is formed by a lumped constant inductance element L1,
It is formed by a series circuit of the capacitive element C2 and has an input capacitance Cin.
The value of 2 determines the gate width size of the field effect transistor Q3 by causing the combined capacitance with the capacitance C _Q2 to resonate in parallel with the inductance element L1 at the frequency 2fo.
That is, this embodiment has a configuration in which the capacitive element C3 in the first embodiment is included in the input capacitance Cin2, and a circuit including a bandpass filter and a matching circuit is further provided as compared with the first embodiment. There is an advantage that it can be miniaturized. The capacitive element C4 is for DC cutting of the output.

[0018]

As described above, according to the present invention, the bandpass filter is a lumped constant type capacitor whose value is determined from the transfer characteristic including the parasitic capacitance of the second field effect transistor and the input capacitance of the matching circuit. By adopting a configuration in which the element and the inductance element are formed, there is an effect that the area of the band pass filter can be reduced, and high integration and monolithicization can be facilitated.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a bandpass filter portion of the embodiment shown in FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional multiplier.

[Explanation of symbols]

 1, 1a, 1x band pass filter 2, 2a matching circuit C1 to C4 capacitive element Cin1, Cin2 input capacitance L1 inductance element Q1 to Q4 field effect transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Yoshi ▼ Sadayoshi Tada 5-7 Shiba, Minato-ku, Tokyo NEC Corporation

Claims (3)

[Claims] 1. A signal including a second frequency obtained by multiplying a first frequency of an input signal transmitted to the gate by connecting a source to a ground potential point and supplying predetermined bias potentials to the drain and the gate, respectively. A first field effect transistor for outputting, a second field effect transistor for supplying the bias potential to the drain of the first field effect transistor, and a matching circuit for matching and outputting the supplied signal to an external circuit An output of the first field-effect transistor formed of a lumped-constant type capacitive element and an inductance element whose values are determined from the transfer characteristics including the parasitic capacitance of the second field-effect transistor and the input capacitance of the matching circuit. At least the first frequency component of the signal is removed and the second frequency component is extracted to supply the band pass filter to the matching circuit. A multiplier having a filter. 2. The multiplier according to claim 1, wherein the matching circuit is formed of a source follower circuit having a predetermined input capacitance. 3. A band-pass filter is connected in series between the drain of the first field effect transistor and a ground potential point, and a first capacitive element that resonates in series at a first frequency and a first capacitive element.
Of the inductance element, the second capacitance element including the parasitic capacitance of the second field effect transistor and the input capacitance of the matching circuit, the value of which is determined so as to resonate in parallel with the first inductance element at the second frequency. A multiplier as claimed in claim 1 formed with: