JP3030977B2 - Multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier, and more particularly to a multiplier for microwaves.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional multiplier receives an input signal Vin having a first frequency f1 and converts a signal including a second frequency f2 component obtained by multiplying the first frequency f1. Output source-grounded field effect transistor Q1
And a distributed constant bandpass filter 1A that passes only the second frequency f2 component included in the output signal of the field effect transistor Q1.

An input signal Vin having a first frequency f1
Is nonlinearly amplified by the field effect transistor Q1, and as a result, a signal including a frequency that is a multiple of the first frequency f1 is output as a distortion component. From this output signal, only the second frequency f2 component, which is a desired multiple wave, is output by the subsequent bandpass filter 1A.

In the field of microwaves, since the bandpass filter 1A is constituted by a distributed constant circuit, a mounting size larger than a wavelength of a desired signal is required.

In FIG. 4, a resistance element R1 and an inductance element L1 are bias circuits for supplying a bias potential to the gate and the drain of the field effect transistor Q1.

[0006]

In this conventional multiplier, since the bandpass filter 1A is of a distributed constant circuit type, its mounting size is about the wavelength of a signal to be handled or more, requiring a large area. There is a problem that integration and monolithicization are difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplier capable of reducing the mounting size of a bandpass filter and facilitating integration and monolithicization.

[0008]

A multiplier according to the present invention has a source connected to a ground potential point, a predetermined bias potential supplied to a drain and a gate, and a first frequency of an input signal transmitted to the gate. And a field-effect transistor that outputs a signal containing a second frequency component by multiplying the frequency-divided signal, and removes at least the first frequency component from the output signal of the field-effect transistor that is formed by a lumped-constant-type capacitance element and an inductance element. A band-pass filter for extracting and outputting the second frequency component, and an input capacitance having a predetermined value.
And a buffer circuit, wherein the input capacitance is one capacitance element.
Form a bandpass filter as a child and the output of this bandpass filter
A signal is supplied to the input terminal of the buffer circuit.
It is characterized by the following .

[0009]

[0010] The bias potential to the drain of the field effect transistor is supplied by the bias circuit including a capacitor for DC blocking of lumped inductance element for DC supply, bandpass filter, the DC blocking And a direct-current supply inductance element.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a reference example of the present invention.

This reference example differs from the conventional multiplier shown in FIG. 4 in that the bandpass filter 1 is connected in series between the drain of the field effect transistor Q1 and the ground potential point, and the input signal Vin is A lumped-constant-type inductance element L2 and a capacitance element C2 that resonate in series at the first frequency f1
And a capacitor C1 connected between the drain of the field-effect transistor Q1 and the ground potential point and resonating in parallel with the inductance element L2 and the capacitor C2.

The output signal of the field effect transistor Q1 contains a first frequency f1 component and a second frequency f2 component obtained by multiplying the first frequency f1 component.

In the bandpass filter 1, the first frequency f
For one component, the impedance between the ground potential point and the inductance element L2 and the capacitance element C2 becomes zero, so that the first frequency f1 component does not appear at the output terminal. On the other hand, for the second frequency f2 component, since the inductance element L2 and the capacitance element C2 and the capacitance element C1 resonate in parallel to make the impedance between the ground potential point infinite, the second frequency f2 component Directly appears at the output terminal. Thus, the desired second frequency f
A signal (Vout) of only two components is obtained.

[0016] In this reference example, a band-pass filter 1 in da
Click drawers element L2, since is formed by three lumped element capacitive element C1, C2, it is possible to reduce the mounting area compared with the conventional distributed constant circuit type.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, a buffer circuit 2 for amplifying and outputting a desired frequency is provided, and the bandpass filter 1a has a configuration including the input capacitance Cs of the buffer circuit 2 as one capacitance element. ing. Therefore, there is no need to provide an independent capacitance element C1 as in the reference example, and the mounting area of the element independently provided as a bandpass filter can be further reduced.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, in addition to the first embodiment, the bias potential to the drain of the field effect transistor Q1 is
Resistance element R2 and inductance element L3 for DC supply
And a bias circuit 3 formed of a DC blocking capacitive element C3 having one end connected to a ground potential point, and the inductance element L3 and the capacitive element C3 are supplied to the first frequency f1.
In series, and these inductance elements L
3, there is no single element provided independently as a bandpass filter with the capacitance element C3 and the input capacitance Cs of the buffer circuit 2, and all the elements are shared with other circuits.

Therefore, the entire mounting area can be further reduced as compared with the first embodiment.

[0022]

As described above, according to the present invention, the band-pass filter is formed by the lumped-constant type inductance element and the capacitance element, so that the mounting area of the band-pass filter is smaller than that of the conventional distributed constant type. Therefore, there is an effect that integration and monolithicization become easy. In addition, by using the inductance element and the capacitance element together with other circuits, the entire mounting area can be further reduced, and the integration and monolithicization can be further facilitated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a reference example of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional multiplier.

[Explanation of symbols]

 1, 1a, 1b, 1A Bandpass filter 2 Buffer circuit 3 Bias circuit C1 to C3 Capacitance element Cs Input capacitance of buffer circuit L1 to L3 Inductance element Q1 to Q3 Field effect transistor R1, R2 Resistance element

Continuation of the front page (72) Inventor Tatsuya Miya 5-7-1, Shiba, Minato-ku, Tokyo Within NEC Corporation (56) References JP-A-2-192205 (JP, A) JP-A-62-60304 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03B 19/14

Claims (2)

(57) [Claims] A source is connected to a ground potential point, a predetermined bias potential is supplied to a drain and a gate, and a first frequency of an input signal transmitted to the gate is multiplied to include a second frequency component. A field effect transistor that outputs a signal; and a lumped-constant type capacitive element and an inductance element, wherein at least the first frequency component is removed from the output signal of the field effect transistor and the second signal is removed.
A bandpass filter for extracting and outputting a frequency component of a predetermined
A buffer circuit having an input capacitance of the value
A bandpass filter is formed using the capacitance as one capacitance element.
Output signal of the bandpass filter to the input terminal of the buffer circuit
A multiplier characterized in that it is supplied . Bias potential to the drain of 2. A field effect transistor is supplied by the bias circuit including a capacitor for DC blocking of lumped inductance element for DC supply, bandpass filter, the DC blocking multiplier of claim 1 configured to include a inductance element for the DC supply and the capacitive element of use.