JPH1093349A - Frequency multiplier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase an output power of a multiplied output signal by activating a transistor(TR) at a point at which nonlinearity in an input and output characteristic of the TR is more increased so as to improve the conversion gain. SOLUTION: The frequency multiplier 31 is configured in such a way that an input signal is given to a TR 32 via an input matching circuit 33 and a multiplied output signal outputted from the TR 32 is outputted through a reflection type fundamental wave signal band suppression circuit 41 and an output matching circuit 42. In this case, a transmission line 40 which generates a standing wave is provided between an output terminal of the TR 32 and an input terminal to the reflection type fundamental wave signal band suppression circuit 41. Through the constitution above, since a voltage applied to an output terminal of the TR 32 is increased, the TR 32 is operated at a point where the nonlinearity of the input output characteristic of the TR 32 is much increased so as to increase output power of the multiplied output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplier configured to receive a signal in a frequency band such as a microwave or a millimeter wave and output a multiplied output signal.

[0002]

2. Description of the Related Art A frequency multiplier is configured to output a frequency signal that is an integral multiple of the frequency of an input signal (ie, a multiplied output signal) by utilizing the nonlinearity of input / output characteristics of a transistor or the like. . In the case of this configuration, it is required that the power of the multiplied output signal be made larger and the power of the unnecessary signal be made smaller. Here, the unnecessary output is
Low-order and high-order frequency signals that are signals other than the multiplied output signal among the output signals output from the transistors and the like. Among these unnecessary outputs, an output signal having the same frequency as the frequency of the input signal is called a fundamental signal. Since the output power of the fundamental wave signal is often higher than the output power of the multiplied output signal, a circuit for suppressing the output of the fundamental wave signal is provided in the frequency multiplier.

[0003] Such a frequency multiplier is basically composed of
It comprises an input matching circuit, a transistor, a fundamental wave signal band suppression circuit, and an output matching circuit. The input matching circuit is a circuit that matches the frequency of the input signal,
The output matching circuit is a circuit that matches the frequency of the multiplied output signal. Further, as the fundamental wave signal band suppressing circuit, a reflection type circuit that reflects a fundamental wave signal (unnecessary signal) is generally used.

[0004] On the other hand, there has been conventionally known a frequency multiplier having the above-mentioned configuration formed of a monolithic microwave integrated circuit (MMIC). As an example of this configuration,
"" A60GHz MMIC STABILIZED
FREQUENCY SOURCE COMPOSED
OF A 30 GHz DRO AND A DOU
BLER, 1995 IEEE Microwave
Symp. Digest pp. 71-74 ". FIG. 7 shows a specific configuration of this frequency multiplier.

As shown in FIG. 7, a frequency multiplier 1
Is configured to include an input matching circuit 2, a transistor 3, a reflection type fundamental wave signal band suppression circuit 4, and an output matching circuit 5. The input matching circuit 2 includes a transmission line 6 and a stub 7
The connection point between the transmission line 6 and the stub 7 is connected to one end of a capacitor 8.
Is an input terminal 9. Transistor 3
Is composed of, for example, an FET, and its gate is connected to the other end of the transmission line 6 of the input matching circuit 2 and grounded via the transmission line 10 and the capacitor 11.

Further, the reflection type fundamental wave signal band suppressing circuit 4 is composed of an open stub 12, and the output matching circuit 5 is composed of a transmission line 13 and a stub 14. The drain of the transistor 3 is connected to one end of the stub 12, connected to one end of the transmission line 13, and further grounded via the transmission line 15 and the capacitor 16. The source of the transistor 3 is grounded. Also,
A connection point between the transmission line 13 and the stub 14 is connected to one end of a capacitor 17, and the other end of the capacitor 17 is an output terminal 18. The transmission line 10 and the capacitor 11
Is a voltage terminal 19 for supplying a gate bias, and a connection point between the transmission line 15 and the capacitor 16 is
It is a voltage terminal 20 for supplying a drain bias.

[0007]

In the frequency multiplier having the above-described structure, a multiplied output signal is generated by utilizing the nonlinearity of the input / output characteristics of the transistor. There is a characteristic that the gain becomes very small, in other words, the output power of the multiplied output signal becomes small. Therefore, it is strongly desired to increase the conversion gain of the frequency multiplier.

Therefore, the inventor tried various experiments to increase the conversion gain of the frequency multiplier. First, it is known that operating the transistor at the point where the nonlinearity of the input / output characteristics of the transistor becomes larger increases the output power of the multiplied output signal.
The inventor paid attention to this characteristic. The present inventor has noticed that in order to operate the transistor, the high-frequency voltage applied to the output terminal of the transistor should be increased in that the nonlinearity of the input / output characteristics of the transistor becomes larger.

Here, as a method of increasing the voltage applied to the output terminal of the transistor, a method of connecting a voltage terminal for applying a voltage from the outside to the output terminal of the transistor can be easily considered. However, when such a voltage is applied, only the DC voltage level increases, and the effect of increasing the high-frequency voltage as intended by the inventor cannot be expected.

For this reason, the present inventor has considered whether there is a method of increasing the voltage applied to the output terminal of the transistor without applying a voltage from outside. Here, the present inventor:
The fundamental wave signal output from the output terminal of the transistor is reflected by the reflection type fundamental wave signal band suppression circuit, and furthermore, the reflection signal is repeatedly reflected at the output terminal of the transistor. Attention has been paid to the fact that the reflection is attenuated at the portion (transmission line) connecting to the input terminal of the fundamental wave signal band suppression circuit. The inventor of the present invention has thought that the voltage applied to the output terminal of the transistor can be increased by using the fundamental wave signal that is attenuated by reflection, and as a result of pushing this idea forward, based on the fundamental wave signal and the reflected signal, A transmission line having a function of generating a standing wave is provided between the output terminal of the transistor and the input terminal of the reflection type fundamental wave signal band suppression circuit.

In order to confirm the operation of the present invention, the inventor has provided a transmission line for generating a standing wave between the output terminal of the transistor and the input terminal of the reflection type fundamental wave signal band suppression circuit. An experiment for producing a frequency multiplier MMIC was performed. Then, when the output power and the conversion gain of the multiplied output signal output from the manufactured frequency multiplier were measured, it was actually confirmed that the output power and the conversion gain were considerably large. The specific configuration and measurement results of the MMIC of the manufactured frequency multiplier will be described in detail in the section of the embodiment of the invention.

An object of the present invention is to improve the conversion gain and increase the output power of the multiplied output signal by configuring the transistor to operate at a point where the nonlinearity of the input / output characteristics of the transistor becomes larger. It is an object of the present invention to provide a frequency multiplier.

[0013]

According to the first aspect of the present invention, a transmission line of a predetermined length for generating a standing wave is provided between an output terminal of a transistor and an input terminal of a reflection type fundamental wave signal band suppression circuit. Is provided, the voltage applied to the output terminal of the transistor can be increased, and the transistor operates at a point where the nonlinearity of the input / output characteristics of the transistor becomes larger. As a result, the conversion gain is improved and the output power of the multiplied output signal is increased. In the case of this configuration, a transmission line having a function of generating a standing wave can be relatively easily designed simply by adjusting its length, and thus can be easily realized.

According to the second aspect of the invention, the length of the transmission line is determined by the phase of the fundamental wave signal output from the transistor,
The fundamental wave signal reflected by the reflection type fundamental wave signal band suppression circuit was further set so that the phase of the signal reflected by the output terminal of the transistor was the same as that of the signal. Thereby, the amplitude of the standing wave becomes maximum, and the voltage applied to the output terminal of the transistor also becomes maximum. Therefore, since the transistor operates at the point where the nonlinearity of the input / output characteristics of the transistor is maximized, the conversion gain can be maximized.

According to the third aspect of the present invention, the length of the transmission line is changed by the fundamental signal output from the transistor and the fundamental signal reflected by the reflection-type fundamental signal band suppression circuit, further by the output terminal of the transistor. Are set so that the signals reflected by the above have a phase relationship that reinforces each other. As a result, the fundamental wave signal and its reflected signal are superimposed so as to reinforce each other, so that the voltage applied to the output terminal of the transistor becomes larger than when the transmission line does not exist. Therefore, the transistor operates at a point where the nonlinearity of the input / output characteristics of the transistor becomes larger, so that the conversion gain and the output power can be increased.

In this configuration, when the length of the transmission line is set such that the phase difference φd falls within the range determined by the equation (1), the fundamental wave The signal and its reflected signal can be actually constructed in such a way that they reinforce each other. As a result, the conversion gain can be improved, and the output power of the multiplied output signal can be increased. Further, when the phase difference φd is defined as described in the invention of claim 5, the length of the transmission line can be easily set by calculation.

According to the sixth aspect of the present invention, when an even-order harmonic signal is output as the multiplied output signal, the transmission line corresponding to the fundamental signal frequency to suppress the reflection type fundamental signal band suppression circuit is suppressed. An open stub having a quarter length of the internal wavelength λ or a short stub having a half length was used. This makes it possible to easily realize the reflection-type fundamental signal band suppression circuit with a relatively simple configuration.

According to the seventh aspect of the present invention, when an odd-order harmonic signal is output as a multiplied output signal, the reflection type fundamental wave signal band suppressing circuit converts the signal corresponding to the fundamental wave signal frequency to be suppressed. It consisted of a bandpass filter having the function of attenuating. This makes it possible to easily realize the reflection-type fundamental signal band suppression circuit with a relatively simple configuration.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. This first
Is used as a part of a signal source for a millimeter wave radar system of the FMCW system, for example, and the frequency of an input signal (for example, 30 GHz) is used.
z) is doubled (converted to 60 GHz) and output. First, FIG. 1 is a diagram showing an electric circuit configuration of the frequency multiplier 31 of the first embodiment.

As shown in FIG. 1, the frequency multiplier 31
The transistor 32 as an active element of InP
High electron mobility transistor (hereinafter referred to as HEMT) using an InAlAs / strained InGaAs heterostructure fabricated on a substrate.
). The gate length of this HEMT 32 is 0.5 μm, the unit gate width is 25 μm, and the number of fingers is two.

An input matching circuit 33 is connected to the gate of the HEMT 32. This input matching circuit 33
The transmission line 34 and the stub 35 are connected.
In this case, the transmission line 34 and the stub 35 of the input matching circuit 33 are configured to match a 30 GHz band input signal. Then, one end of the transmission line 34 (the terminal not connected to the stub 35) is connected to the HEMT 3
2 gate. The connection point between the transmission line 34 and the stub 35 is connected to one end of a capacitor 36, the other end of the capacitor 36 is used as an input terminal 37, and an input signal is input to the input terminal 37. Further, the other end of the stub 35 (the terminal on the side not connected to the transmission line 34) is grounded via a capacitor 38 and serves as a voltage terminal 39 for supplying a gate bias.

The drain of the HEMT 32 constitutes the output terminal of the transistor. One end of a transmission line 40 for generating a standing wave is connected to this drain. The specific configuration and operation of the transmission line 40 will be described later. The other end of the transmission line 40 is connected to input terminals of a reflection type fundamental wave signal band suppression circuit 41 and an output matching circuit 42.

The reflection type fundamental wave signal band suppression circuit 41
Is the frequency of the fundamental signal (30 GHz in this embodiment)
An open stub 43 having a quarter length of the in-line wavelength λ corresponding to z). One end of the open stub 43 is an input terminal of the reflection type fundamental wave signal band suppression circuit 41 and is connected to the other end of the transmission line 40. The output matching circuit 42 is configured by connecting a transmission line 44 and a stub 45. In this case, the output matching circuit 42
The transmission line 44 and the stub 45 are configured to match the output signal in the 60 GHz band. Then, one end of the transmission line 44 (the terminal on the side not connected to the stub 45) is connected to the other end of the transmission line 40. A connection point between the transmission line 44 and the stub 45 is connected to one end of a capacitor 46, and the other end of the capacitor 46 is used as an output terminal 47. From this output terminal 47, a multiplied output signal (in the case of this embodiment, a 60 GHz frequency signal)
Is configured to be output.

The other end of the stub 45 (the terminal not connected to the transmission line 44) is grounded via a capacitor 48. The connection point between the capacitor 48 and the stub 45 is a voltage terminal 49 for supplying a drain bias. Further, the source of the HEMT 32 is grounded.

Each of the circuit elements (ie, the HEMT 32, the transmission line 34,
40, 44, stubs 35, 43, 45, condenser 3
6, 38, 46, 48, terminals 37, 39, 47, 49)
Are integrated on an InP substrate, for example, so that the frequency multiplier 31 is manufactured as an MMIC. The manufactured frequency multiplier 31 is an MMIC (chip) that receives an input signal in a 30 GHz band and outputs an output signal in a 60 GHz band (doubled).

In producing the above MMIC,
As the transmission line and the stub, a coplanar line 50 having the configuration shown in FIG. 2 was used. This coplanar line 50 is
A signal line 52 provided on a P substrate 51;
2 and ground electrodes 53, 53 disposed on both sides. Here, the signal line 52 and the ground electrode 53 are formed of, for example, gold. Then, the width dimension W of the signal line 52
s was set to 50 μm, and the distance Wg between the signal line 52 and the ground electrode 53 was set to 43 μm. In the case of this configuration, the wavelength (in-line wavelength) of the 30 GHz high-frequency signal in the coplanar line 50 was calculated to be approximately 3900 μm.

Here, the frequency multiplier (M
The actual circuit pattern of the MIC 31 is shown in FIG. In FIG. 4, the components indicated by the reference numerals and the lead lines are as follows.
In FIG. 1, the configuration is the same as the configuration indicated by each reference numeral and the lead line. The MMIC (frequency multiplier) 31 has a chip size of 2.7 × 1.7 mm.

Next, the operation of the transmission line 40 for generating a standing wave will be described with reference to FIG. As shown in FIG. 3, in the transmission line 40, the fundamental wave signal S1 output from the drain of the HEMT 32 and the fundamental wave signal reflected by the reflection type fundamental wave signal band suppression circuit 41 are further reflected by the drain of the HEMT 32. By the signal S2 obtained,
A standing wave is generated. And the amplitude of this standing wave is HE
The output signal (multiplied output signal and unnecessary signal (ie, signal including the fundamental signal S1)) output from the drain of the MT 32 is superimposed on the output signal.

As a result, the voltage applied to the drain of the HEMT 32 increases by the amplitude of the standing wave, and
HE in that the nonlinearity of the input / output characteristics of
The MT 32 operates. As a result, the conversion gain of the frequency multiplier 31 increases, and the output power of the multiplied output signal increases.

Here, the above-mentioned two signals S1 and S2
Let us consider the conditions that lead to a constructive topological relationship. First, when the phase difference φd between the two signals S1 and S2 belongs to the range defined by the following equation (1), the two signals S1 and S2 have a phase relationship that reinforces each other, and the amplitude of the standing wave is reduced. growing.

N × 360−120 ≦ φd ≦ nx360 + 120 (1) (where n is an integer) Therefore, the transmission line 40 is set so that the above equation (1) holds.
May be set (designed). Here, the phase difference φd is defined by the following equation (2).

Φd = (2 × φL) + φA + φB (2) In the equation (2), φL is a fundamental wave signal S corresponding to the length Ld, where L is the length of the transmission line 40.
1 phase delay. And this phase delay φL (degree)
Is defined by the following equation (3).

ΦL = (Ld / λ) × 360 (3) In the equation (3), λ is the wavelength of the fundamental signal S1 in the transmission line 40 (intra-line wavelength).
It is about 3900 μm.

In the above equation (2), φA represents a reflection coefficient Γ when the drain of the HEMT 32 is viewed from the transmission line 40.
A (see FIG. 3) is a phase characteristic. And φB
Is a reflection type fundamental wave signal band suppression circuit 4 from the transmission line 40.
1, that is, the phase characteristic of the reflection coefficient ΓB (see FIG. 3) when the input terminal of the open stub 43 is viewed.

Therefore, the inventor measured the two reflection coefficients ΔA and ΔB for the fundamental signal S1 of 30 GHz. The measurement results are shown below.

[0036]

(Equation 2) In this case, “0.7252” of the reflection coefficient ΓA is an amplitude characteristic, and “−29.7621 °” is a phase characteristic. Similarly, “1.0” of the reflection coefficient ΓB is an amplitude characteristic, and “180 °” is a phase characteristic.

From the measured values of the phase characteristics of the reflection coefficients ΓA and ΓB and the above three equations (1), (2) and (3), the length Ld of the transmission line 40 when n = 1 is calculated as When obtained, this length Ld is in a range determined by the following equation (4).

486.21 (μm) ≦ Ld ≦ 1786.21 (μm) (4) Accordingly, the length Ld of the transmission line 40 is set to fall within the range of the above equation (4), and the frequency multiplier is set. (MMIC)
It can be seen that the fabrication of No. 31 shows that the two signals S1 and S2 have a phase relationship that reinforces each other in the transmission line 40, and a standing wave having a sufficiently large amplitude is generated.

The present inventor has determined that the length Ld of the transmission line 40 falls within the range of the above equation (4),
Is set to 500 μm, and Ld is set to 6
A frequency multiplier 31 set to 00 μm was fabricated, and a frequency multiplier 31 having Ld set to 250 μm was fabricated assuming that Ld did not fall within the range of the above equation (4). Then, the three frequency multipliers 3 produced above are used.
A conversion gain of 1 was measured. The measurement results are shown in Table 1 below.
Shown in

[0040]

[Table 1] From this table, it can be seen that the conversion gain was significantly improved when Ld was set to 500 μm and 600 μm, as compared with the case where Ld was set to 250 μm. That is, as compared with the case where the phase difference φd between the two signals S1 and S2 is close to 180 degrees (when the signal S1 and the signal S2 are close to opposite phases), the phase difference φd is 36 degrees apart from 180 degrees to some extent.
It can be seen that the conversion gain is significantly improved when approaching 0 degrees (when the signals S1 and S2 approach the same phase). Thus, it was confirmed that the conversion gain was improved when the phase difference φd was within the range defined by the equation (1).

When the phase difference φd is 360 degrees, that is, when the signal S1 and the signal S2 have the same phase, the amplitude of the standing wave generated in the transmission line 40 becomes maximum. It is thought to be the largest. And the phase difference φd
Is set to 360 degrees, the length Ld of the transmission line 40 is set to about 1
It is calculated by calculation that it should be set to 100 μm. Therefore, the length Ld of the transmission line 40 is set to about 1100 μm
And the frequency multiplier 31 is manufactured, a configuration having the maximum conversion gain can be realized.

In this case, the MMIC-based frequency multiplier 3
Since the size of one chip is preferably as small as possible, the length Ld of the transmission line 40 is set to about 1 as described above.
If it is set to 100 μm, there is a problem that the chip size becomes considerably large. For this reason,
Actually, the frequency multiplier 31 (prototype) in which the length Ld of the transmission line 40 is set to about 500 μm or 600 μm is the most preferable configuration due to the restriction of the chip size.

In the above embodiment, the frequency multiplier 31
Is configured as a frequency doubler, but is not limited thereto, and may be configured as a frequency quadrupler. Specifically, an input signal of a 15 GHz band is input and a 60 G
When manufacturing a quadruple that outputs a multiplied output signal in the Hz band, the input matching circuit 33 is configured to perform matching in the 15 GHz band, the output matching circuit 42 is configured to perform matching in the 60 GHz band, and the reflection is performed. The type fundamental wave signal band suppression circuit 41 may be constituted by an open stub having a quarter length of the in-line wavelength λ1 of 15 GHz.

FIGS. 5 and 6 show a second embodiment of the present invention, and the points different from the first embodiment will be described. The same parts as those in the first embodiment are denoted by the same reference numerals. The frequency multiplier 31 of the second embodiment has a 20
This is a tripler that receives an input signal in the GHz band and outputs a multiplied output signal in the 60 GHz band, and outputs a so-called odd-order harmonic signal.

In this frequency multiplier 31, the input matching circuit 33 is configured to perform matching in the 20 GHz band.
The output matching circuit 42 is configured to perform matching in the 60 GHz band. Then, the reflection type fundamental wave signal band suppression circuit 4
1 is constituted by a band-pass filter 54 that passes a signal in the 60 GHz band. This bandpass filter 54
6 is shown in FIG. The band-pass filter 54 includes a plurality of signal lines 55 formed in a step-like and island shape on the InP substrate 51, and ground electrodes 56 formed on both sides of the signal lines 55. .
Note that λ3 shown in FIG. 6 is the in-line wavelength of the frequency signal in the 60 GHz band.

In the frequency multiplier 31,
As shown in FIG. 5, the transmission line 5 is connected to the gate of the HEMT 32.
7 is connected, and the other end of the transmission line 57 is grounded via the capacitor 38. The connection point between the transmission line 57 and the capacitor 38 is a voltage terminal 39 for supplying a gate bias. One end of a transmission line 58 is connected to the drain of the HEMT 32, and the other end of the transmission line 58 is grounded via a capacitor 48. And
A connection point between the transmission line 58 and the capacitor 48 is a voltage terminal 49 for supplying a drain bias.

Further, the configuration of the second embodiment other than that described above is the same as the configuration of the first embodiment. Therefore, in the second embodiment, substantially the same operation and effect as in the first embodiment can be obtained.

In each of the above embodiments, the InP substrate is used, but a GaAs substrate may be used instead. Further, in each of the above embodiments, the transmission line and the stub are constituted by the coplanar line 50, but may be constituted by a microstrip line. Furthermore, in each of the above embodiments, the transistor is constituted by the HEMT 32. However, the present invention is not limited to this. The transistor may be constituted by another FET (field effect transistor), or may be constituted by a bipolar transistor (for example, a hetero bipolar transistor). )
May be used.

In each of the above embodiments, one frequency multiplier is configured as one MMIC chip. However, the voltage controlled oscillator for supplying an input signal to the frequency multiplier and the frequency multiplier are configured as one MMIC chip. Alternatively, an amplifier circuit for amplifying a signal output from the frequency multiplier and the frequency multiplier may be configured as one MMIC chip, and a voltage-controlled oscillator, a frequency multiplier, and an amplifier The circuit may be configured as one MMIC chip.

Furthermore, in each of the above embodiments, the present invention is applied to a frequency multiplier constituting a part of a signal source for a millimeter wave radar system. However, the present invention is not limited to this. The present invention may be applied to a frequency multiplier constituting a part of a signal source for a system.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a perspective view of a coplanar line.

FIG. 3 is a diagram illustrating the operation of a transmission line.

FIG. 4 is a diagram showing a circuit pattern of a frequency multiplier.

FIG. 5 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 6 is a diagram showing a circuit pattern of a bandpass filter.

FIG. 7 is a diagram corresponding to FIG. 1 showing a conventional configuration.

[Explanation of symbols]

31 is a frequency multiplier, 32 is a high electron mobility transistor, 33 is an input matching circuit, 37 is an input terminal, 39 is a voltage terminal, 40 is a transmission line, 41 is a reflection type fundamental wave signal band suppression circuit, and 42 is output matching. Circuit, 43 is an open stub,
47 is an output terminal, 49 is a voltage terminal, 50 is a coplanar line, 51 is an InP substrate, and 54 is a bandpass filter.

Claims (7)

[Claims] 1. A frequency multiplier configured to input an input signal to a transistor through an input matching circuit and to output a multiplied output signal output from the transistor through a reflection type fundamental wave signal band suppression circuit and an output matching circuit. A frequency multiplier, wherein a transmission line having a predetermined length for generating a standing wave is provided between an output terminal of the transistor and an input terminal of the reflection type fundamental signal band suppression circuit. 2. The length of the transmission line, the phase of a fundamental wave signal output from the transistor, and the fundamental wave signal reflected by the reflection type fundamental wave signal band-suppressing circuit are further changed at the output terminal of the transistor. 2. The frequency multiplier according to claim 1, wherein the phase of the reflected signal is set to be the same. 3. The length of the transmission line, the fundamental wave signal output from the transistor and the fundamental wave signal reflected by the reflection type fundamental wave signal band suppression circuit are further reflected at the output terminal of the transistor. 2. The frequency multiplier according to claim 1, wherein the signals are set so as to have a mutually reinforcing phase relationship. 4. A phase difference between a fundamental wave signal output from the transistor and a signal reflected by an output terminal of the transistor, wherein the fundamental wave signal reflected by the reflection type fundamental signal band suppression circuit is further reflected by φd. (Degrees), the length of the transmission line is set so that the phase difference φd falls within the range defined by the following equation (1), so that the two signals reinforce each other. 4. The frequency multiplier according to claim 3, wherein: nx360-120 ≦ φd ≦ nx360 + 120 (1) where n is an integer. 5. A phase characteristic of a reflection coefficient ΓA as viewed from an output terminal of the transistor from the transmission line as φA, and a phase characteristic of a reflection coefficient ΓB as viewed from an input terminal of the reflection type fundamental wave signal band suppression circuit from the transmission line. Is φB, and the phase delay of the fundamental wave signal corresponding to the length Ld of the transmission line is φB.
The frequency multiplier according to claim 4, wherein when L is set, the phase difference φd is defined by the following equation (2). φd = (2 × φL) + φA + φB (2) Here, the phase delay φL (degree) is defined by the following equation (3). φL = (Ld / λ) × 360 (3) where λ is the wavelength in the transmission line of the fundamental signal. Also,
The reflection coefficients ΓA and ΓB have amplitude characteristics α and β in addition to the phase characteristics φA and φB, and are described as follows. (Equation 1) 6. When an even-order harmonic signal is output as the multiplied output signal, the reflection type fundamental wave signal band suppression circuit is configured to output one of the wavelengths λ in the transmission line corresponding to the fundamental wave signal frequency to be suppressed. The frequency multiplier according to any one of claims 1 to 5, wherein the frequency multiplier is constituted by an open stub having a length of / 4 or a short stub having a length of 1/2. 7. When outputting an odd-order harmonic signal as the multiplied output signal, the reflection-type fundamental signal band suppression circuit has a function of attenuating a signal corresponding to a fundamental signal frequency to be suppressed. The frequency multiplier according to any one of claims 1 to 5, comprising a bandpass filter.