JPH05274893A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To speed up the reading of a NAND cell type EEPROM without selection gate on the drain side. CONSTITUTION:The drains of memory cells M11, M12 on the bit line BL side out of memory cells M11 to M41, M12 to M42 constituting NAND cells (NAMD1, 2) are directly connected to a bit line BL without being passed through a selection gate and the sources of the memory cells M41, M42 are connected to source lines through section gates S1, S2. In the NAND cell having a selected memory cell in a data reading mode, 0V is applied to a selected word line and Vcc is applied to other non-selected word lines. In the non-selected NAND cell sharing the bit line with the NAND cell having the selected memory cell, voltage smaller than the threshold voltage of a memory cell set up at the time of erasing is impressed to the word line of at least one memory cell in the non-selected NAND cell and OV is applied to other non-selected word lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM) constructed by using a memory cell having a MOS transistor structure having a charge storage layer and a control gate.

[0002]

2. Description of the Related Art NAND is used as an EEPROM cell structure.
There is a type. The initially proposed NAND cell has a threshold voltage of 0 when data is written / erased.
This is a cell structure having a configuration in which a plurality of memory cells whose V is raised and lowered are arranged in series, and selection gates are connected in series to the drain side and the source side of the memory cells.
EEPRO by arranging D cells in a matrix
M memory array. In the case of this structure, generally, a plurality of NAND cells share one bit line.

By the way, in the case of a NAND type cell structure,
Reading is generally done by a precharge method. That is, first, prior to the actual reading, the source side select gate is closed and the bit line and the NAND connected to it are connected.
Charge the cell and then open the select gate. Then, when the cell to be read is in a state in which no data is written, the charge accumulated in the bit line flows to the source, and after a certain time, the potential of the bit line is almost 0V.
However, when the read cell is in the state where data is written, no current flows and the potential of the bit line does not drop. As described above, the reading of the NAND type cell adopts a method of discriminating the held data by the potential of the bit line after charging and discharging the bit line and the NAND cell connected thereto. Therefore, if the capacity (bit line capacity) to be charged / discharged is large, it takes time to charge / discharge and the read speed becomes slow. Therefore, in order to reduce the bit line capacitance, the non-read NAND cell is separated by using the drain side select gate at the time of reading to reduce the capacitance.

The first proposed NAND cell was as described above, but thereafter, a NAND cell without the select gate on the drain side was proposed from the above structure for the purpose of reducing the cell area. It was However, in the case of this structure, it is not possible to separate the non-read NAND cell among the plurality of NAND cells sharing the bit line by the drain side select gate. Therefore, non-read N
The AND cell also contributes to the bit line capacitance, which increases the bit line capacitance. Therefore, the NAND cell array in which the drain side select gate is abolished generally has a read speed of NAN having the drain side select gate.
It was suggested to be slower than the D cell array.

In the conventional case, a non-read NAND is used.
Although 0V was applied to the control gate of the memory cell in the cell, if there is a memory cell in which data is written and the threshold voltage is higher than 0V in the non-read NAND cell, the source side of this cell is set. The potential of the bit line is not transferred to the portion of, and does not contribute to the bit line capacitance. Therefore, the bit line capacitance changes significantly depending on the information written in each memory cell of the NAND cells sharing the bit line. For this reason, there is also a problem that the variation in read time becomes large.

[0006]

As described above, NAND is used.
If the drain side select gate is eliminated in the cell type cell structure, the cell area is reduced, but there is a problem that the reading time is very long. The present invention solves such a problem by a NAND type EEPROM memory cell,
And its operation method.

[0007]

According to the present invention, a plurality of non-volatile semiconductor memory devices are arranged in series, and a plurality of NAND type cells each having a selection gate on the source side thereof are included in the object of the present invention. EEPR sharing a bit line
An OM memory cell array is assumed. In the case of such a structure, the NA to be read at the time of reading
Non-read NAN sharing bit line with ND cell
There are D cells.

The operation principle of the above-described memory cell array newly proposed by the present invention is that the control gate of at least one memory cell among the control gates of the memory cells in such a non-read NAND cell is used when data is erased. The feature is that a voltage smaller than the threshold voltage of the memory cell transistor is applied.

At this time, the effect of the present invention is greatly exhibited when the memory cell for applying a voltage smaller than the threshold voltage of the memory cell transistor at the time of erasing to the control gate is closest to the bit line contact.

[0010]

In the NAND type cell having the select gate only on the source side, in the conventional reading method, at the time of reading,
The control gate of the memory cell in the non-read NAND cell sharing the bit line with the NAND cell to be read has been installed. Therefore, in the worst case, all NAND cells sharing the bit line contribute to the bit line capacitance. Therefore, the capacity of the bit line to be charged / discharged becomes large, which may cause a decrease in the reading speed.

Here, as shown in the present invention, the control gates of the memory cells in the NAND cells sharing the bit line are
If a voltage lower than the threshold voltage of the cell transistor is applied during data erasing, no current will flow in the memory cell located on the source side of this cell, so these cells will not reach the capacity to be charged or discharged during reading. Will not be involved. Therefore, the capacity to be charged / discharged is smaller than that in the conventional case, and is almost the same as in the case where the drain side also has a selection gate. Therefore, the read speed can be higher than that of the conventional write method, and even when the drain side select gate is omitted, the read time is almost the same as when the select gate is not omitted.
Can be provided.

Further, in the select gate of the memory cell closest to the bit line contact in the non-read NAND cell,
If a voltage smaller than the threshold voltage at the time of erasing is given, the non-read NAND cell is completely separated from the bit line. Therefore, the data written in the non-read NAND cell reduces the bit line capacitance. Problems such as change will be solved.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an EEPROM according to an embodiment of the present invention.
3 is a plan view showing the NAND cell of FIG. 2 (a) (b)
FIG. 3 is a sectional view taken along line AA ′ and BB ′. Also, in FIG.
It is an equivalent circuit of an AND cell.

In this embodiment, four memory cells M1 ...
M4 is directly connected in a form sharing the source and drain diffusion layers between adjacent ones to form a NAND cell. The drain of one end of such a NAND cell is directly connected to the bit line BL, and the source of the other end is connected to the common source line (ground line) via the selection gate S.
The control gates CG1 to CG4 of each memory cell are arranged in a direction intersecting the bit line BL to form a word line WL.

In this embodiment, four memory cells constitute one NAND cell, but in general, 2n power (n = 1, 2, ...) Memory cells form one NAND cell. Can be configured.

A specific memory cell structure is as shown in FIG. A p-type well 1'is formed on the n-type silicon substrate 1, and memory cells are arrayed in the p-type well 1 '. The peripheral circuit is formed in a p-type well different from the memory cell. Four memory cells and one select gate are formed in a region surrounded by the element isolation insulating film 2 of the p-type well 1 '.

Each memory cell has a floating gate 4 (41 to 4) made of first-layer polycrystalline silicon formed on the p-type well 1'through a first gate insulating film 31 made of a thermal oxide film.
4) is formed, and the control gate 6 is formed on the second layer polycrystalline silicon through the second gate insulating film 5 made of a thermal oxide film. The n-type layer 9 serving as the source / drain diffusion layer of each memory cell is directly connected to four memory cells in a form shared by adjacent ones.

At the source-side end of the NAND cell, the gate electrode 4 formed of the first-layer polycrystalline silicon is formed on the p-type well 1'through the gate insulating film 32 made of a thermal oxide film.
A select gate having 5 is formed. Here, the gate insulating film 32 may be the same as the first gate insulating film 31. Wirings 65 made of the second-layer polycrystalline silicon are arranged in an overlapping manner on the gate electrode 45. These gate electrodes 45 and the wirings 65 are connected by through holes at predetermined intervals to reduce the resistance.

Here, the floating gates 41 to 41 of each memory cell are
44, the control gates 61 to 64, and the gate electrode 45 of the select gate and the wiring 65 are patterned and aligned in the channel length direction using the same etching mask. The n-type layer 9 serving as a source / drain diffusion layer is formed by ion implantation of arsenic or phosphorus using these electrodes as a mask.

The substrate on which the elements are formed is covered with a CVD insulating film 7, and a bit line 8 is provided on the substrate with an A1 film. The drain at one end of the NAND cell is directly connected to the bit line 8 without passing through the select gate.

In such a configuration, the coupling capacitance C1 between the floating gate 4 of each memory cell and the substrate is
Is set smaller than the coupling capacitance C2 between the control gate 6 and the control gate 6. This relationship is as shown in FIG.
It is obtained by extending the floating gate 4 from above the element region to above the element isolation region. FIG. 4 shows two NAND cells sharing the bit line BL, and the read operation of the EEPROM according to the present invention will be described using this. Table 1 shows the potential of each part at the time of reading.

[0022]

[Table 1]

The following description will be given assuming that the cell to be read is M21. In this case, the word line WL1
Vcc is applied to 1, WL31, and WL41, and the selection gate SG
2 and WL21, WL22 to WL42, 0V, WL1
A voltage smaller than the threshold voltage of the memory cell at the time of erasing data is applied to 2. In addition, 0V is initially applied to the selection gate SG1.
Is given to keep the current from flowing. In this state, Vcc is applied to the bit line BL and the bit line and NAND
Charge the cell (precharge). After Uricharge
The power supply that applies Vcc to the bit line is disconnected, Vcc is applied to the select gate SG1, and SG1 is opened.
When data is written in M21, the threshold voltage is higher than 0V, so that no current flows from the bit line to the source and the potential of the bit line is kept at Vcc. However, when M21 is in a data erased state, the threshold voltage is lower than 0V, so that a current flows from the bit line to the source, and the potential of the bit line becomes almost 0V after a certain period of time. The held data is discriminated by checking the potential of the bit line after this fixed time.

Generally, in the NAND type EEPROM, since the threshold voltage of the memory cell transistor at the time of erasing is about -2 to -3V, the voltage applied to the WL12 may be set to about -5V.

In the case of the conventional read method, the potential applied to WL12 is 0 V, so that the potential of the bit line may be transmitted to the NAND cell 2. Worst case, M
When 12 to M42 are in a state where data is erased, the cells of M12 to M42 also add to the capacity for charging and discharging in the above reading sequence. As a result, since the time required for charging and discharging increases, it is necessary to take a long time from opening SG1 to reading the potential of the bit line, which slows the reading.

However, in the read method of the present invention, the WL
Since a potential lower than 0 V is applied to 12 to make sure that no current flows in M12, the potential is not transmitted to the NAND cell 2, and the charge / discharge capacity in the read sequence can be made smaller than that in the conventional method. Therefore, it is possible to provide higher-speed reading as compared with the conventional method.

In the example shown here, of the word lines WL12 to WL42 connected to the select gates of the memory cells in the non-read NAND cell (NAND2), only the negative voltage is applied to WL12 and 0V is applied to WL22 to WL42. Was there. However, the effects of the present invention can be obtained even when a negative voltage is applied to WL22 to WL42 as in the case of WL12.
Although the effect is small, the effect of the present invention can be obtained by applying 0V to WL12 and applying a negative voltage to at least one of the other word lines.

In this embodiment, one bit line is connected to two N
Although an example in which the AND cells are shared is used, generally, one bit line is shared by many NAND cells, for example, 128 NAND cells. The present invention exerts a great effect in such a case.

The present invention is not limited to the above embodiment. Although the FETMOS type memory cell having the floating gate and the control gate is used in the embodiment, the present invention can be similarly applied to the case of using the MNOS type memory cell.

[0030]

As described above, according to the present invention,
It is possible to reduce the capacity that has to be charged and discharged when reading, and even when the drain side select gate is omitted,
It is possible to provide a NAND cell type EEPROM whose reading time is almost the same as that before the omission.

[Brief description of drawings]

FIG. 1 is an NAN of an EEPROM according to an embodiment of the present invention.
The top view of D cell.

FIG. 2 is AA ′ and BB of the NAND cell of FIG.
′ Sectional view.

FIG. 3 is an equivalent circuit diagram of the NAND cell.

FIG. 4 is an equivalent circuit diagram of two NAND cell units sharing a bit line.

FIG. 5 is a diagram showing a bit line potential at the time of reading.

FIG. 6 is a timing chart at the time of reading.

[Explanation of symbols]

 M1 to M4 ... Memory cells M11 to M41 M12 to M42 ... Memory cell S ... Select gate BL ... Bit lines CG1 to CG4 ... Control gate line CG ... Select gate line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/792 H01L 29/78 371

Claims (3)

[Claims] 1. A source layer and a drain layer are formed by a second-conductivity-type impurity diffusion layer on a first-conductivity-type semiconductor substrate, and further, a first gate insulating film, a charge storage layer, and a second gate in this order. A plurality of nonvolatile semiconductor memory cells that are stacked and electrically rewritable by giving charges between the charge storage layer and the substrate are connected in series, and a select gate transistor is connected in series on the source side. Composed of N
AND cells are arranged in a matrix to form a NAN
In the non-volatile semiconductor memory device configured by connecting the drain on one end side of the D cell to the bit line and connecting the control gate of each memory cell to the word line, at the time of reading,
A potential smaller than the threshold voltage of the memory cell transistor at the time of erasing data is applied to the control gate of the memory cell located closest to the bit line contact of the non-read NAND cell sharing the bit line with the NAND cell to be read. A non-volatile semiconductor memory device characterized by: 2. A source layer and a drain layer are formed of a second-conductivity-type impurity diffusion layer on a first-conductivity-type semiconductor substrate, and further, a first gate insulating film, a charge storage layer, and a second gate in this order. A plurality of nonvolatile semiconductor memory cells that are stacked and electrically rewritable by giving charges between the charge storage layer and the substrate are connected in series, and a select gate transistor is connected in series on the source side. Composed of N
AND cells are arranged in a matrix to form a NAN
In the non-volatile semiconductor memory device configured by connecting the drain on one end side of the D cell to the bit line and connecting the control gate of each memory cell to the word line, at the time of reading,
To the control gates of all memory cells of the non-read NAND cell that shares the bit line with the read NAND cell,
A non-volatile semiconductor memory device characterized by applying a potential smaller than a threshold charge of a memory cell transistor at the time of erasing data. 3. A source layer and a drain layer are formed of a second conductivity type impurity diffusion layer on a first conductivity type semiconductor substrate, and further, a first gate insulating film, a charge storage layer, and a second gate in this order. A plurality of nonvolatile semiconductor memory cells that are stacked and electrically rewritable by giving charges between the charge storage layer and the substrate are connected in series, and a select gate transistor is connected in series on the source side. Composed of N
AND cells are arranged in a matrix to form a NAN
In the non-volatile semiconductor memory device configured by connecting the drain on one end side of the D cell to the bit line and connecting the control gate of each memory cell to the word line, at the time of reading,
Non-volatile, characterized in that a potential smaller than the threshold voltage of the memory cell transistor at the time of data erasing is applied to the control gate of at least one memory cell in the non-read NAND cell sharing the bit line with the NAND cell to be read. Semiconductor memory device.