JPH05274216A - Image memory - Google Patents

Abstract

PURPOSE:To provide the image memory which can process the change of image data in the row direction such as the density projection of images easily at high speed by selectively driving the access of the image memory not only from the conventional row direction but also from a transfer gate and a serial access memory (SAM) in the column direction. CONSTITUTION:The data lines of respective memory cells in a cell array 1 are connected through transfer gates 7a and 7b to a column SAM 8a and a row SAM 8b. When the row transfer gate 7b and the row SAM 8b connected to the data line in the column direction are selected by a select signal, the respective memory cells on the (x) columns of the cell array 1 and the row SAM 8b exchange data at high speed synchronously with a control signal SC, and the row SAM 8b can transfer serial I/O data from the outside at high speed synchronously with the control signal SC so that the image data in the column direction can be easily changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory for storing digitized image data, and more particularly to an image which can be selectively serially accessed in either the row direction or the column direction of the image memory. Regarding memory.

[0002]

2. Description of the Related Art A conventional image memory is shown in FIG.
The structure is such that That is, in FIG.
Therefore, 1a has 51 memory cells corresponding to pixels for one screen.
Consists of dynamic RAM arranged in 2 rows and 512 columns
The cell array is composed of four layers. That
The cell array 1a has an addressing circuit A₁And whereabouts
512 address lines and columns in each direction
It is connected by 512 data lines. Also,
The cell array 1a is a serial data transfer circuit B ₁And column direction
Are connected by 512 data lines. And
Cell array 1a and addressing circuit A₁And serial
Data transfer circuit B₁To carry out the exchange of information with
Timing generator that generates various timing signals
Equipped with 13.

The address designation circuit A ₁ is stored in the column address buffer 2 and the column address buffer 2 and the row address buffer 3 which respectively receive address data (A _{0 to} A ₈ ) supplied from the outside at a predetermined timing. and the address data (a ₀ ~A ₈₎ row decoder 5 which enter decodes the address data stored in input to the column decoder 4 and the row address buffer 3 and decodes (a ₀ ~A ₈₎ a dynamic RAM The cell array 1a is composed of a refresh counter 6 and a sense amplifier 6a for periodically refreshing the cell array 1a.

The column decoder 4 is arranged in the cell array 1
The row decoder 5 is connected by 512 address lines respectively corresponding to the respective column addresses of a.
They are connected by 512 address lines respectively corresponding to the row addresses of a. Further, the sense amplifier 6a is connected by 512 data lines respectively corresponding to each column data of the cell array 1a.

The cell array 1a has a dynamic R
Since it is composed of AM, a refresh cycle for periodically refreshing data is necessary. For this reason, the refresh counter 6 is connected to the row address buffer 3 and the contents of the row address buffer 3 are updated, so that the specified row is updated. The entire contents of the cell array are read by the sense amplifiers 6a arranged in the column direction, and then the contents are rewritten to the same cell array to complete the operation, and this operation is performed for all rows.

Next, the serial data transfer circuit B ₁ includes a transfer gate 7a and a SAM (serial access memory) 8a for collectively transferring data in any row of the cell array 1a.
A serial selector 9 connected to each memory element of the SAM 8a, and a serial input buffer 11 and a serial output buffer 12 which are connected to the serial selector 9 and are buffer circuits for serially inputting / outputting with the outside.
And a serial address counter 10 which is connected to the serial selector 9 and sets a start address for serial transfer.
It consists of and.

Since a static circuit is used for the SAM 8a, refresh is unnecessary. Then, the serial selector 9 serially transfers data between the serial input buffer 11 and the serial output buffer 12 according to the address designation from the serial address counter 10.

Various control signals for controlling the above operation are externally supplied to the timing generator 13. Since a SAM 8a capable of inputting / outputting image data for one row is connected to the cell array 1a, a row address, a column address, and other read control signals are given to the image memory, as shown in FIG. In addition, the image data stored in the cell array of any row of the image memory can be read out to the SAM 8a and sequentially read out through the serial output buffer 12 as shown in FIG.

In the case of writing the image data, the data is input to the serial input buffer 11 and the row address, the column address and other write control signals are given to the image memory, so that the image data serially input to the SAM 8a can be obtained. It is configured such that data can be sequentially written in the cell array of any row of the image memory.

[0010]

However, in the conventional image memory described above, when image data for one row is serially output in the row direction as shown in FIG. 7A, one read operation is performed. Transfer cycle (cell array to S
Input data to AM) and serial read (SA
The process of serially outputting image data from M to the outside through the serial output buffer 12) may be performed. However, when data of one column is serially output in the column direction as shown in FIG. The read transfer cycle and the serial read must be performed once, so that it takes processing time to read the image data in the column direction such as image density projection, make a change, and store the changed image data again. There were unresolved issues.

Therefore, the present invention has been made by paying attention to the above-mentioned unsolved problems of the prior art, and makes it possible to selectively drive either the row-direction or column-direction serial access means for accessing the image memory. By increasing the degree of freedom in the selection of the serial transfer direction and selecting the latter, it is possible to provide an image memory that can easily deal with changes in the image data in the column direction such as image density projection and can shorten the processing time. Has a purpose.

[0012]

To achieve the above object, an image memory according to the present invention is provided with a transfer gate and a serial access memory connected in the row direction of a cell array arranged in the row direction and the column direction. An image memory having a row-direction serial access means configured by: a column-direction serial access means including a column-direction transfer gate connected in the column direction of the cell array and a serial access memory; It is characterized in that it is provided with selection means for selecting either one of the directional serial access means.

[0013]

According to the present invention, in the image memory having the row-direction serial access means connected to the cell array, the column-direction serial access means connected in the column direction of the cell array and the row-direction and column-direction serial access means. Since the selection means for selecting either one of the two is provided, if the row-direction serial access means is selected by the selection means, the serial image data in the row direction can be transferred, and if the one-column direction serial access means is selected, the column direction is selected. The serial image data can be transferred and the degree of freedom in selecting the serial access direction is increased.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of an image memory showing an embodiment of the present invention. In FIG. 1, the image memory is composed of one cell array, an A addressing circuit, a B serial data transfer circuit, a C selecting circuit, and a D timing generator circuit.

In the cell array 1, memory cells are arranged in n rows and m columns (for example, 512 rows and 512 columns), and each memory cell corresponds to one corresponding pixel in n × m pixels. The cell array 1 is connected to the addressing circuit A by n address lines in the row direction, m address lines in the column direction, and m data lines in the column direction. Further, the cell array 1 includes a serial data transfer circuit B
Are connected by n data lines in the row direction and m data lines in the column direction.

The address designating circuit A is almost the same as the address designating circuit A ₁ described in the conventional example, and is a column address for receiving address data (A _{0 to} A _i ) supplied from the outside at a predetermined timing. A buffer 2 and a row address buffer 3, and a column decoder 4 and a row address buffer 3 for inputting and decoding the address data (A _{0 to} A _i ) stored in the column address buffer 2.
A row decoder 5 for inputting and decoding the address data (A _{0 to} A _i ) stored in the memory, a refresh counter 6 for periodically refreshing the cell array 1 composed of a dynamic RAM, and a sense amplifier 6a. Has been done.

The column decoder 4 is arranged in the cell array 1
Are connected by m address lines respectively corresponding to the respective column addresses, and the row decoder 5 is connected by n address lines respectively corresponding to the respective row addresses of the cell array 1. Further, the sense amplifier 6a is connected by m data lines respectively corresponding to each column data of the cell array 1.

The refresh operation of the cell array 1 is similar to that of the conventional example, and therefore its explanation is omitted. Next, the serial data transfer circuit B includes a column transfer gate 7a and a column S for collectively transferring the data in any row of the cell array 1.
AM8a, row transfer gate 7b and row SAM8b for collectively transferring data in any column of cell array 1, serial selector 9 connected in parallel corresponding to each memory element of column SAM8a and row SAM8b, and serial selector 9. It is composed of a serial input buffer 11 and a serial output buffer 12 which are connected to each other to serially input / output with the outside, and a serial address counter 10 which is connected to the serial selector 9 and sets a start address for serial transfer. ..

The row SAM 8b and the column SAM 8a
Since a static circuit is used for this, refresh is unnecessary. Then, the serial selector 9 follows the address designation from the serial address counter 10.
Serial input buffer 11 and serial output buffer 1
Data is serially transferred between the two.

Next, the selection circuit C outputs the image data for one row designated in the row direction of the cell array 1 to the column transfer gate 7a.
Via the row transfer gate 7b, or between the row SAM 8a via the row transfer gate 7b and image data for one designated column in the column direction of the cell array 1 via the row transfer gate 7b. That is, the SAM selection signal 14 and its inverted signal supplied from the outside are connected to the column transfer gate 7a and the row transfer gate 7b, and one of the gates is in a passing state and the other is in a prohibiting state. Further, the SAM selection signal 14 and its inverted signal supplied from the outside are connected to the column address buffer 2 and the row address buffer 3 together with SC (serial clock) which will be described later, and the serial address counter 10 corresponding to the pass gate. Either the address information from the column address buffer 2 or the row address buffer 3 supplied to the memory is selected.

Next, in the timing generator circuit D, in order to generate various timing signals for exchanging information between the cell array 1 and the addressing circuit A and the serial data transfer circuit B, RAS- ( Each control signal such as row address strobe), CAS- (column address strobe), OE- (output enable), WE- (write enable), SC (serial clock), SE- (serial enable) is input (note that ,
Signals with a minus sign at the end of the above signal names are
"L" level indicates a significant signal).

Here, RAS- takes in row addresses A _{0 to} A _{i at} the fall of RAS-. SAM
RAS is selected during the transfer cycle by selecting the selection signal 14.
The low SAM start address is fetched at the falling edge of-. CAS- is, A ₀ ~ by the fall of the CAS-
Take in the column address of A _i . SAM selection signal 14
In the transfer cycle, the start address of the column SAM is fetched at the fall of CAS-.

OE- becomes a data transfer cycle when OE- is at "L" level at the fall of RAS- (or CAS-) by the selection of SAM selection signal 14, and cell array 1 and column SAM 8a (or row SAM 8).
Control data transfer to and from b). WE-
Is selected by the SAM selection signal 14 and, in the data transfer cycle, when it is at the "H" level at the falling edge of RAS- (or CAS-), read transfer [cell array 1
From column to column SAM 8a (or row SAM 8b)], and at the "L" level, write transfer [column SA
Transfer from M8a (or raw SAM8b) to the cell array 1].

The SC counts up the column address buffer 2 or the row address buffer 3 by the SAM selection signal 14 and its inverted signal, and serializes the data from the SAM start address in synchronization with the rising edge of the SC. Can be output. In the case of the serial input mode, the data serially input in synchronization with the SC can be taken into the SAM.

In SE-, the state of another control signal is, for example, R.
When AS- is in the falling state and CAS- is at "H" level and OE- and WE- are at "L" level,
If it is at "L" level, write transfer [column SAM8a
(Or transfer from row SAM 8b) to cell array 1]
The input / output mode of the SAM port changes from the output mode to the input mode, and if it is at “H” level, the pseudo write transfer is performed and the input / output mode of the SAM port changes from the output mode to the input mode.

Here, the read transfer means to load the selected one row (or one column) of data in the cell array 1 into the column SAM 8a (or row SAM 8b), and the write transfer means. It means to transfer m-bit (or n-bit) data captured in the column SAM 8a (or row SAM 8b) by serial input to the cell array on the selected row (or column) in the cell array 1.

Here, the column transfer gate 7a and the column SAM 8a correspond to the row-direction serial access means, the row transfer gate 7b and the row SAM 8b correspond to the column-direction serial access means, and the selection circuit C serves as the selection means. It corresponds. Next, the operation of the above embodiment will be described. Now, it is assumed that image data is stored in the cell array 1 of FIG. Here, a case of serially outputting data for one column of an arbitrary column will be described.

First, the SAM selection signal 14 is set to a state of selecting the row transfer gate 7b and the row SAM 8b. In this state, the column transfer gate 7a is disabled and the serial selector 9 controls the gate so that the data from the row SAM 8b is input. Next, based on the addresses A _{0 to} A _i supplied from the outside, for example, x is set in the column address buffer 2 at the fall of the CAS- signal, and zero is set in the row address buffer 3 at the fall of the RAS- signal. To do. At this time, each control signal is assumed to be input from the outside at a predetermined timing.

Here, when the control signal is controlled and one read transfer cycle is performed, the address 0 is assigned to the row decoder 6 due to the fall of the RAS- signal, and the address x is assigned to the column decoder 5 due to the fall of the CAS- signal. Is output,
When the SC signal input to the row address buffer 3 counts up in the row address buffer 3 depending on the state of the SAM selection signal 14, the row decoder 6 synchronizes with the SC signal from address 0 to address (n-1). The image data of the cell array 1 to be serially output is selected by address shifting. That is, image data for one column of x columns is set in the row SAM 8b through the row transfer gate 7b. Next, the start address of the serial pointer of the row SAM 8b operates so as to be taken into the serial address counter 10 from the addresses A _{0 to} A _i supplied from the outside at the falling edge of the RAS- signal. The read transfer cycle is completed at the rising edge of the OE- signal. In this state, serial read is performed and S
Each time one C (serial clock signal) is input, the image data in the row SAM 8b is incremented by 1 in the order of the row address in which the serial address counter 10 fetches the image data.
Each of them enters the serial output buffer 12 through the serial selector 9 and is output to the outside.

The number of serial clock signals SC depends on the value of the start address set in the serial address counter 10. In the case of the description here, the data for one column of an arbitrary column is serially output. Therefore, the serial clock signal SC is the sum of n for the number of rows and n for the serial read. 2n minutes will be input.

Next, the case of serially inputting data for one column of an arbitrary column will be described. In this case, first, the SAM selection signal 14 is set to a state of selecting the row transfer gate 7b and the row SAM 8b. In this state, the column transfer gate 7a is in the prohibited state. In the serial selector 9, image data from the outside is stored in the low SAM 8b.
Control the gate to enter. Next, on the basis of the addresses A _{0 to} A _i supplied from the outside, the column address buffer 2 receives, for example, x when the CAS- signal falls.
Is set to zero in the row address buffer 3 by the fall of the RAS- signal. At this time, the WE- signal is set to "L" level and the SE- signal is set to "L" level. At this time, each control signal is assumed to be input from the outside at a predetermined timing.

Here, when serial writing is performed, each time one SC (serial clock signal) is input from the outside, image data is passed through the serial input buffer 11 to the serial selector 9 one by one in the ascending order of row address. Through to the raw SAM 8b. Then
When the control signal is controlled and one write transfer cycle is performed, the address 0 is output to the row decoder 6 due to the fall of the RAS- signal and the address x is output to the column decoder 5 due to the fall of the CAS- signal. In accordance with the state of 14, the SC signal input to the row address buffer 3 counts up the row address buffer 3 so that the row decoder 6 shifts the address from address 0 to address (n-1) in synchronization with the SC signal. Then, the image data for one column is written in the x column of the cell array 1 to which the image data should be serially input. In this state, the number of serial clock signals SC is (number of rows n) × 2.

Next, as shown in FIG. 3, in the case of serially inputting / outputting data for one row of an arbitrary row, the SAM selection signal 14 is set to the opposite state to the above-mentioned case, and the column The transfer gate 7a and the column SAM 8a are selected, the row transfer gate 7b is disabled, and then the column address buffer 2 is supplied to the column address buffer 2 at the fall of the CAS- signal based on the addresses A _{0 to} A _i supplied from the outside. Zero
If y is set in the row address buffer 3 by the fall of the RAS- signal, the timing of the control signal may be set in the same manner as described above, and the description thereof will be omitted.

According to the above embodiment, since image data for one column of an arbitrary column can be serially input / output at high speed, it is possible to easily deal with the change of image data occurring in the column direction and the serial input / output matrix. The freedom of direction selection is increased.
In the above embodiment, one cell array of n rows and m columns is used.
Although the layers have been described, the present invention is not limited to this, and L
The cell array and peripheral circuits can be multi-layered within the allowable range of the number of pins of the SI package.
Can also be arbitrarily determined in relation to the number of address bits.

Further, in the above embodiment, the cell array 1
When inputting and outputting the image data for one column or one row of
Column address buffer 2 and row address buffer 3
The SC signal is input to and one of the buffers counts up from 0 depending on the state of the SAM selection signal 14
Although the method of performing the address scan in synchronization with the signal has been described, the invention is not limited to this, and the SC signal is input to the column decoder 4 and the row decoder 5, and the SAM selection signal 1
Depending on the state of 4, any one of the decoders may operate as a shift register synchronized with the SC signal, and address scanning may be performed from address 0.

[0036]

As described above, according to the image memory of the present invention, serial input / output transfer of image data in the row direction and serial input / output transfer of image data in the column direction can be selected. In addition to increasing the degree of freedom, the image data in any column can be changed quickly and easily by selecting the latter, improving the processing speed when performing processing such as image density projection. There is an effect that can be achieved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an image memory according to an embodiment.

FIG. 2 is a diagram for serially inputting and outputting image data for one column in the column direction in the image memory of the embodiment.

FIG. 3 is a diagram for serially inputting and outputting image data for one row in a row direction in the image memory of the embodiment.

FIG. 4 is a schematic configuration diagram of a conventional image memory.

FIG. 5 is a diagram for serially inputting and outputting image data for one row in a row direction in an image memory of a conventional example.

FIG. 6 is a time chart of serially input / output data in FIG.

FIG. 7 is a diagram showing the disadvantages of the conventional image memory.

[Explanation of symbols]

 1, 1a Cell array 2 Column address buffer 3 Row address buffer 4 Column decoder 5 Row decoder 6 Refresh counter 6a Sense amplifier 7a Column transfer gate 7b Row transfer gate 8a Column SAM 8b Row SAM 9 Serial selector 10 Serial address counter 11 Serial input buffer 12 Serial output buffer 13 Timing generator 14 SAM selection signal A Address designation circuit B Serial data transfer circuit C selection circuit D Timing generator circuit

Claims (1)

[Claims] 1. An image memory having row-direction serial access means, which is connected in the row direction of a cell array arranged in the row direction and the column direction and is composed of a transfer gate in the row direction and a serial access memory, wherein columns of the cell array are provided. Column-direction serial access means composed of column-direction transfer gates and serial access memory connected in the direction,
An image memory, comprising: selecting means for selecting one of the row-direction and column-direction serial access means.