US6243837B1 - Microcomputer with the capability of suppressing signals which reset a watchdog-timer - Google Patents

Microcomputer with the capability of suppressing signals which reset a watchdog-timer Download PDF

Info

Publication number
US6243837B1
US6243837B1 US08397157 US39715795A US6243837B1 US 6243837 B1 US6243837 B1 US 6243837B1 US 08397157 US08397157 US 08397157 US 39715795 A US39715795 A US 39715795A US 6243837 B1 US6243837 B1 US 6243837B1
Authority
US
Grant status
Grant
Patent type
Prior art keywords
microcomputer
program
volatile memory
operating
operating state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US08397157
Inventor
Jürgen Zimmermann
Walter Grote
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0754Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A microcomputer (10) is proposed, which includes a central processing unit (11), a non-volatile memory (13), a volatile memory (14), a monitoring circuit (12) and also an input/output unit (16). Two different operating states are possible in the microcomputer (10). In the first operating state, the microcomputer executes a program which is located in the non-volatile memory (13). In the second operating state, the microcomputer (10) executes a program which is located in the volatile memory (14). The monitoring circuit (12) effects a resetting of the microcomputer (10) whenever it does not receive a monitoring signal for a predetermined time (watchdog timer). The microcomputer is distinguished in that it includes an element for suppressing monitoring signals which are always active whenever the microcomputer (10) is operating in the second operating state.

Description

BACKGROUND OF THE INVENTION

The microcomputer according to the invention is based on a microcomputer of the generic type of the main claim. Data Sheet MC 68 F 333 TS/D, Motorola 1992, already discloses a microcomputer which has, apart from the central processing unit, a programmable, non-volatile memory (flash EEPROM), input/output components, a monitoring circuit (watchdog timer), and also a volatile memory (code RAM), into which there can be written program data which can be accessed by the instruction counter of the central processing unit. All the said components are integrated on a chip. The microcomputer is configured such that it can both access program data which are located in the programmable, non-volatile memory and can execute a program which is located in the volatile memory. In both cases, the monitoring circuit is activated, ie. it must be ensured that, in the case of regular program flow, the monitoring circuit is reset at the correct time, since otherwise the monitoring circuit carries out a resetting of the microcomputer. A disadvantage of this microcomputer is that haphazard changes of the memory content in the volatile memory (for example due to interfering EMC radiation) can cause the forming a situation in which the monitoring circuit is reset at the correct time although the program flow is irregular.

SUMMARY OF THE INVENTION

The microcomputer according to the invention having the characterizing features of the main claim has in comparison the advantage that in it there is a separation between execution of a program in the programmable, non-volatile memory (ROM mode) and execution of a program in the volatile memory (RAM mode). The separation is constituted by the fact that resetting of the monitoring circuit is not possible at all in the second operating state (RAM mode). A resetting of the monitoring circuit can take place only in the first operating state (ROM mode). The forming of an EMC radiation-induced program loop in which resetting of the monitoring circuit at the correct time occurs in spite of a disturbed program flow is in this way made more difficult.

It is advantageous on the one hand that the selection of the at least two different operating states of the microcomputer takes place implicitly by a decoding of the address space. As a result, the programming effort is kept low. On the other hand, it is advantageous if the selection of the at least two different operating states takes place by an explicit switching-over of operating modes of the microcomputer. This achieves a more pronounced separation of the two operating states, so that a programmer can keep a better check on the operating states.

Furthermore, it is particularly advantageous that the microcomputer includes a program flow counter. This counter is activated at least whenever the microcomputer is operating in the second operating state (RAM mode). The program flow counter, which in the case of regular program flow is respectively set in a defined way after a certain number of program instructions, makes an additional check on the program flow possible.

It is furthermore advantageous that there are included in the microcomputer means which check the reading of the program flow counter and suppress the emission of monitoring signals if the checking of the program flow counter indicates an irregular program flow. This virtually rules out the forming of an EMC interference-induced program loop in which monitoring signals are emitted at the correct time in spite of irregular program flow.

For simple checking of the reading of the program flow counter, it is advantageous that the microcomputer has a reference counter, which is incremented before each checking of the reading of the program flow counter, that it has means which compare the current counter reading of the program flow counter with the current counter reading of the reference counter and that it detects an irregular program flow if the counter readings of program flow counter and reference counter do not match.

For a simple way of realizing a suppression of monitoring signals it is advisable to provide in the microcomputer a configuration register in which, if there is a change of operating state (from ROM mode to RAM mode), a flag in the configuration register is set, whereby an electronic device is switched in such a way that it blocks the line for the transmission of monitoring signals.

BRIEF DESCRIPTION OF THE DRAWINGS

An exemplary embodiment of the invention is represented in the drawing and explained in more detail in the following description.

FIG. 1 shows a basic block diagram for an exemplary embodiment of the invention;

FIG. 2 shows a block diagram of a microcomputer according to the invention;

FIG. 3 shows a more detailed cutout of the central processing unit of the microcomputer according to the invention;

FIG. 4 shows a first structured chart for a program for execution in the microcomputer according to the invention;

FIG. 5 shows a second structured chart for a program for execution in the microcomputer according to the invention and

FIG. 6 shows a third structured chart for a program for execution in the microcomputer according to the invention.

DESCRIPTION OF THE INVENTION

In FIG. 1, the reference numeral 10 denotes a microcomputer. Connected to the microcomputer 10 is a development computer 9. The connection between microcomputer 10 and development computer 9 is realized with the aid of a serial data transmission line 8. The exemplary embodiment relates to the field of application of control devices. In this case, the control device is intended to represent an engine control device. For the sake of simplicity, only the microcomputer 10 of the control device is shown. During the application phase of the development of a control device, in particular the optimum program flows for the control device are to be determined. For this purpose, the program flow of the control device is changed, sometimes several times. The effects of the changes are then determined by test runs of the control device. The changes of the program flows relate predominantly to certain program parts of the program flow. Thus, a completely new program does not have to be programmed into the memory of the microcomputer every time. If the control device or the microcomputer of the control device has a code RAM, this code RAM can be advantageously utilized for the application. New programs can namely be written into this code RAM in a simple way, without having to carry out lengthy programming operations of programmable, non-volatile memories. The design of such an engine control device is known per se from the prior art. The engine control device calculates on the basis of input variables of the engine, for example the injection times and also the ignition points for the individual cylinders of the internal-combustion engine. The calculation of these control values takes place by computation algorithms known per se. There are, however, various possibilities for the computation algorithms. To determine here the optimum computation algorithm for the engine, the application system described here is to be used. In optimizing the program flow for the control device, the applicator attempts to find a compromise between the accuracy of the control value calculation on the one hand and the computing time requirement needed for this on the other hand.

To achieve computation results which are as accurate as possible, it is often advisable to use as many parameters as possible of the internal-combustion engine (such as for example speed, engine load, engine temperature, air temperature, battery voltage etc.). On the other hand, the engine load and the speed are sufficient for calculating injection times and ignition points. First control values are often calculated just from these two variables. In order to bring other parameters into the calculation, often just a correction of the previously calculated control values takes place. The exemplary embodiment relates to the correction of the roughly precalculated control values for ignition angles and injection times for the individual cylinders of a six-cylinder internal-combustion engine on the basis of the engine temperature as an additional operating parameter.

The microcomputer 10 of the control device has a design such as that represented in FIG. 2. In it, the reference numeral 11 denotes the CPU of the microcomputer. The reference numeral 12 denotes a monitoring circuit, which has also become known in the literature by the term watchdog timer. A programmable, non-volatile memory is denoted by the reference numeral 13. The reference numeral 14 denotes a volatile memory (code RAM), which has as a special feature the option of being configured as a program memory for the CPU 11. Finally, the reference numeral 16 denotes the input/output components of the microcomputer. A serial interface is also intended to be included therein.

FIG. 3 shows a more detailed cutout of the central processing unit 11 of the microcomputer 10. In the central processing unit 11 there is provided a configuration register 20. The configuration register 20 comprises a number of flags. Two flags are particularly highlighted here. The flag 21 is always set whenever the microcomputer 10 is operating in the first operating state (ROM mode), ie. it is executing the program in the non-volatile memory 13. If, on the other hand, the microcomputer is operating in the second operating state (RAM mode), the flag 21 is not set. The status of the flag 21 is passed via a line 23 to a first input of an AND gate 24. The status of the flag 22 is fed to the second input of the AND gate 24. The flag 22 is set only briefly with the aid of a subroutine of the microcomputer 10, namely whenever a monitoring signal is to be emitted to the monitoring circuit 12. This signal can pass to the monitoring circuit 12 only when the flag 21 is set. Otherwise, the AND gate 24 blocks these signals.

In the monitoring circuit 12, a time counter runs up during operation of the microcomputer 10. As soon as this time counter produces an overflow, a resetting of the microcomputer 10 is instigated by the internal logic of the monitoring circuit 12. In FIG. 3, the resetting signal is emitted via the line 18 to the central processing unit 11. The monitoring circuit 12 thus functions in such a way that the internal time counter has to be successively reset before the time counter produces an overflow. Only if this resetting takes place at the correct time does the resetting of the microcomputer 10 not take place. Therefore, the programmer has to take care that, in the case of a regular program flow, resetting of the monitoring circuit 12 at the correct time takes place. For this purpose, the programmer inserts into the program corresponding instructions at defined program points. The program flow in the microcomputer 10 is explained in more detail below with reference to FIGS. 4, 5 and 6.

In FIG. 4, the reference numeral 30 denotes the program start. After the program start 30, an initialization of the microcomputer 10 takes place in the program step 31. In the interrogation 32, it is interrogated whether the external development computer 9 is connected to the microcomputer 10. If the result of the interrogation is yes, in the program step 33 an application function is loaded into the code RAM 14 of the microcomputer 10. If the development computer 9 was not connected to the microcomputer 10, the program step 33 does not take place. In the program step 34, the operating parameter acquisition for the controlling operation then takes place. In this, the engine speed and engine load are thus determined, inter alia. In the program step 35, the rough control values are calculated on the basis of the acquired operating parameters of engine speed and engine load. In the program step 36, the application function, which was previously loaded into the code RAM 14, is executed. Subsequently, in the program step 37, the control function execution takes place. After that, a first computation cycle has been completed, and the next computation cycle is started with program step 34.

In FIG. 5, a more detailed structured chart of the application function is shown. The call-up of the application function is indicated by the reference numeral 40. First of all, in the program step 41, a switching-over of the operating state (from ROM mode to RAM mode) is then carried out. During this, the flag 21 in the configuration register 20 is reset. Then, in the program step 42, the correction of the first control values (ignition point and injection time for cylinder 1 of the internal-combustion engine) takes place on the basis of the additional application function. After the program step 42, a program flow counter is set to “1” in the program step 43. Subsequently, in the program step 44, the subroutine call-up takes place for the resetting of the monitoring circuit 12. After this subroutine call-up 44, the next action to take place is the correction of the control values 2 (ignition point and injection time for cylinder 2 of the internal-combustion engine). This is not shown in any more detail in FIG. 5, since the program steps 42, 43 and 44 are virtually repeated for this. Therefore, we have dispensed with a separate representation of these program steps. Finally, after the correction of the control values 1-5, the correction of the control values 6 is carried out in the program step 45. After that, in the program step 46, the program flow counter is newly set and, in the program step 44, the subroutine for resetting the monitoring circuit 12 is called up. If this subroutine is correctly executed, the switching-over from RAM mode to ROM mode subsequently takes place in the program step 47. The application function ends with the return 48 to the main program.

The subroutine which effects the resetting of the monitoring circuit is explained below with reference to FIG. 6. After the call-up of the subroutine 49, a switching-over of the operating state of the microcomputer 10 takes place in the program step 50, to be precise by switching over from RAM mode to ROM mode. In this case, the flag 21 in the configuration register 20 is set. Subsequently, it is checked in interrogation 52 whether the program flow counter is indicating regular program flow. For this purpose, a reference counter is used, which upon call-up of the application function in the program step 36 is set to an initial value and is incremented each time the WD refresh is called up. Then the two counter readings are compared with each other. If the two counter readings do not match, there is an irregular program flow. It is likewise conceivable that an additional time counter is measured here. If the counter reading of the program flow counter has not been changed within certain time limits, it can be concluded that there is a faulty program flow. If regular program flow is detected in interrogation 52, the resetting of the monitoring circuit 12 follows in program step 53. In this case, the flag 22 in the configuration register 20 is set for a certain time and subsequently reset again. The pulse thus produced is passed on via the AND gate 24 and the connection line 17 to the monitoring circuit 12. Subsequently, a renewed switching-over of the operating state of the microcomputer 10, namely from ROM mode back into RAM mode, then takes place in the program step 54. The subroutine for resetting the monitoring circuit 12 is ended with the return 55. If an irregular program flow was detected in interrogation 52, the program step 53 is omitted, so that no resetting of the monitoring circuit 12 takes place. After a short time, the monitoring circuit 12 will then completely reset the microcomputer 10, in order to bring about a reliable state.

The microcomputer 10 according to the invention offers not only advantages for the application of motor vehicle control devices. The reliable operation of the microcomputer is always ensured whenever the microcomputer is executing a program which is located in the code RAM 14 of the microcomputer 10. A further application example of this is the programming of the internal programmable, non-volatile memory 13. The code RAM 14 is also utilized for this. In the code RAM there is then stored the programming algorithm. The data to be programmed are transferred from a connected external programming device to the microcomputer 10. Should the obligation to leave RAM mode within certain cycles be disruptive, a stopping of the monitoring circuit 12 could be provided by additional hardware measures. For example, the monitoring circuit 12 could be stopped by means of the separate programming pin during the programming of the programmable, non-volatile memory 13 (EEPROM) in RAM mode.

It is not absolutely necessary for the invention that the individual components of the microcomputer are integrated on one chip. They may also be accommodated on separate chips.

It is also not absolutely necessary for the invention that a switching-over of the operating states is explicitly provided in the microcomputer 10. The distinction between the operating states may also take place implicitly, for example by address decoding.

Furthermore, when an irregular program flow is detected according to the program step 52, alternatively a resetting of the microcomputer 10 could also be directly initiated.

Claims (1)

What is claimed is:
1. A microcomputer, comprising a central processing unit; a non-volatile memory and a volatile memory usable as a program memories, so that programs executable by said central processing unit are readable into said memories; input/output unit; a monitoring circuit effecting a resetting of the microcomputer when it does not receive any monitoring signal for a predetermined time, the microcomputer operating in at least two different operating states so as to execute a program in said volatile memory in a second operating state; and means for suppressing monitoring signals which are active if the microcomputer is operating in said second operating state; and means for switching the microcomputer from time to time from said second operating state to said first operating state in which outputting of the monitoring signals is not suppressed and then a monitoring signal is outputted.
US08397157 1993-09-25 1994-09-10 Microcomputer with the capability of suppressing signals which reset a watchdog-timer Expired - Fee Related US6243837B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE19934332769 DE4332769C1 (en) 1993-09-25 1993-09-25 Microcomputer
DE4332769 1993-09-25
PCT/DE1994/001043 WO1995008802A1 (en) 1993-09-25 1994-09-10 Microcomputer with monitoring circuit

Publications (1)

Publication Number Publication Date
US6243837B1 true US6243837B1 (en) 2001-06-05

Family

ID=6498682

Family Applications (1)

Application Number Title Priority Date Filing Date
US08397157 Expired - Fee Related US6243837B1 (en) 1993-09-25 1994-09-10 Microcomputer with the capability of suppressing signals which reset a watchdog-timer

Country Status (7)

Country Link
US (1) US6243837B1 (en)
EP (1) EP0671031B1 (en)
JP (1) JP4005124B2 (en)
CN (1) CN1037716C (en)
DE (1) DE4332769C1 (en)
RU (1) RU2129300C1 (en)
WO (1) WO1995008802A1 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6405328B1 (en) * 1996-07-09 2002-06-11 Nokia Telecommunications Oy Method for resetting processor, and watchdog
US6424581B1 (en) * 2000-08-14 2002-07-23 Matrix Semiconductor, Inc. Write-once memory array controller, system, and method
US6438432B1 (en) * 1996-08-24 2002-08-20 Robert Bosch Gmbh Process for the protection of stored program controls from overwriting
US6543012B1 (en) * 1999-04-19 2003-04-01 Motorola, Inc. Method of detecting incorrect sequences of code execution
US20040078731A1 (en) * 2000-10-06 2004-04-22 Alwin Becher Method for operating a processor-controlled system
US20040095116A1 (en) * 2002-11-14 2004-05-20 Fyre Storm, Inc. Power converter circuitry and method
US20040250178A1 (en) * 2003-05-23 2004-12-09 Munguia Peter R. Secure watchdog timer
US20050050360A1 (en) * 2003-06-12 2005-03-03 Fuji Xerox Co., Ltd. Controller, image processing apparatus, and method of controlling execution of program
US20080148107A1 (en) * 2006-12-19 2008-06-19 Fujitsu Ten Limited Electronic control device
US20080244302A1 (en) * 2007-03-30 2008-10-02 Dell Products, Lp System and method to enable an event timer in a multiple event timer operating environment
CN103294147A (en) * 2013-06-24 2013-09-11 天津七一二通信广播有限公司 Software startup and shutdown circuit and realizing method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3076239B2 (en) * 1996-01-17 2000-08-14 日本電気アイシーマイコンシステム株式会社 On-board write control method
DE102004060342B3 (en) 2004-12-15 2006-07-27 Siemens Ag Operating method for a rolling mill and corresponding thereto facilities
RU2461051C2 (en) * 2010-07-27 2012-09-10 Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" Method of detecting random "wanderings" in microcomputer

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2177241A (en) * 1985-07-05 1987-01-14 Motorola Inc Watchdog timer
US4956807A (en) * 1982-12-21 1990-09-11 Nissan Motor Company, Limited Watchdog timer
US5036493A (en) * 1990-03-15 1991-07-30 Digital Equipment Corporation System and method for reducing power usage by multiple memory modules
US5068783A (en) * 1985-10-24 1991-11-26 Oki Electric Industry Co., Ltd. Microcomputer having a built-in prom for storing an optional program
US5119381A (en) * 1987-02-05 1992-06-02 Honda Giken Kogyo Kabushiki Kaisha Program execution malfunction detecting method for an automobile controlling device
EP0551870A2 (en) * 1992-01-13 1993-07-21 Sony Corporation Electronic apparatus
JPH05274216A (en) * 1992-03-26 1993-10-22 Fuji Electric Co Ltd Image memory
US5408645A (en) * 1991-06-25 1995-04-18 Nissan Motor Co., Ltd. Circuit and method for detecting a failure in a microcomputer
US5521880A (en) * 1994-05-31 1996-05-28 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory having control circuitry for shared data bus

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956807A (en) * 1982-12-21 1990-09-11 Nissan Motor Company, Limited Watchdog timer
GB2177241A (en) * 1985-07-05 1987-01-14 Motorola Inc Watchdog timer
US5068783A (en) * 1985-10-24 1991-11-26 Oki Electric Industry Co., Ltd. Microcomputer having a built-in prom for storing an optional program
US5119381A (en) * 1987-02-05 1992-06-02 Honda Giken Kogyo Kabushiki Kaisha Program execution malfunction detecting method for an automobile controlling device
US5036493A (en) * 1990-03-15 1991-07-30 Digital Equipment Corporation System and method for reducing power usage by multiple memory modules
US5408645A (en) * 1991-06-25 1995-04-18 Nissan Motor Co., Ltd. Circuit and method for detecting a failure in a microcomputer
EP0551870A2 (en) * 1992-01-13 1993-07-21 Sony Corporation Electronic apparatus
JPH05274216A (en) * 1992-03-26 1993-10-22 Fuji Electric Co Ltd Image memory
US5521880A (en) * 1994-05-31 1996-05-28 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory having control circuitry for shared data bus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Motorola Semiconductor Technical Data, 1992, MC 68 F333, pp. 3-7, 28-30, 100-102 and 110.

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6405328B1 (en) * 1996-07-09 2002-06-11 Nokia Telecommunications Oy Method for resetting processor, and watchdog
US6438432B1 (en) * 1996-08-24 2002-08-20 Robert Bosch Gmbh Process for the protection of stored program controls from overwriting
US6543012B1 (en) * 1999-04-19 2003-04-01 Motorola, Inc. Method of detecting incorrect sequences of code execution
US6424581B1 (en) * 2000-08-14 2002-07-23 Matrix Semiconductor, Inc. Write-once memory array controller, system, and method
US20040078731A1 (en) * 2000-10-06 2004-04-22 Alwin Becher Method for operating a processor-controlled system
US7174483B2 (en) * 2000-10-06 2007-02-06 Conti Temic Microelectronic Gmbh Method for operating a processor-controlled system
US6946753B2 (en) * 2002-11-14 2005-09-20 Fyre Storm, Inc. Switching power converter controller with watchdog timer
US20040095116A1 (en) * 2002-11-14 2004-05-20 Fyre Storm, Inc. Power converter circuitry and method
US20040250178A1 (en) * 2003-05-23 2004-12-09 Munguia Peter R. Secure watchdog timer
US20050050360A1 (en) * 2003-06-12 2005-03-03 Fuji Xerox Co., Ltd. Controller, image processing apparatus, and method of controlling execution of program
US7457943B2 (en) * 2003-06-12 2008-11-25 Fuji Xerox Co., Ltd. Controller, image processing apparatus, and method of controlling execution of program
US20080148107A1 (en) * 2006-12-19 2008-06-19 Fujitsu Ten Limited Electronic control device
EP1953644A2 (en) * 2006-12-19 2008-08-06 Fujitsu Ten Limited Electronic control device
US8042009B2 (en) 2006-12-19 2011-10-18 Fujitsu Ten Limited Electronic control device
EP1953644A3 (en) * 2006-12-19 2009-04-22 Fujitsu Ten Limited Electronic control device
US20080244302A1 (en) * 2007-03-30 2008-10-02 Dell Products, Lp System and method to enable an event timer in a multiple event timer operating environment
US7783872B2 (en) 2007-03-30 2010-08-24 Dell Products, Lp System and method to enable an event timer in a multiple event timer operating environment
CN103294147A (en) * 2013-06-24 2013-09-11 天津七一二通信广播有限公司 Software startup and shutdown circuit and realizing method
CN103294147B (en) * 2013-06-24 2016-05-18 天津七一二通信广播有限公司 A software open, shut down circuit realization and

Also Published As

Publication number Publication date Type
WO1995008802A1 (en) 1995-03-30 application
DE4332769C1 (en) 1994-12-15 grant
EP0671031A1 (en) 1995-09-13 application
JP4005124B2 (en) 2007-11-07 grant
EP0671031B1 (en) 1998-01-21 grant
CN1114842A (en) 1996-01-10 application
CN1037716C (en) 1998-03-11 grant
JPH08503802A (en) 1996-04-23 application
RU2129300C1 (en) 1999-04-20 grant

Similar Documents

Publication Publication Date Title
US5765025A (en) Digital signal processor with on board program having arithmetic instructions and direct memory access instructions for controlling direct memory access thereof
US4796235A (en) Write protect mechanism for non-volatile memory
US5436837A (en) System for controlling a motor vehicle
US5283792A (en) Power up/power down controller and power fail detector for processor
US7050859B1 (en) Systems and methods to port controller state and context in an open operating system
US5274827A (en) Method for EEPROM write protection using threshold voltage projection
US4763296A (en) Watchdog timer
US6009370A (en) Control unit for vehicle and total control system therefor
US6202104B1 (en) Processor having a clock driven CPU with static design
US5862148A (en) Microcontroller with improved debug capability for internal memory
US5408672A (en) Microcomputer having ROM to store a program and RAM to store changes to the program
US5638272A (en) Control unit for vehicle and total control system therefor
US4802119A (en) Single chip microcomputer with patching and configuration controlled by on-board non-volatile memory
US5151986A (en) Microcomputer with on-board chip selects and programmable bus stretching
US5027317A (en) Method and circuit for limiting access to a RAM program memory
US5263168A (en) Circuitry for automatically entering and terminating an initialization mode in a data processing system in response to a control signal
US4924382A (en) Debugging microprocessor capable of switching between emulation and monitor without accessing stack area
US5454114A (en) Microcontroller power-up delay
US6981176B2 (en) Secured microcontroller architecture
US6272587B1 (en) Method and apparatus for transfer of data between cache and flash memory in an internal combustion engine control system
US5117498A (en) Processer with flexible return from subroutine
US5446864A (en) System and method for protecting contents of microcontroller memory by providing scrambled data in response to an unauthorized read access without alteration of the memory contents
US4542453A (en) Program patching in microcomputer
US4386427A (en) Fail-safe device in an electronic control system for an automotive vehicle
US6076161A (en) Microcontroller mode selection system and method upon reset

Legal Events

Date Code Title Description
REMI Maintenance fee reminder mailed
REIN Reinstatement after maintenance fee payment confirmed
FP Expired due to failure to pay maintenance fee

Effective date: 20050605

FPAY Fee payment

Year of fee payment: 4

SULP Surcharge for late payment
PRDP Patent reinstated due to the acceptance of a late maintenance fee

Effective date: 20051011

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Expired due to failure to pay maintenance fee

Effective date: 20130605