JPH05273955A - Device for displaying plural pictures - Google Patents

Abstract

PURPOSE:To overlap plural images to one picture and to synthesize them by controlling the display priority order of a part, where the plural images are displayed while being overlapped, by a display priority order control circuit. CONSTITUTION:First and second horizontal and vertical address translating RAM 8-11 are respectively provided with additional bits and respectively write data to control the ON/OFF of horizontal and vertical display. Further, these additional bits are horizontally/vertically ANDed, and a signal is generated to show the display periods of respective first and second image data. Corresponding to the period of overlapping data outputs from first and second image display memories 16 and 17, a display priority order control circuit 19 is operated to turn on only one display of signal having the highest display priority order and to turn off all the other display period signals. Thus, while the plural display signals are turned on at the same time, only one image is displayed, and the other image data are controlled to be turned off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display system,
In particular, the present invention relates to a multi-image display device that compositely displays a plurality of images on one screen.

[0002]

2. Description of the Related Art FIG. 4 shows a circuit block diagram of a conventional multiple image display device. In the conventional technique, horizontal and vertical display address counters 402 and 403, which receive the display clock from the display clock generator 401 at their inputs, generate horizontal and vertical display addresses, and address bus switches 404 and 405, respectively, at their address inputs. , 406 and 407, the first to nth horizontal and vertical display address conversion RAMs 408, to which the horizontal and vertical display addresses are input.
409, 410, 411 convert the horizontal and vertical display addresses according to internal data, and input the addresses,
The first and nth horizontal and vertical display addresses converted by the first to nth horizontal and vertical display address conversion RAMs 408, 409, 410, 411 are respectively connected through the data bus switches 412, 413, 414, 415. The image memories from the nth to the nth output image data according to the input horizontal and vertical display addresses, and the horizontal and vertical display address conversion RAMs 408, 40.
An image data output from the first to nth image memories is turned on by a signal indicating a display period generated by ANDing horizontal and vertical directions of data of additional bits provided in each of 9, 410 and 411. By controlling / OFF, a plurality of image data were combined and displayed on one screen.

[0003]

However, in the above-described conventional multi-image display device, the image data output from the first to nth image memories is changed to the first to nth horizontal and vertical display addresses, respectively. Since the opening and closing of the video switch connected to the data output of each image memory is controlled by the signal indicating the display period generated by logically ANDing the additional bits provided in the conversion RAM in the horizontal and vertical directions, When the display of image data is turned on at the same time, a plurality of image data outputs collide with each other and a normal image cannot be displayed. Therefore, there is a disadvantage that a plurality of images cannot be displayed in an overlapping manner.

Therefore, in view of the above-mentioned drawbacks, a technical object of the present invention is to provide a multiple image display apparatus capable of superposing and displaying a plurality of images in an overlapping manner.

[0005]

According to the present invention, a horizontal and vertical display address conversion RAM for converting horizontal and vertical display addresses according to predetermined internal data,
In a multi-image display device having an image memory that outputs a plurality of image data according to the converted horizontal and vertical display addresses, a priority order is defined in a portion where image displays related to the plurality of image data overlap. A multi-image display device is provided which has means for superimposing a plurality of images on another image based on the priority order and displaying the composite image.

According to the present invention, the horizontal and vertical display addresses are converted according to predetermined internal data,
The converted horizontal and vertical display addresses are generated, and additional bits are provided in the converted horizontal and vertical display addresses,
A horizontal and vertical display address conversion RAM for generating a signal indicating a display period, an image memory for outputting a plurality of image data according to the converted horizontal and vertical display addresses, and an image memory for receiving the output image data, ON / OF of image data output based on the signal indicating the display period
In a multi-image display device having a video switch for performing F, after rearranging the signals indicating the display period in accordance with a predetermined priority, one image data output having the highest priority is turned on, and the remaining Output image data O
A multi-image display device is obtained which has a display priority control means for controlling the video switch so as to perform FF.

According to the present invention, in the multi-image display device, when the display priority control means indicates display periods in which two or more signals indicating the display periods overlap each other, any one of the images is displayed. A multi-image display device is obtained, characterized in that the video switch is controlled to select the data output.

That is, according to the present invention, the horizontal and vertical address counters which receive the display clock at the input and output the horizontal and vertical display addresses, and the first to the first which are respectively connected to the horizontal address at the address input. n horizontal display address conversion RAMs up to n, first to nth vertical display address conversion RAMs connected to the vertical display addresses at address inputs, and the first to nth horizontal display at address inputs The first to nth image memories, to which the data buses of the address conversion RAM and the first to nth vertical display address conversion RAMs are respectively connected, and the first to nth image memories A data output is connected to each of the first to nth horizontal and vertical display address conversion RAM An image display device having at least first to nth video switches that are opened and closed by a signal indicating the first to nth image display periods generated by ANDing After rearranging the signals indicating the image display period up to n according to the display priority, one image data with the highest priority output from the first to nth image memories is passed through and the other is blocked. Thus, a multi-image display device is obtained which controls the opening and closing of the first to nth video switches.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit block diagram of an embodiment of the present invention. In this embodiment, a composite display of two images will be described. According to the display clock generated from the display clock generator 1, the horizontal and vertical display address counters 2 and 3 output horizontal and vertical display addresses, respectively. The horizontal and vertical display addresses are transferred to the first horizontal and vertical display address conversion RAMs 8 and 9 through the first horizontal and vertical display address bus switches 4 and 5 and the second horizontal and vertical display address bus switches 6 and 7. And to the address buses of the second horizontal and vertical display address conversion RAMs 10 and 11, respectively. The first and second horizontal and vertical display address conversion RAMs 8, 9, 10, and 11 convert the input horizontal and vertical display addresses according to their internal data, and output the respective outputs to the first horizontal and vertical data. The data is input to the address buses of the first and second image memories through the bus switching units 12 and 13 and the second horizontal and vertical data bus switching units 14 and 15. The first and second image memories 16 and 17 output image data.

Additional bits are provided in the first and second horizontal and vertical display address conversion RAMs 8, 9, 10, and 11, respectively, and data for controlling ON or OFF of horizontal and vertical display is written therein. Further, a logical product of the additional bits in the horizontal / vertical directions is calculated to generate a signal indicating the display period of each of the first and second image data. By controlling the video switch connected to the data output of the first and second image memories by the signal indicating the first and second display periods, the image data is displayed while the signal indicating the image display period is ON. Output. Further, the following control is performed for the period in which the data outputs of the first and second image memories overlap.

A signal indicating the display period of the first and second image data described above is input to the matrix switch 18,
After being sorted according to the display priority order, the data is input to the display priority order control circuit 19. Display priority control circuit 19
Operates so as to turn on only the display with the highest priority of display with respect to the inputted signals indicating a plurality of display periods, and turn off all other display period signals.
Therefore, only one image is displayed and the other image data is controlled to be OFF while a plurality of display signals are simultaneously turned on. The display period signals output from the display priority control circuit 19 are rearranged by the matrix switch 20 to control the opening and closing of the first and second video switches 21 and 22, respectively.

FIG. 2 shows an example of displaying a plurality of images. First
And second horizontal and vertical display address conversion RAM 20
When the first and second images 206 and 207 are displayed redundantly by the signals H1, H2, V1 and V2 indicating the display period generated from the data of the additional bits 1, 202, 203 and 204, the conventional technique is used. Then, in the image overlapping unit 205, the first
And the second image data collided, and normal display could not be performed. Therefore, the display priority control circuit controls the image duplication unit 2
In the period of 05, data in any of the image memories is selected and output.

FIG. 3 shows an example of image display when this display priority control is performed.

(1) is a case where the display of the first image is prioritized, and the first image is displayed in the portion where the images overlap in FIG.
Image is displayed. Further, (2) is a case where the second image display is prioritized, and the second image is displayed in the portion where the images overlap.

[0016]

As described above, according to the present invention, the signals indicating the respective display periods are generated from the additional bits provided in the horizontal and vertical display address conversion RAMs connected to the plurality of image memories. , A plurality of images are superimposed on one screen by controlling a plurality of image display periods and further controlling a display priority of a portion where a plurality of image displays overlap by a display priority control circuit. The effect is that it can be displayed.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing correspondence between additional bits of a horizontal and vertical display address conversion RAM and a display screen.

FIG. 3 is an example of image display when display priority control is performed.

FIG. 4 is a block diagram of a conventional embodiment.

[Explanation of symbols]

1,401 Display clock generator 2,402 Horizontal display address counter 3,403 Vertical display address counter 4,5,6,7,404,405,406,407
Address bus switcher 8, 10, 408, 410 Horizontal display address conversion R
AM 9, 11, 409, 411 Vertical display address conversion R
AM 12, 13, 14, 15, 412, 413, 414, 4
15 data bus switching device 16, 17, 416, 417 image memory 18, 20 matrix switch 19 display priority control circuit 21, 22, 418, 419 video switch 201 first horizontal display address conversion RAM 202 second horizontal display address Conversion RAM 203 1st vertical display address conversion RAM 204 2nd vertical display address conversion RAM 205 Image duplication part 206 1st image 207 2nd image 208 Display screen 301,304 1st image 302,305 2nd Image 303, 306 Display screen

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Claims (3)

[Claims] 1. A horizontal / vertical display address conversion RAM for converting horizontal / vertical display addresses according to predetermined internal data, and an image for outputting a plurality of image data according to the converted horizontal / vertical display addresses. In a multi-image display device having a memory, a priority order is defined in a portion where the image displays related to the plurality of image data overlap, and a plurality of images are superimposed on another image based on the priority order and combined display is performed. A multi-image display device having means for performing. 2. A horizontal and vertical display address is converted according to predetermined internal data to generate a converted horizontal and vertical display address, and an additional bit is provided in the converted horizontal and vertical display address to set a display period. A horizontal and vertical display address conversion RAM for generating a signal, an image memory for outputting a plurality of image data according to the converted horizontal and vertical display addresses, and a display period for receiving the output image data. In a multi-image display device having a video switch for turning on / off image data output based on the signal shown, the signals showing the display period are rearranged in accordance with a predetermined priority, Turn on the video switch to turn on one high image data output and turn off the remaining image data output. A multi-image display device having display priority control means for controlling. 3. The multi-image display device according to claim 2, wherein the display priority control means outputs any one of the image data when signals indicating two or more display periods overlap each other. A multi-image display device, characterized in that the video switch is controlled so as to select.