JPH0225895A - Display device - Google Patents

Abstract

PURPOSE:To execute a different superposition processing to a different area and to simplify a picture preparation by providing a superposition logic designation plane. CONSTITUTION:At the input side of a superposing circuit 4, a superposition logic designation plane 6 in a bit map system is provided, and superposition logic data 105 stored in it are inputted to the superposing circuit 4. Namely, the superposing circuit 4 reads image data 100 and 101 stored in image planes 1 and 2, simultaneously, reads the superposition logic data stored in the superposition logic plane 6 and superposes the picture element data 100 and 101 based on the superposition logic data 105. In such a way, the designation of the area of the superposition processing and the superposition logic designation can be executed, and the preparation of the picture can be simplified.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is applicable to process control, plant control systems, etc., and is used to monitor the control status of the system and display the control system. The present invention relates to a display device.

(Prior Art) As a conventional display device of this kind, a plurality of image data of a plurality of display screens are displayed on one display screen of a display device.
There is a type that combines FMm, as shown in Figures 7 and 8.
The figures are diagrams showing different examples of overlapping methods.

FIG. 7 shows the first method, in which the entire screen is superimposed using a logic specified from among predetermined superimposition logics. That is, the superposition circuit 4 reads out image data 100° 101 from the image plane 1 and the image plane 2 that store the image data, and also reads the superposition logic designation data 102 designated by the superposition logic designation circuit 3, Based on these, image data 100 and 101 can be superimposed. The superposition circuit 4 outputs the superimposed image data 103 to a display (not shown). Image planes 1 and 2 are
It is usually composed of a memory element and can store data for one display dot with the number of bits corresponding to the display color. Therefore, the image data 100 and 101 are data having the number of bits corresponding to the display color.

FIG. 8 shows the second method, in which, in addition to the configuration shown in FIG. 7, there is provided an overlay area designation plane capable of outputting overlay area designation data 104 stored therein to the overlay circuit 4. 5, which allows the overlapping area to be specified.

In other words, the overlay area designation plane 5 determines which part of the image planes 1 and 2 is subjected to the overlay processing based on the logic specified by the overlay designation circuit 3, and is usually composed of memory elements. , is expressed as two values: "1" when superimposition processing is performed, and "0" when no superposition processing is performed,
One bit is assigned to each displayed dot.

(Problems to be Solved by the Invention) In the method shown in FIG. 7 (first method), the overlay logic designation circuit 3 has a function to designate which part of the image planes 1 and 2 is to be overlayed. Because there is no superimposition processing, the overlapping process can only be performed on the entire image planes 1 and 2. Therefore, the process of overlapping only a part of the image planes 1 and 2, that is, specifying an area to perform partially different overlapping processing. I can't do it.

Further, the method shown in FIG. 8 (second method) is different from the first method in that it is possible to specify an area for overlapping, but it is not possible to perform overlapping processing on separate areas.

In this way, both the conventional first method and the second method cannot apply different overlay processing to different areas, which not only complicates screen creation and limits its use as a display device. , lacks practicality.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a display device that can perform different overlay processes on different areas, thereby simplifying screen creation.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention superimposes screen data stored in a plurality of bitmap image planes using a superimposition circuit to display a display device. In a display device that displays on one display screen, a bitmap type superimposition logic specification plane that can specify a display minimum tri order of superposition logic when superimposing screen data stored in the image plane is provided. Based on the image data of the image plane and the superposition logic specification data from the superposition logic specification plane, independent superposition logic specifications can be made simultaneously to multiple areas with one dot as the minimum unit. It is something.

(Function) Since the present invention provides a superposition logic specification plane,
Since the superimposition logic can be specified for each area of the superimposed screen, screen creation is simplified.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic configuration of an embodiment of the present invention, in which a bitmap type superposition logic designation plane 6 is provided on the input side of the superposition circuit 4, and superposition logic data 105 stored in this plane is provided. It is designed so that it can be input to the superposition circuit 4.

The superposition logic plane 6 has the functions of the superposition logic designation circuit 3 shown in FIGS. 7 and 8 and the function of the superposition area designation plane 5 shown in FIG. It consists of The image constituent dots 200 of the image plane 1 and the image constituent dots 201 of the image plane 2 are in a one-to-one relationship, respectively.
The superposition logic plane 6 stores information that determines what kind of superposition processing is to be performed on the image constituent dots 200 and the image constituent dots 201, that is, superposition logic data 105. There is. The superposition circuit 4 reads the image data 100° 101 stored in the image planes 1 and 2, reads the superposition logic data 105 stored in the superposition logic plane 6, and converts the superposition logic data 10
5, the image data 100 and 101 are superimposed, and the superposition circuit 4 outputs the superimposed image data 103 to a display (not shown).

FIG. 2 is a block diagram showing only the essential parts of an embodiment of the present invention, and here the case is the superposition of image data 100° 101 stored in two image planes 1 and 2. The present invention is not limited to this, and can be implemented in the same manner even if there are three or more image planes. Image planes 1 and 2 are both 4
It is made up of bit/pixel memory, and the overlapping logic plane 6 is made up of 2 bit/pixel memory. The overlapping logical plane 6, which is an important component of the present invention, is
Up to four types of superimposition logic can be specified by operation commands from a console (not shown), but in this embodiment, as shown in FIG. 5, three types are specified: image data 100 priority, image data 101 priority, and exclusive logic. It is now possible to specify overlapping. That is, as shown in FIG. 4, the status terminal go, 31(y) of the console
If the number i is set to 0 and 0, respectively, the image data 100 has priority, and the status terminal S. When the +S1 signal is set to 1 and 0, respectively, the image data 101 is prioritized, and furthermore, when the status terminals So and S are set to 0 and 1, respectively, exclusive logic is established.

A console (not shown) is connected to the drawing processor 7, and the drawing processor 7 is
Create image data 1. , this is written in the image plane 1 and the image plane 2, and the drawing processor 7 can also write the superimposition logic designation data in the superposition logic plane 6 by an operation command.

FIG. 3 shows the structure of write data in this case.

When the display controller 8 receives a display operation command from a console (not shown), it outputs a display command signal 130 and a status signal 131 from the bus and timing control circuit 14, and also outputs a display command signal 130 and a status signal 131 from the display address bus 1.
The display address signal is periodically output to the display address signal 29.

The bus and timing control circuit 14 receives a drawing command signal 128 from the drawing processor 7, a display command signal 30 from the display controller 8, and a status signal 131, respectively, and outputs a bus from the drawing processor 7 and the display controller 8. Synchronization signal 1 for synchronizing
22, and also outputs an address select signal 124, a data buffer control signal 23, a command signal 121, and a latch timing signal 125, respectively.

When the address select signal 124 from the bus and timing control circuit 14 is input, the address multiplexer 12 connects a drawing address bus 126 connected to the drawing processor 7 and a display address bus C connected to the display controller 8. 129.

The data buffer 13 includes the bus and timing control circuit 1
When the data buffer control signal 123 from 4 is input, that is, at the time of drawing, the memory data signal 110 of image plane 1, the memory data 111 of image plane 2,
The memory data signals 112 of the overlapping logic plane 6 are respectively input, and these are also input to the drawing processor 7 via the drawing data bus 127.

The image plane data latch circuit 9 is the image plane data latch circuit 9.
When the latch timing signal 125 from the bus and timing control circuit 14 is input, the memory data signal 1.10 from the bus and timing control circuit 14 is latched.

The image plane data latch circuit 10 latches the memory data signal 111 from the image plane 2 when the latch timing signal 125 from the bus and timing control circuit 14 is input.

The image plane data latch circuit 13 latches the memory data signal 1.12 from the overlapping logic plane 6 when the latch timing signal 125 from the bus and timing control circuit 14 is input.

The superposition circuit 4 is an inverter as shown in Figure 4! 1,1
2,13. I4.15, AND circuit A1. A2. A3.
A4. A5. A6. It is composed of A7゜A8, OR circuits 01.02, inputs image data 100, ]01, performs superposition using superposition logic specification data 102, and displays image data 103 after this superposition on a display (not shown). This is what is output to. In this case, as shown in FIG. 5, the signals of the status terminals So and S are set to 0.
By setting 0.1, 0.0, 1, image data 10
A 0 select signal 143, an image data 200 select signal 144, and an exclusive logic select signal 145 are obtained. Note that the image data 100 and 101 in FIG.
FIG. 4 shows a superposition circuit for one of the bit bus configurations. Image data select signals 143, 144 and exclusive logic select signal 145 in FIG. 4 are also commonly connected to other bit lines.

Next, the operation of the display device configured as described above will be explained. When a drawing operation is performed using a console (not shown), drawing command No. 13 128 is input from the drawing processor 7 to the bus and timing control circuit 14. An address select signal 124 is provided from the bus and timing control circuit 14 to the address multiplexer 12, the drawing address bus 126 is selected, and a command signal 121 is sent from the bus and timing control circuit 14 to the data buffer 13. entered,
Since the memory data signals 110, 111 and 112 stored in advance in the image plane 1.2 and the superposition logic plane 6 are input to the image planes 1 and 2 and the superimposition logic plane 6, respectively, via the drawing data bus 127, are input to the drawing processor 7, where each image plane 1, 2 and the overlapping logical plane 6 are
Image data for each image is formed, and this image data is written to image planes 1 and 2 and superimposed logical plane 6.

j5, when a display operation command is given to the display controller 8 by a console (not shown), a display command signal 130 and a status signal 131 are given to the bus and timing control circuit 14, and the address multiplexer 12 is sent from the bus and timing control circuit 14. Since the address select signal 124 is applied to the display address bus 129, the display address bus 129 is selected. As a result, the memory address signal is input to the image plane 1.2 and the superposition logic plane 1 node 6. Then, a command signal ]2] is input from the bus and timing control circuit 14 to the image plane 1/-2 and the overlapping logic plane 6, and the memory data stored in each plane 1/2. The signals 110°11.1, 1.12 are read out, and the latch timing signal 125 is given from the bus and timing control circuit 14 to the latch circuits 9 to 11, so that the memory data signals 110 to 112 are read out.
is latched, and the image data 100, 101 and superposition logic designation data output from the latch circuits 9, 10 and ]1 are output to the superposition circuit 4, where each data 100 to ]02 are superimposed, and this The superimposed image data 103 is output to a display (not shown).

FIG. 6 shows an example of a superimposed screen displayed by the display device of the embodiment described above. 100 is a fixed screen with no update data in image plane 1, and 200 is a variable screen with only update data in image plane 2.

300 is a superimposed screen of screens 100 and 200,
The superposition logic at this time is that image plane 1 has priority in the left half of image plane 1, and image plane 2 has priority in the right half. In this case, the image plane] and the overlapping logical plane 6 are the image plane 2 that only needs to be initialized and updated, which greatly simplifies drawing.

According to the embodiment described above, since the bitmap type superimposition logic plane 6 is provided, it becomes possible to specify the area for superposition processing and the superposition logic, which simplifies screen creation and makes it possible to use as a display device. It is versatile and practical.

[Effects of the Invention] According to the present invention described above, it is possible to provide a display device in which different overlapping processes can be applied to different areas, thereby simplifying screen creation.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of a display device according to the present invention, FIG. 2 is a block diagram showing an embodiment of a display device according to the present invention, and FIG. 3 is a diagram showing an image plane and a superimposed logical plane in FIG. Configuration diagram of written data, 4th
5 and 5 are diagrams and logic tables showing the details of the superposition circuit of the same embodiment, FIG. 6 is a diagram showing an example of display of the superposition screen according to the same embodiment, and FIGS. 7 and 8 are respectively conventional FIG. 2 is a diagram showing a schematic configuration of a different display device. 1.2... Image plane, 4... Superposition circuit,
6... Overlapping logical plane, 7... Drawing processor, 8... Display controller, 9.10... Data latch circuit for image plane, 11... Data latch circuit for overlapping logical plane, 12... Address multiplexer, 13... Data buffer, 14...
Bus and timing control circuits. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 1F7 Figure 18

Claims (1)

[Scope of Claims] A display device in which screen data stored in a plurality of bitmap image planes is superimposed by a superimposition circuit and displayed on one display screen of a display device, comprising: A bitmap-based overlay logic specification plane is provided that allows you to specify the overlay logic of the minimum display unit when superimposing the screen data that is displayed, and the image data of the image plane and the overlay logic specification plane are superimposed from the overlay logic specification plane. Based on the logical specification data,
A display device characterized in that it is possible to simultaneously specify independent superimposition logic for a plurality of areas whose minimum unit is one dot.