JP2907617B2 - Display control processing method for display target - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control processing method for a display object which controls a plurality of display objects to be displayed on a display screen, and more particularly to a display control method for a flexible display object. The present invention relates to a display control processing method for a display object to be displayed.

[0002]

2. Description of the Related Art In data processing devices, cursors, ruled lines,
A plurality of display objects such as a character plane and a graphic plane may be simultaneously displayed on a display screen.

Conventionally, when displaying such a plurality of display objects, the superposition order of the display objects is fixedly determined in advance, and the display objects are displayed in accordance with the display mode indicated by the superposition order. Processing was performed to display the target object.

[0004]

However, in such a conventional technique, there is a problem that it is not possible to meet a user's request for a display mode in which a superposition order different from the superposition order specified by the system is indicated. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is intended to realize a flexible display processing of a display object when displaying a plurality of display objects on a display screen. An object of the present invention is to provide a display control processing method for a display object.

[0006]

In order to achieve this object, the present invention provides a display object processing method for controlling a plurality of display objects displayed in color to be displayed on a display screen. A decoder circuit that decodes the superimposition order type of the designated display object and activates one of the superimposition order type display signals prepared for the number of superposition order types, in association with the superposition order type. A corresponding superimposition order type display signal output from the decoder circuit is input, and a signal of a display object to be allocated and an inverted signal of a signal of the display object having a higher superposition order than the signal are input. And an OR circuit for calculating the logical sum of the output values of the AND circuits. Among them, a superimposing circuit prepared for each of the RGB images for selecting and outputting the signal of the highest display object specified by the associated superimposition order type, and an RGB image for calculating and outputting the logical sum of the superimposing circuits And a selection circuit prepared in the above.

According to the present invention having the above-described structure, when the superimposition order type is designated, the decoder circuit activates the superposition order type display signal defined by the superposition order type, and in response thereto, the activation signal is activated. The superimposition circuit that inputs the superimposition order type display signal operates. Then, the AND circuit forming the activated superimposing circuit outputs the AND product establishment signal on the condition that the AND circuit higher than itself does not output the AND product signal according to the input form of the signal of the display object. It operates to output, thereby, the activated superimposing circuit selects the signal of the highest display object specified by the superimposition order type to be associated, from the signals of the existing display objects. Output. In response to this, the selection circuit outputs a signal of the display object output from the activated superimposing circuit. As described above, the present invention employs a configuration in which a simple hardware circuit is used to execute the superimposition processing of the display target object information defined by the specified superimposition order type among the plurality of prepared superposition order types. Therefore, only by implementing a simple hardware circuit, flexible display processing of the display target can be realized.

[0007]

[0008]

[0009]

[0010]

[0011]

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments. FIG. 1 shows an embodiment of the principle of the present invention.
In the figure, 1 is a processor, 2 is a CRT for displaying a plurality of display objects, 3 is a video memory for storing display object information such as character plane image data and graphic plane image data, and 4 is a video memory 3. The CRT controller 5 is a video controller that is configured according to the present invention and controls display control of a display object. The video controller 5 includes a cursor information management unit 50 that manages cursor information to be displayed, a ruled line information management unit 51 that manages ruled line information to be displayed,
A superimposition order type display circuit 52 for displaying superimposition order type information set by the processor 1 among the superposition order types of display objects prepared in a plurality of types, and a superimposition order type display circuit using all display object information as input. The superimposition processing of the display target object information is executed according to the superimposition order type displayed by 52, and CR
And a superimposing circuit 53 for outputting to T2. In the present invention configured as described above, for example, as shown in FIG. 2, a superposition order type (P1) of cursor>character>graphic> ruled line and a superposition order type (P2) of cursor>graphic>character> ruled line A superimposition order type (P3) of cursor> ruled line>character> graphic and a superposition order type (P4) of graphic>character> ruled line> cursor are prepared. On the other hand, the superimposing circuit 53
When the superimposition order type (P1) of cursor>character>graphic> ruled line is designated, the superimposition process of the display target object information is executed so that the superimposition order designated by this superimposition order type (P1) can be realized. When the superimposition order type (P2) of cursor>graphic>character> ruled line is designated, the superimposition process of the display target object information is executed so that the superimposition order designated by this superimposition order type (P2) can be realized. When the superimposition order type (P3) of cursor> ruled line>character> graphic is designated, the superimposition processing of the display target object information is executed so that the superimposition order specified by this superimposition order type (P3) can be realized. When the superimposition order type (P4) of graphic>character> ruled line> cursor is designated, this superimposition order type (P4 A configuration in which the overlap rank specified by the executing the process of superimposing the display object information can be realized. When configured in this way, the processor 1
Sets information on which of these superimposition order types to select in the superposition order type display circuit 52,
Performs superimposition processing of display object information in accordance with the superimposition order type information displayed by the superimposition order type display circuit 52 so that the superimposition order specified by the superimposition order type can be realized. Is output to CRT2.
As described above, in the present invention, the superimposition circuit 53 does not execute the superimposition processing of the fixed display target object information, but performs the display that defines the specified superimposition order type among the plurality of prepared superposition order types. Since the configuration for executing the superimposition processing of the object information is adopted, flexible display processing of the display object can be realized. The video memory 3 described with reference to FIG. 1 manages character plane image data and graphic plane image data to be displayed on the CRT 2, and sends these image data to the superimposing circuit 53. On the other hand, the cursor information management unit 50
Manages the cursor information to be displayed on the CRT 2 and sends this cursor information to the superimposing circuit 53. The ruled line information management unit 51 manages the ruled line information to be displayed on the CRT 2,
This ruled line information is sent to the superimposing circuit 53.

FIG. 3 (a) shows an explanatory diagram of reference numerals for character plane image data transmitted from the video memory 3, and FIG. 3 (b) shows the graphic plane image data transmitted from the video memory 3. FIG. Also, FIG.
FIG. 4B illustrates an explanatory diagram of reference numerals for cursor information transmitted by the cursor information management unit 50, and FIG.
An explanatory diagram of reference numerals for ruled line information sent from the ruled line information management unit 51 is shown.

Hereinafter, as shown in FIG. 3A, the character plane image is CHD, and the character color flags for displaying the color information of the image are CHR, CHG, C
HB, and as shown in FIG.
RED for plane image, GRD for graphic G plane image, B for graphic B plane image
It will be represented by LD. As shown in FIG. 4A, cursor data output from the cursor generator is represented by CUD, and cursor color flags for displaying color information of the cursor are represented by CUR, CUG, and CUB.
As shown in (1), ruled line data output from the ruled line generator is represented by LID, and ruled line color flags for displaying color information of the ruled line are represented by LIR, LIG, and LIB.

FIG. 5 shows an embodiment of the superposition order type display circuit 52 described in FIG. 1, and FIGS. 6 to 10 show an embodiment of the superposition circuit 53 described in FIG. Next, the present invention will be described in detail according to these examples.

The superimposition order type display circuit 52 of the embodiment shown in FIG. 5 is composed of a combination of flip-flop circuits, and is provided with 8-bit data (D
I0-DI7) in accordance with the latch timing signal, and the lower 2 bits of the latch data (DO0-DO7) of the register circuit 521 are decoded to superimpose which superimposition order type is set by the processor 1. A circuit comprising a decoder 522 to be displayed on the circuit 53 is disclosed.

Here, in the embodiment of this figure, assuming that the four types described in FIG. 2 are prepared as the superimposition order types, the processor 1 transmits the 8-bit data (DI0 to DI0).
7) The superposition order type P1 is set with the lower two bits value “00”, the superposition order type P2 is set with the lower two bits value “01”, and the superposition is set with the lower two bits value “10”. The order type P3 is set, and the value of the lower two bits is “1”.
It is assumed that the superimposition order type P4 is set with “1”.

The embodiment shown in FIG. 6 shows the entire circuit configuration relating to the R signal of the superimposing circuit 53.
The circuit portion indicated by 100 in the figure is a superimposition order type display circuit 5
2 operates when the superimposition order type P1 is displayed, and a circuit portion indicated by 200 operates when the superposition order type display circuit 52 displays the superposition order type P2, and a circuit indicated by 300. A portion operates when the superimposition order type display circuit 52 displays the superposition order type P3, and a circuit portion indicated by 400 operates when the superposition order type display circuit 52 displays the superposition order type P4. That is, the OR circuit 500 calculates the logical sum of the inverted output values of these four circuit portions 100, 200, 300, and 400, and outputs the result to the CRT 2.

Here, in the embodiment shown in FIG. 6, only the circuit portion handling the R signal is shown, but the G signal and the B signal
Signals having the same circuit configuration are prepared.
The circuit configuration shown in FIG. 7 is an embodiment of a circuit portion indicated by 100 in FIG. 6, the circuit configuration shown in FIG. 8 is an embodiment of a circuit portion indicated by 200 in FIG. 6, and the circuit configuration shown in FIG. Is an embodiment of a circuit portion indicated by 300 in FIG. 6, and a circuit configuration shown in FIG. 10 is an embodiment of a circuit portion indicated by 400 in FIG.

The embodiments shown in FIGS. 7 to 10 basically follow the same circuit configuration.
A second AND circuit 532, a second AND circuit 532, a third AND circuit 533, a fourth AND circuit 534,
These four AND circuits 531, 532, 533, 5
NOR for calculating and outputting a logical sum inverted value of the output value of No. 34
And a circuit 535.

Next, the superimposing circuit 5 shown in FIGS.
The operation process 3 will be described. The superposition order type display circuit 52 displays the superposition order type P1 “P1 = 1, P2 =
0, P3 = 0, P4 = 0 ", the circuit shown in FIG. 7 enters the operating state, and at the display screen position where the cursor exists, the cursor data output from the first-order AND circuit 531 is output to the NOR circuit 535. CRT output
2 at the display screen position where the cursor does not exist and the character exists, the second AND circuit 53
2 is output to the NOR circuit 535 and is displayed on the CRT 2. At the display screen position where neither a cursor nor a character exists and a graphic exists, the graphic plane output by the third-order AND circuit 533 is displayed. Image is NOR circuit 53
5 is displayed on the CRT 2, has no cursor, character, or graphic, and at a display screen position where a ruled line exists, the ruled line data output from the fourth-order AND circuit 534 is output to the NOR circuit 535. Thus, it is displayed on the CRT 2.

Then, the superimposition order type display circuit 52 displays the superposition order type P2 "P1 = 0, P2 = 1, P3 =
When "0, P4 = 0" is output, the circuit in FIG. 8 enters an operating state, and at the display screen position where the cursor is present, the cursor data output from the first-order AND circuit 531 is output to the NOR circuit 535. At the display screen position where the cursor is not present and the graphic is present, the graphic plane image output from the second-order AND circuit 532 is displayed on the NOR circuit 53.
5 is displayed on the CRT 2, has no cursor and no graphic, and at a display screen position where a character exists, the character plane image output from the third-order AND circuit 533 is output to the NOR circuit 535. At the display screen position where there is no cursor, graphic, or character, and there is a ruled line, the ruled line data output from the fourth-order AND circuit 534 is output to the NOR circuit 535 and displayed on the CRT2. Will be done.

Then, the superimposition order type display circuit 52 displays the superposition order type P3 "P0 = 0, P2 = 0, P3 =
When 1, P4 = 0 "is output, the circuit of FIG. 9 enters an operating state, and at the display screen position where the cursor is present, the cursor data output from the first-order AND circuit 531 is output to the NOR circuit 535. At the display screen position where the cursor is not present and the ruled line is present, the ruled line data output from the second-order AND circuit 532 is output to the NOR circuit 535, so that the CRT2 is displayed.
In the display screen position where the character is displayed without the cursor or the ruled line and the character exists, the character plane image output by the third-order AND circuit 533 is N.
The signal is output to the OR circuit 535 and displayed on the CRT 2. In the display screen position where the cursor, the ruled line, and the character do not exist and the graphic exists, the fourth place AN is displayed.
The graphic plane image output from the D circuit 534 is output to the NOR circuit 535 and displayed on the CRT 2.

Then, the superimposition order type display circuit 52 displays the superposition order type P4 "P1 = 0, P2 = 0, P3 =
When "0, P4 = 1" is output, the circuit of FIG. 10 enters an operating state, and at the display screen position where a graphic exists, the graphic plane image output from the first-order AND circuit 531 is output to the NOR circuit 535. Therefore, at the display screen position where no graphic is present and a character is present on the CRT 2, the character plane image output from the second-order AND circuit 532 is output to the NOR circuit 535 and displayed on the CRT 2. At the position on the display screen where no rule exists and no ruled line exists, the ruled line data output from the third-order AND circuit 533 is output to the NOR circuit 535 and displayed on the CRT 2, and no graphic, character and ruled line exist. At the display screen position where the cursor is So that the cursor data output of the fourth of AND circuit 534 is displayed on CRT2 by being output to the NOR circuit 535.

[0025]

As described above, according to the present invention,
When displaying a plurality of display objects on the display screen, instead of performing a fixed display object information superimposition process, a superimposition order type selected from a plurality of prepared superposition order types Since the configuration for executing the superimposition process of the display object information specified in the above is adopted, it is possible to realize a flexible display process of the display object.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the principle of the present invention.

FIG. 2 is an explanatory diagram of an example of a superimposition order type.

FIG. 3 is an explanatory diagram of reference numerals for image data.

FIG. 4 is an explanatory diagram of symbols for cursor information and ruled line information.

FIG. 5 is an embodiment of a superimposition order type display circuit.

FIG. 6 is an embodiment of a superposition circuit.

FIG. 7 is an embodiment of a superposition circuit.

FIG. 8 is an example of a superposition circuit.

FIG. 9 is an embodiment of a superposition circuit.

FIG. 10 is an embodiment of a superposition circuit.

[Explanation of symbols]

 1 Processor 2 CRT 3 Video Memory 4 CRT Controller 5 Video Controller 50 Cursor Information Management Unit 51 Ruled Line Information Management Unit 52 Superposition Order Type Display Circuit 53 Superposition Circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 5/00-5/40 G06F 3/14-3/153 G06T 3/00

Claims (1)

(57) [Claims] In a display control processing method of a display object for controlling a plurality of display objects displayed in color to be displayed on a display screen, a superimposition order type of a specified display object is decoded. A decoder circuit for activating any one of the superposition order type display signals prepared by the number of superposition order types; and a corresponding superposition order type display provided in association with the superposition order type and output from the decoder circuit. AND circuits provided for the number of display objects to which the signals are input and to which the signals of the display objects to be allocated and the inverted signals of the signals of the display objects having a higher superimposition order than the signals are input; And an OR circuit for calculating the logical sum of the output values of the AND circuit, so that among the signals of the existing display objects, the highest-order display pair specified by the associated superimposition order type A superimposing circuit prepared for each RGB image that selects and outputs a body signal; and a selecting circuit prepared for each RGB image that calculates and outputs a logical sum of the superimposing circuits. Display control processing method for the display target.