SU1658419A1 - Device for processing and displaying halftone color and graphic images - Google Patents

Abstract

The invention relates to applied television. The purpose of the invention is to simplify the device. The device for processing and displaying color halftone and graphic images includes a camera 1, a synchronous generator 2, a camera interface 3, an image memory control unit 4, an image memory block 5, a video control block 6, a DAC 7, a switching unit O, blocks 9 table conversions and control block 10. The presence of three blocks 9 of tabular conversions allows reducing the hardware costs of the device as a whole. 1 hp f-ly, 4 ill.

Description

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The invention relates to applied television using computer technology and can be used for processing and displaying Earth remote sensing data, in medical diagnostics, in automatic control systems, in designing, etc.

The purpose of the invention is to simplify the device.

Fig. 1 is a structural electrical circuit of a display device and a processing of color halftone and graphic images; Fig. 2 is a structural electrical circuit of the masking unit and logical operations; in FIG. 3, a structural electrical circuit of the table conversion unit; in FIG. 4, a structural electrical circuit of the control unit.

A device for displaying and processing color grayscale and graphic images (see Fig. 1) comprises a camera 1, a synchronous generator 2, a unit 3 for interfacing with a camera, an image storage control unit 4, first, second, etc. The n-th image memory blocks 5.1, 5.5, ..., 5.k, as a control unit 6, first, second, third digital-to-analog converters 7.1, 7.2, 7.3, switching unit 8, first, second and third blocks 9.1 , 9.2, 9.3 tabular transformations, control block 10. Block 8 of masking and logical operations (see FIG. 2) consists of the first, second, etc. The eighth bit switch 11.1, 11.7, each of which is a static memory element. Each block 9.1, 9.2, 9.3 tabular transformations (see fig.Z)

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contains an input address multiplexer 12, a static memory block 13 and a buffer output register 14 for data exchange between the computer and the static memory block 13. Such organization of tabular transformations reduces the number of tables compared to the known device and thus reduces hardware costs for displaying and processing video data. The control unit 10 (see FIG. 4) contains the address decoder 15, the exchange control block 16, the bidirectional bus data generator 17, the high-order block 18 for the addresses of blocks 9.1-9.3 of the table conversions and the connection of graphics. Synchronizer 2 generates the synchronization required for operation of the device units, generates a standard TV monitor synchronization signal (video monitor unit 6), camera 1 synchronization signals, the display address for the 5.1 - 5.k blocks of the image memory. The memory management unit 4 contains a shaper of control elements of the dynamic memory of the 5.1 - 5.k image memory blocks, an address multiplexer, a computer data exchange control unit and 5.1 - 5.k blocks of the image memory, and the display addresses come from the clock generator 2. Use in block 4 of the memory management of one generator, rather than one for each memory block of the prototype device, using the display address directly from the synchro-generator 2, rather than forming it on the address counters for Each storage unit of the prototype device allows reducing the hardware costs of the proposed device. Each block 5.1 - 5.k of the image memory contains the elements of dynamic memory and shift registers, address and data multiplexers. Information about the location of the image in these blocks is provided below in the description text. It should be noted that the use of one address multiplexer, rather than one for each memory block of the prototype device, also significantly reduces the hardware costs of the proposed device.

A device for displaying and processing color halftone and graphic images works as follows.

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Sources of information to be processed and displayed are either the camera 1, or an external digital data storage device from which data enters the device via a computer communication bus. In the case of the arrival of information from the camera 1, the analog television signal from the output of camera 1 is fed to the input of the interface 3 with the camera in which it is subjected to analog-to-digital conversion. The synchronization of the camera 1 and the block 3 of the interface with the camera is performed by a signal arriving at their inputs from the first output of the synchro-generator 2, and the connection of the block 3 of the interface with the camera to the communication bus with the computer is carried out by a command coming at its first input from the first output of memory management unit 4. In the case of receipt of information from an external storage device, the image signal to be processed and displayed is transmitted via the bus, which is connected with the computer to the memory control unit 4. At the same time, the necessary control signals are transmitted via the communication bus from the synchronous generator 2 to the memory control unit 4. In this case, from the memory management unit 4, the input data and addresses of the transmitted data are received, respectively, on the first pass (via the data bus) and the second input (via the address bus) of the image memory blocks 5.1-5.k. The contents of the blocks 5.1-5.k of the image memory are sequentially read by the addresses generated by the memory management unit 4. Each block 5. 1-5.k of the image memory stores data about the image represented as a numerical matrix, i.e. in the form of two square numerical matrices, the rows and columns of which correspond to the horizontal line and vertical of the image, and the numerical values contain the characteristics of each of the points into which the image is divided. The size of each matrix of 5.1 - 5.k image memories allows each of them to store 4 images of 256x256 (or one) size of image split elements. When displaying, sequential line-by-line interrogation of all matrixes of blocks 5.1 - 5.k of the image memory is made in tempo and in accordance with the scan of the television image, which ensures its continuous regeneration. The control signals necessary for operation of blocks 5.1 - 5.k of the memory are generated by the synchronous generator 4 and are transferred from its third output to the third input of blocks 5.1 - 5.k of the image memory. Image information is located in blocks 5.1 through 5.k of the image memory as follows. By organizing the four matrices, it is possible to store four independent digital images of 256K256 or. The outputs of the matrices are the corresponding outputs of the blocks 5.1 - 5.R of the image memory, to each of which the corresponding input of the block 8 of masking and logical operations is connected. At the same time, the address inputs of the 5.1 - 5.k memory of the image are interconnected and connected to the third output of the memory management unit 4, and the data inputs to the second output of the same device. From k-blocks 5.1 - 5.k, video images are received at the K-inputs of masking and logical operations unit 8 (see Fig. 2), where, in accordance with the content, which is entered into elements of the static subblocks 11.1 - 11.8 (see FIG. 2) on the computer bus circuit - switching control block 10 - the video controller's internal bus block 8 prohibits or allows passage of certain data bits from blocks 5.1 - 5.k of the image memory to the second inputs of blocks 9.1 - 9.3 table conversions. In addition, each of the subunits 11.1–11.3 (see FIG. 2) of the masking unit 8 and the logical operations performs the function of arbitrarily converting k-bits of information of the same weight (where weight is the sequence number of the bit in the information byte) arriving at its k- inputs and k-outputs of blocks 5.1 - 5.k of image memory, 4 bits of information at the rate of arrival of video information at the input of the device to display and process color grayscale and graphic images, all bits of the same weight from all blocks 5.1-5 .k image memories arrive at one of eight subunits 11.1–11.8 (see FIG. 2), allowing for each combination of k-input bits to specify a value, 4 output bits (P1, C1, B1 and Y1, etc. in FIG. 2) due to that each subunit 11.1 - 11.8 (see FIG. 2)

is a static random access element with 2x4 bit organization. Thus, this structure allows simple switching of k-input signals into any of the G, C, B, Y output signals, reproduction of any input signal to any combination of outputs, and arbitrary logical operations on the input signals, which allows displaying video data image memory in any arbitrary color or pseudo-colors and, moreover, this structure eliminates the need for masking blocks for each memory block, as is done in the prototype device, reducing hardware costs and as a result, power consumption. The output signals R, G., B in block 8 of masking and logical operations are the byte of information, and the output signal Y is an eight-bit code, the lower 4 bits of which contain graphical information red-green-blue-black and high-4 bits used to generate higher addresses of blocks 9.1-9.3 of table conversions. In the prototype device, there is no possibility of presenting graphic information against a halftone background by turning off the display at the required points (black and color of the graphic). The output Y of block 8 of masking and logical operations at the four lower bits carries graphic information of the following content: red YOO, green Y01, blue Y02, black Y03. And the next priority is set when displaying graphic and half-tone information. In the case of their simultaneous resolution by the video control unit 10, the half-tone information is displayed in accordance with a given tabular, function of the corresponding conversion table 9.1-9.3 if and only if all the YOO, Y01, Y02, Y03 bits are simultaneously zero, in all other cases graphic information. The output signals P, C or B are fed directly to the input of any of the tables 9.1 - 9.3 transformations. The input address multiplexer (see FIG. 5) 12 of each conversion table 9.1 to 9.3 connects video data to the address input of the static memory 13 of this table

for displaying or the address of the exchange with the internal bus of the video controller from the unit, 10 control of the video controller during data exchange with the computer via the bus. Video data is stored in the address multiplexer 12 register synchronously with the video data arrival frequency, the static memory 13 stores the table conversion function of the incoming ten-digit input data into the eight-digit code of the red, green or blue (respectively, R, G, B) image characteristics. each point of the video. At the output of the static memory 13, data is generated with a time delay determined by the speed of the static memory. In this case, data exchange between the computer and static memory 13 is performed via the buffer output register 14 via the internal bus of the video controller. Thus, the presence of three tables 9.1–9.3 of a converter with independent inputs allows to reduce the hardware costs of the device as a whole, but it allows to obtain displays of video information in natural colors. Analog signals for display on video monitor unit 6 are generated in blocks 7.1 through 7.3 digital-to-analog converters synchronously with the rate of arrival of video data, and their second inputs receive data with output of the corresponding blocks 9.1 through 9.3 of table transformations for red, green, and blue also synchronously with the rate of arrival of video data. The generation of analog signals of graphic video information is provided by control signals supplied to the third inputs of digital-to-analog converters 7.1 - 7.3 from the second input of the video control unit 10. The light separated analog signals are fed to the corresponding inputs of the video monitoring unit 6 and can be used to obtain the encoded signal in the SECAM or PAL standard. The synchronization signals of digital to analogue converters 7.1–7.3 are received at their first inputs from the fourth output of synchronous generator 2, and the synchronization signals of video control unit 6 are received at its first input from the second output of synchronous generator 2. Control of operation of block 8 of masking and logical operations, blocks 9.1–9.3 tabular transform

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Nin and digital-to-analog converters 7.1 to 7.3 are carried out over a bidirectional internal bus of a video controller by a video controller control unit 10 that performs the following functions: data exchange between the computer masking unit 8 and logical computer operations, data exchange between the computer and blocks 9.1-9.3 of table conversions , the formation of higher addresses of blocks 9.1 to 9.3 of table transformations, in this case there are two options for the formation of addresses: the first is that the highest addresses have fixed values determined by data from the register of blinds 18 generation of higher addresses of blocks 9.1 to 9.3 of table conversions and connection of graphics, the second is the dynamic generation of high addresses from four bits (Y04 to Y07) of the byte stream of the output signal Y of the masking unit and logical operations according to the following law: P08-Y04, C08-Y05 , B08-Y06, PCB09 - Y07 (common), where the letter index corresponds to the conversion table for red, green or blue colors, and the digital index is the number of the address input, the definition of the display mode, namely the prohibition or permission to pass to the video monitor Solo block 6 of graphic or half-tone video information. In this case, the address decoder 15 (see FIG. 4) is a block in which addresses that are allocated in the address space of a computer are decoded for exchanging data with high-address registers and display modes of block 18 with block 8 of masking and logical operations and blocks 9.1 - 9.3 tabular transformations, and the exchange unit 16 generates read or write signals. Bidirectional bus Converter 17 is designed to exchange data. Formation block 18 is the high-order address bits for blocks 9.1 to 9.3 of table conversions and control signals for digital-to-analog converters 7.1 to 773.

Claims (2)

1. A device for processing and displaying color halftone and graphic. sixteen images of cnc, camera, camera interface, memory control unit connected via computer communication bus, the first output of which is connected to the first camera input unit of the camera interface, first, second and third digital-to-analog converters, outputs which are connected respectively to the first, second, and third inputs of the video monitoring unit, and the first inputs, through a data link, to the memory management unit, n-blocks of the image memory, the first inputs of which are connected via the input data to the second output the house of the memory control unit, the second inputs - with the first output of the synchronous generator, the first, second and third blocks of tabular transformations, the outputs of which are connected to the first inputs of digital-to-analog converters, the control inputs of which are connected to the second output of the synchronous generator and the first inputs of the first, second and second of the third block of tabular transformations, which is different from the fact that, in order to simplify the device, a switching unit and a control unit are introduced into it, and n inputs of the switching unit are connected to the corresponding by the outputs of the p-blocks of the image memory, (n + 1) outputs of the memory control unit, including the inputs of the first, second and third blocks of tabular transformations are connected respectively to the first, second and third outputs of the switching unit, the control unit not through the pin of communication with the computer, its first input is connected to the third output of the clock generator, the second input is via a bi-directional bus to the (n-H) th input of the switching unit and the third inputs of the first, second and third blocks of tabular transformations, the third input is the block control unit is connected to the fourth output of the switching unit, the first output - via the senior address control bus - to the third inputs of the first, second and third blocks of tabular transformations, and the second output - to the third inputs of the first, second and third digital-analog conversions Atelier. 2. The device according to claim 1, wherein the control unit comprises an address decoder, an exchange control unit, a bi-directional bus data converter, the first inputs of which are connected via buses to a computer, an output signal bus of the exchange control unit connected to a second group of inputs of the bi-directional data type and, together with the output signals of the exchange control unit, forms the output signal bus of the control unit, the unit for generating the upper addresses of the table transformations, the first input of which is the input m of signals Y, and its second input is connected by a bi-directional bus to the output of the exchange control unit, the second, third outputs of the address conversion table generation unit are the second and third outputs of the control unit. g TV t f  J K0 - & / S Q-BUS about ttttttltUlitttU1 ds5sjeaddssS5ЈgЈ3; l5i8 p g 113 lit 11 5 ft / 2.7 about "With" h § & to l EDE1 I P 7 P8 Internal bus video controller Internal Buato controller bus. Fig.Z