JP3335198B2 - Image display circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display circuit for displaying characters, graphics, etc. on a screen of a television or the like using a so-called on-screen display IC (OSDIC). , Or circuits to enhance.

[0002]

2. Description of the Related Art An OSDIC is a television (TV),
An IC that can display characters, graphics, etc. on a TV screen by using it for video discs,
Normally, upon receiving a dot clock, which is a basic clock for displaying dots which are components of a character on a screen, a horizontal synchronization signal and a vertical synchronization signal, a monochrome dot signal constituting a character of a predetermined size is output. . In addition, there is a display that can display about eight colors. However, the background color is changed for each line.

As an example of the OSDIC, a CMOS L for an on-screen character display of 12 rows and 24 columns is used.
ΜPD6453, which is SI, is known.

[0004]

According to the OSDIC, a circuit for displaying characters or figures on a screen of a TV or the like can be provided at low cost.

[0005] However, OSDIC is either single color or 8 color.
When only a color display of about the same color can be performed and more colors are to be displayed, a more expensive screen display control LSI (for example, HD63484, μPD72120) is used instead of the OSDIC.
RAM for image and R for character
OM had to be used.

In addition, the OSDIC has a problem that a color can be specified only in units of one line for a background portion other than a character or graphic portion.

An object of the present invention is to provide an image display circuit capable of having advanced color functions by adding or enhancing color functions to OSDIC, without using expensive circuits using a screen control LSI. It is in.

[0008]

In order to achieve the above object, an image display circuit according to the present invention receives a clock signal, a horizontal synchronizing signal and a vertical synchronizing signal, and forms an image in synchronization with these signals. In an image display circuit using an on-screen display IC that outputs dot data, a first counter that counts a dot clock that is a basic clock for displaying dots and is reset by a horizontal synchronization signal, A second counter that counts and is reset by a vertical synchronizing signal, a RAM that uses the outputs of the first and second counters as an address signal, and stores a plurality of bits of color data at a memory address corresponding to the address signal; , Combining the output of the RAM with the dot data output from the on-screen display IC. It is obtained by a synthesizing circuit for outputting a large output dot data of bits than Todeta.

In this image display circuit, preferably,
A microcomputer that outputs color data to be written to the RAM and a write address of the color data; and a selector that switches between the write address and the output of the quantity counter according to a control signal from the microcomputer. Further prepare.

[0010]

The on-screen display IC receives a clock signal, a horizontal synchronizing signal and a vertical synchronizing signal, and outputs dot data forming an image in synchronization with these signals. This dot data is usually 1-bit monochrome dot data, but may be about 3 bits of color bits.

The first counter counts a dot clock which is a basic clock for displaying dots,
Reset by horizontal sync signal. The output of the first counter indicates the horizontal dot position of the dot currently being output by the OSDIC. In the case where the color is specified for each character and the number of horizontal dots constituting the character is 2 n times, the upper bits of the first counter excluding the lower n bits are used. The required RAM capacity can be reduced.

[0012] The second counter counts the horizontal synchronizing signal and is reset by the vertical synchronizing signal. The output of the second counter indicates the vertical position (line position) of the dot currently output by the OSDIC. In the case where the color is specified for each character and the number of vertical dots forming the character is 2 n times, the upper bits of the second counter excluding the lower n bits are used. Necessary RA
The capacity of M can be reduced.

The RAM uses the outputs of the first and second counters as an address signal, and stores a plurality of bits of color data at a memory address corresponding to the address signal. Therefore, in this RAM, the color at that position is arbitrarily set (within the range of the number of colors represented by the number of bits) regardless of the OSDIC according to the position of the dot or character on the screen.
Can be specified.

The combining circuit combines the output of the RAM with the dot data output from the on-screen display IC, and outputs output dot data having a larger number of bits than the dot data. That is, the number of colors that can be displayed can be increased.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows a schematic configuration of an image display circuit according to this embodiment. This circuit comprises an OSDIC 1, a horizontal position counter 2, a vertical position counter 3, a RAM (random access memory: readable and writable memory) 4, and a synthesizing circuit 10. The synthesis circuit 10 includes three AND gates.

The OSDIC 1 normally has a dot clock (DOTCLOCK) and a horizontal synchronizing signal (H.SY).
NC) and the vertical synchronization signal (V.SYNC),
A monochrome dot signal Vo is output. OS of this embodiment
As shown in FIG. 2, the DIC 1 displays eight characters by eight dots per character and displays eight characters in one screen in the horizontal direction and six lines in the vertical direction.

As shown in FIG. 3, the horizontal position counter 2
Consists of a 6-bit counter, counts the dot clock, and is reset by the horizontal synchronization signal. That is,
The horizontal position counter 2 indicates the horizontal position of the dot currently output (displayed) by the OSDIC 1. Similarly, the vertical position counter 3 comprises a 6-bit counter, counts horizontal synchronization signal pulses, and is reset by the vertical synchronization signal. That is, the vertical position counter 3
SDIC Indicates the vertical position of the currently output dot. The upper 3 bits output (Q3 to Q5) of each of the horizontal position counter 2 and the vertical position counter 3 are connected to address terminals (A0 to A5) of the RAM 4, respectively. The output Q3 of the horizontal position counter 2 is inverted every time eight dot clocks are input, and the output Q3 of the vertical position counter 3 is similarly inverted every time eight horizontal synchronization signal pulses are input. Here, each “eight” corresponds to the number of dots constituting one character in FIG. 2 in the horizontal and vertical directions. As a result, the position of the character currently displayed on the screen is given to the RAM 4.

As shown in FIG. 3, the RAM 4 has 6-bit address input terminals (A0 to A5) and 4-bit data terminals (D0 to D3). As shown in FIG.
The storage area of the RAM 4 stores 6 bits corresponding to a 6-bit address.
Bits D0 to D48 of the 48 memory addresses among the 4 memory addresses
D2 is used. This “48” corresponds to the total number of characters on the screen of FIG. By storing a desired bit value at each memory address of the RAM 4, an arbitrary color can be given to the character at that character position, as described below.

The D0 bit of the RAM 4 is associated with red (R), the D1 bit is associated with green (G), and the D2 bit is associated with blue (B). As can be seen from FIG.
Is output in synchronization with the output of the OSDIC,
Instead of the output bit "1" of a character at a specific position output from the OSDIC 1, color data "D0D1D2" specified in the RAM 4 for the character can be output. For example, by setting specific color data “D0D1D2” in the memory address 8 of the RAM 4, the color can be given to the character of the number 8 on the screen.

In this embodiment, the color is added in units of characters. However, if all the output bits of the counters 2 and 3 are used and the RAM 4 has a 12-bit address, the color is added in units of dots. It is also possible to

Next, FIG. 5 shows that one character is composed of 16 dots vertically and 12 dots horizontally and the screen is composed of 19 characters in the horizontal direction (22 characters).
8 shows the configuration of the second embodiment of the present invention in the case of 11 rows (176 lines) in the vertical direction.

The microcomputer 8 and the OSDIC 1 are conventional circuit components. This OSDIC 1 has a microcomputer 8
And outputs the dot clock 11 in response to the clock from the controller. This dot clock 11 is shown in FIG.
Is input to the horizontal position counter 2. The horizontal position counter 2 counts the dot clock 11,
Reset by horizontal sync signal. As a result, the count output corresponds to the horizontal position on the screen. Similarly, the vertical position counter 3 counts the horizontal synchronization signal and is reset by the vertical synchronization signal. Thereby, the count output corresponds to the vertical position on the screen. In this example, an 8-bit counter is used for both the horizontal counter and the vertical counter according to the character configuration and the screen configuration. As in the case of FIG. 1,
In order to add a color in character units, in the vertical direction, the lower 4 bits of the output of the counter 4 are not used, but the remaining upper 4 bits (represented by V0 to V4) are used.

In the horizontal direction, since the number of dots (12 dots) is not a multiple of 2 to the nth power, it cannot be dealt with by not using specific lower bits. Therefore, these 12 dots (a,
b, c,... l) are divided into three by four dots, and a memory address of the RAM 4 is assigned to each four-dot unit.
This is equivalent to a case where the character configuration is made four dots horizontally. To specify a color in character units, it is necessary to set the same color data at three addresses for the same character in the RAM 4. In this configuration, the lower 2 bits of the counter 2 are not used, and the remaining upper 6 bits (represented as H0 to H5) may be used. 3 × 209 = 67 in RAM4
Two memory addresses are required. This is 10 in RAM4
This means that a bit address input is required.

Further, in order to give the address at the time of writing data to the RAM 4 from the microcomputer 8, the addresses given to the RAM 4 are supplied to the microcomputer 8 by the line selectors 5, 6 and 7.
And the addresses from the horizontal position counter 2 and the vertical position counter 3 can be switched and selected. At the time of data writing, the line selectors 5 to 7 are switched to the microcomputer 8 side by the selector control signal 12 from the microcomputer 8 and the three-state buffer 9 is switched from the high impedance state to the conductive state. Connect to data line.
Thereafter, desired data is written to a memory address in the RAM 4 corresponding to an arbitrary character. This data writing is performed by inputting a vertical synchronizing signal to the microcomputer 8 to detect a vertical blanking period, and within this period. This is to prevent the screen from being disturbed by rewriting data during the screen display period.

The data in the RAM 4 has a 4-bit structure at address 1. However, as will be described later, the number of bits can be increased to increase the number of colors that can be displayed.

The combining circuit 10 shown in FIG. 5 includes three AND gates 81, 82 and 83 as shown in FIG. R
AM4 has an R value for the D0 bit, a G value for the D1 bit, D
The B value is stored in two bits, and the monochrome output Vo from the OSDIC 1 and the AND output of the D0 bit are output as an R signal,
The AND output of Vo and D1 bit is a G signal, Vo and D2
An AND output with a bit is defined as a B signal. As a result, 8
Color display of colors is realized.

FIG. 9 shows a case where 8-bit data is used as the RAM 4. D0 and D1 are 2-bit R data.
2, a case where 2-bit G data is stored in D3 and 2-bit B data is stored in D4 and D5. In the synthesis circuit 10,
D / A conversion circuits 91 to 93 convert the 2-bit data of each color into D
A / A converted signal is output to AND circuits 94 to 9 together with Vo.
6 to turn on / off the signal output of each color.
Control is performed according to whether Vo is 1 or 0. In this case, the AND circuits 94 to 96 can obtain analog level outputs. Of course, the display must be compatible with analog level inputs. This allows
It is possible to display 2 6 ( 64 ) colors.

FIG. 10 shows the output VR,
1 shows a synthesizing circuit 10 for adding a luminance signal (I) to VG and VB to change from 8 colors to 16 colors. In this OSDIC, the background color can be specified only in units of one line. Therefore, background color data (BR, BG, BB) is stored in the RAM 4 as D0, D1, and D2. Also,
The luminance signal I is stored as D3. The synthesis circuit 10
An inverter 101 for inverting R, VG, and VB,
102, 103 and inverters 101 , 102, 103
AND gate 111 for ANDing the output of
AND gates 104, 105, and 106 for ANDing D0, D1, and D2 with the output of the gate 111, and the outputs of the AND gates 104, 105, 106, and VR, VG, and VB
OR gates 108, 109, 110 that take the OR of
It is composed of an AND gate that ANDs D3 and Vo. V
R, VG, and VB are “0” (Lo) in a section other than the character display.
w), the background color can be set to the designated color by adding the data D0 to D2 only in this section. The number of character colors is doubled by the luminance signal I. Of course, the display must have an input for the luminance signal I.

[0030]

According to the present invention, an OSD having a single-color display function is provided.
Multicolor display can be performed using the IC, and a circuit which is less expensive than an image circuit using a screen display control LSI, a display RAM, and a character ROM can be provided. Further, even an OSDIC capable of displaying about eight colors can further increase the number of colors without using a screen display control LSI. Also, the color of the background portion of the character can be changed in units smaller than one line.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an image display circuit of the present invention.

FIG. 2 is an explanatory diagram showing a character configuration and a screen configuration in the image display circuit of FIG. 1;

FIG. 3 is an explanatory diagram of a connection relationship between a counter and a RAM in FIG. 1;

FIG. 4 is an explanatory diagram of a configuration of a RAM in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

6 is an explanatory diagram of a character configuration and a screen configuration in the image display circuit of FIG. 5;

FIG. 7 is an explanatory diagram of a configuration of a RAM in the image display circuit of FIG. 5;

8 is a circuit diagram showing an example of a configuration of a synthesizing circuit 10 in the image display circuit of FIG.

9 is a circuit diagram showing another example of the configuration of the synthesizing circuit 10 in the image display circuit of FIG.

FIG. 10 is a circuit diagram showing an example of a configuration of a synthesizing circuit 10 in a modification of the image display circuit of FIG. 5;

[Explanation of symbols]

1. On-screen display IC (OSDIC),
2 ... horizontal position counter, 3 ... vertical position counter, 4 ... R
AM, 5-7 line selector, 8 microcomputer, 9 three-state buffer, 10 synthesis circuit, 11 dot clock, 12 selector control signal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 5/00-5/42 H04N 5/262-5/278 H04N 5/38-5/455 H04N 5 / 66-5/68

Claims (2)

(57) [Claims] An image display circuit using an on-screen display IC for receiving a clock signal, a horizontal synchronizing signal, and a vertical synchronizing signal, and outputting dot data forming an image in synchronization with these signals. A first counter that counts a dot clock, which is a basic clock for resetting, and is reset by a horizontal synchronization signal; a second counter that counts a horizontal synchronization signal and is reset by a vertical synchronization signal; A RAM storing an output of the second counter as an address signal and storing a plurality of bits of color data at a memory address corresponding to the address signal; and outputting the output of the RAM to the on-screen display IC.
And a combining circuit for combining the dot data output from the device and outputting output dot data having a larger number of bits than the dot data. In the case where the on-screen display IC outputs 1-bit monochrome dot data Vo, RAM has 6-bit color data R1, R2, G1, G2, B
1, B2 is stored, and the synthesizing circuit outputs a signal obtained by D / A converting 2 bits of each color of the color data.
Is determined according to 1, 0 of the monochrome dot data Vo.
An image display circuit characterized in that the image display circuit controls the image display. 2. An image display circuit using an on-screen display IC for receiving a clock signal, a horizontal synchronizing signal, and a vertical synchronizing signal and outputting dot data constituting an image in synchronization with these signals. A first counter that counts a dot clock, which is a basic clock for resetting, and is reset by a horizontal synchronization signal; a second counter that counts a horizontal synchronization signal and is reset by a vertical synchronization signal; A RAM storing an output of the second counter as an address signal and storing a plurality of bits of color data at a memory address corresponding to the address signal; and outputting the output of the RAM to the on-screen display IC.
And a combining circuit for combining the dot data outputted from the printer and outputting output dot data having a larger number of bits than the dot data, wherein the on-screen display IC includes three-bit color data VR, VG, VB and monochrome dots. When outputting the data Vo, the RAM stores 3-bit background color data BR, BG, BB and 1-bit luminance signal bit I, and the synthesizing circuit stores the color data VR, VG, VB. When all are "0", the background color data is added to the color data in bit units, an AND output of the monochrome dot data Vo and the luminance signal bit I is set as an output luminance signal bit, and the output luminance signal bit is An image characterized in that the color data VR, VG, VB are 4-bit output dot data. Display circuit.