JPH05268638A - Video signal processing device - Google Patents

Abstract

PURPOSE:To improve the device with respect to not only dot disturbance and cross color but also graphic distortion, vertical jitter, or the like accompanying the conversion of the number of lines or fields. CONSTITUTION:A luminance signal Y extracted from a video signal GV by a filter 102 is supplied to a comb line filter consisting of an adder 106, a delay circuit 108, etc. The comb line filter removes carrier chrominance signal components left unremoved by the filter 102 and averages signals of adjacent lines as a vertical filter. Cross color components are removed from color difference signals U and V outputted from a color demodulating circuit 116 by filters 117 and 123 and the result is supplied to a vertical filter consisting of adders 119 and 125, delay circuits 120 and 126, etc. The vertical filter removes cross color components left unremoved by filters 117 and 123 and averages signals of adjacent lines. The device is improved with respect to dot disturbance and cross color by removal of unnecessary signals and is improved with respect to graphic distortion, vertical jitter, or the like by averaging signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus suitable for being arranged in front of a television system conversion apparatus.

[0002]

2. Description of the Related Art Currently, the television (TV) system adopted in the world is mainly composed of the following three types because of the structure of a composite video signal.
It can be divided into methods. System name Scan line / number of frames Color subcarrier Modulation system NTSC 525/60 3.58 MHz Quadrature two-phase modulation PAL 625/50 4.43 MHz Quadrature two-phase modulation However, V axis phase inversion for each scan line SECAM Same as above 4.25 MHz 4.206 MHz FM Modulation Furthermore, the NTSC and PAL each have a combination of scanning line / frame number and color modulation method, and are as follows. Method name Scan line / number of frames Color subcarrier V-axis phase inversion for each scan line 4.43NTSC 525/60 4.43MHz None M-PAL 525/60 3.58MHz Yes N-PAL 625/50 3.58MHz Yes , NTSC, M-PAL, N-PAL 3.58
Each MHz is slightly different.

From these, the requirements necessary for mutual conversion between television systems are summarized in the following two. (1) Conversion of scanning line / number of frames (line / field) 525
/ 60,625 / 50 (2) Conversion of color modulation system Carrier frequency (fsc) Quadrature two-phase modulation, FM modulation Presence / absence of V-axis phase inversion (2) is suitable for each system as demodulator and modulator of color signal It can be easily done by using the one. However, (1) generally requires an image memory because there is a time lag between the signals before and after conversion.

There is also a system in which the application is limited to viewing on a television receiver and only the conversion processing of (2) is used for system conversion.

It is expected that the vertical synchronizing circuit of the 625/50 system TV has a large allowable amount and can sufficiently cope with the TV signal of the 525/60 system, but some readjustment of the vertical synchronization is necessary. Therefore, it is unavoidable that the figure is flattened by being flattened up and down.

[0006] As mentioned above, only TV viewing is possible.
Although viewing with a 525/60 system TV signal is possible, it is impossible to record / reproduce it on a 625/50 system VTR or the like because the VTR has a small allowance for the difference in vertical synchronization. However, in terms of cost, it can be realized at low cost because only the color signal is remodulated.

If the conversion of (1) is also performed, it is necessary to first convert the number of lines. 525/60 →
In case of 625/50 conversion, 100 per field
There is an increase in lines, and it is necessary to increase at a ratio of 1 line to 5 lines (illustrated in FIG. 26A). Conversely, 625/50 →
In the case of the 525/60 system conversion, the number of lines is reduced by 100 lines per field, and it is necessary to reduce the number of lines every 6 lines (shown in FIG. 9B). The increase / decrease in the number of lines
It can be realized simply by overlapping or thinning the same line.

From a strict calculation, the number of converted lines becomes ± 5 lines deficient or shortage due to simple duplication every 5 lines or thinning out every 6 lines, but this is to be absorbed in the vertical blanking period. ..

As is apparent from FIG. 26, the conversion of the number of lines requires an image memory for one line or more. In the figure, it seems that one line is enough, but in order to convert all one field, an image memory for one field or more is required as shown below.

FIG. 27 shows field number conversion.
Referring to the conversion part of the m + 4 → m + 4 ′ field in FIG. A, the last line of the m + 4 field moves to the m + 4 ′ field (arrow P1), which coincides with the timing of the last line of the m + 5 field. Therefore, m +
It is necessary to delay the last line of 4 fields by 1 field.

On the other hand, looking at the conversion portion of the n → n ′ field in FIG. 6B, the last line of the n field is n−
This coincides with the timing of the last line of the 1'field (arrow P2), and a delay of 1 field is required.
The same thing occurs in the conversion part of the n + 5 → n + 5 ″ field (arrow P3).

Strictly speaking, the above line coincidence is
Since it does not match perfectly with a slight line difference, it is completely 1.
A field delay amount is not necessary, but one field is used here for simplification.

A one-field delay is now usually implemented by digitizing the signal and using the digital memory as an image memory.

Horizontal resolution is 320 lines, luminance (Y) S / N
The memory capacity of one field required for system conversion of a standard TV signal of 46 dB for color and C / S of 36 dB or higher is as follows. However, in consideration of the conversion of (2) described above, the C system already has color difference signals RY = V, B.
Assuming demodulation to the state of -Y = U, two systems are required.

Here, the following setting values are considered for the sampling frequencies and gradations of the Y and C systems.

Y system Sampling frequency: 8 MHz Gradation: 8 bits C system Sampling frequency: 3 MHz Gradation: 6 bits Considering mutual conversion between 525/60 system and 625/50 system, 1 field is based on 625/50 system (In the case of FIG. 27B).

From the above, the memory capacity of one field is obtained by the following equation. {8 × 8 × 10 ⁶ + (6 × 3 × 10 ⁶ × 2)} ÷ 50 = 1.8 × 10 ⁶ = 1.8 Mbits If the resolution and gradation set above are required to be improved, The memory capacity will be larger.

Further, looking at the state of line number conversion in more detail, since the TV signal is interlaced in both the 525/60 system and the 625/50 system, a simple field as shown in FIG. 26 is used. The conversion of the number of lines per unit may impair the image quality in the vertical direction.

FIG. 28 shows in detail the position of each line when the images are displayed in the same image size when the system conversion from the 525/60 system to the 625/50 system is performed. The solid line is the line position of the odd field and the dotted line. Indicates the line position of the even field, and since they are interlaced, both
They are arranged alternately.

FIG. 6A shows a state of conversion when a field memory is used, and represents the same type of field (odd → odd or even → even). There are some parts such as the z ″ and a ″ lines where the vertical positional relationship is reversed, and there are also parts where the positions are shifted downward by almost one line like the a ′ to a ″ lines.

FIG. 9B shows a state of conversion when a field memory is used, and shows between different fields (odd → even or even → odd). Again,
Up and down reversals are made in the f'-e "to f" lines, and the positions are greatly shifted downward in the f'-f "lines.

Incidentally, as is apparent from FIG. 27, during conversion, one field overlap (n + 5 ″ in FIG. B) and thinning (m + 5 in FIG. A) occur, so conversion between same-type fields and conversion between different types of fields. The cyclical change with is inevitable.

In each field, a->c-> e are interlaced, but since they are continuously seen from a to k in the eyes, vertical line inversion as shown in FIGS. 28A and 28B and significant line position. The shift is recognized as vertical graphic distortion.

On the other hand, in FIG. 6C, since the conversion field is formed from two fields (one frame),
There is no reversal of the upper and lower lines, and the positional deviation is suppressed to a maximum of 0.5 lines, and the figure distortion in the vertical direction is greatly improved.

Since most of the conventional TV system converters are for broadcasting and business use and do not like image quality deterioration, they also have a large memory capacity per field and the above-mentioned FIG. 28C.
Since the number of lines is converted in each frame, a memory for one frame is required. Actually, in order to further improve the image quality, the one having a memory of several frames is mainstream.

Further, as is apparent from FIG. 27, the TV format converter must simultaneously perform writing (writing) and reading (reading) to this memory for the convenience of immediately converting and outputting an input signal. Moreover, since each data position sequentially changes with time, the above field memory (or frame memory) must have two asynchronous write / read ports. As a memory that meets this condition, a video memory (V-RAM) developed for such image processing is used, or a large number of general-purpose memories are driven by serial / parallel conversion to apparently perform asynchronous operation. I had no choice but to do it.

The advantages and disadvantages of each conversion are summarized as follows. (A) Line / field conversion + color modulation system conversion Merit: It becomes a complete TV system conversion that can be recorded on a VTR or the like.

Disadvantages: Asynchronous write / read is possible, and a large-capacity memory capable of guaranteeing image quality is required, which is expensive and complicated. (B) Conversion of color modulation method only Merit: It is simple and inexpensive because it only has a chroma remodulation circuit.

Disadvantages: Half of which depends on the circuit of the TV receiver, so recording on a VTR or the like is not possible. Also,
It is necessary to re-establish the vertical synchronization of the TV. Furthermore, the screen is flattened up and down.

There is a disadvantage that a large-capacity expensive dedicated video memory or a large amount of general-purpose memory is required to perform the conversion of (a) so that recording on a VTR is possible.

Therefore, the applicant of the present invention has previously proposed a television system conversion device for performing line / field conversion without using a large capacity memory (Japanese Patent Application No. 4-35009).
issue). 2 and 3 are block diagrams showing the configuration.

In the figure, the luminance signal Y is supplied to the input terminal 1Y. The luminance signal Y is supplied to the adder 3 via the resistor 2. The wobbling clock WOB output from the write timing generator 4 is supplied to the adder 3 via the resistor 5. Then, the luminance signal Y added with the wobbling clock WOB output from the adder 3 is supplied to the switch circuit 6.

The carrier color signal C ^* is supplied to the input terminal 1C. This color signal C ^* is supplied to the color demodulator 7. The red color difference signal RY (V signal) and the blue color difference signal BY (U signal) output from the color demodulator 7 are supplied to the switch circuit 6.

The luminance signal Y supplied to the input terminal 1Y is also supplied to the AFC circuit 8 including a sync separation circuit and the like. A horizontal synchronizing pulse PH (frequency fh) is supplied from the AFC circuit 8 to the timing generator 4 as a synchronizing reference signal, and a clock, a latch pulse, a switching control signal and the like are formed based on the synchronizing signal PH.

Switching control signals SW1 and SW2 are supplied to the switch circuit 6 from the timing generator 4, and the luminance signal Y is supplied.
And the V and U signals are combined. The combined signal output from the switch circuit 6 is supplied to the A / D converter 9. A /
The D converter 9 receives the clock CLK from the timing generator 4.
1 (frequency is 1100 fh) is supplied and the synthesized signal is 1
The sample is converted into a 6-bit digital signal. In this case, conversion is performed after removing the sync signal in order to secure the S / N.

FIG. 4 shows a part of the switch circuit 6 and the A / D converter 9.

In the figure, 6A and 6B are changeover switches which constitute the switch circuit 6. The V signal is supplied to the fixed terminal on the v side of the changeover switch 6A, and the U signal is supplied to the fixed terminal on the u side. The changeover switch 6A is changed over on the basis of the changeover control signal SW1 and is connected to the v side and the u side by alternating one horizontal period. As a result, the changeover switch 6A alternately outputs the color signal C which is the V signal and the U signal every horizontal period.

Color signal C output from changeover switch 6A
(FIG. 5B) is supplied to the fixed terminal on the c side of the changeover switch 6B, and the luminance signal Y (A in the same figure) is supplied to the fixed terminal on the y side.

The changeover switch 6B is changed over based on the changeover control signal SW2 (FIG. 9C). in this case,
connected to the y side for a period of 18 / 1100fh, and c
The connection with the side for 2/1100 fh is performed alternately. That is, the changeover switch 6B outputs a combined signal in which the color signal C is inserted to the luminance signal Y at a cycle of 1 / 55fh for a period of 2 / 1100fh (D in the same figure).

The output signal of the changeover switch 6B is supplied to the A / D converter 9. In this A / D converter 9, 1/11
It is converted into a digital signal by the clock CLK1 (E in the figure) having a cycle of 00fh (F in the figure).

Returning to FIG. 2, the output signal of the A / D converter 9 (FIG. 6A) is supplied to the latch circuit 10. A latch pulse P1 is supplied from the timing generator 4 to the latch circuit 10 at the timing of each sample data of the luminance signal Y (B in the same figure), and the luminance signal Y is latched (C in the same figure).

The luminance signal Y latched and output by the latch circuit 10 is supplied to the digital low pass filter 11. The clock CLK1 is supplied to the low-pass filter 11 from the timing generator 4 and low-pass processing is performed. By this low-pass processing, the 7-bit luminance signal Y'is output from the low-pass filter 11 (D in the same figure).

The luminance signal Y'output from the low pass filter 11 is supplied to the latch circuit 12. A latch pulse P2 having a frequency of 275 fh is supplied from the timing generator 4 to the latch circuit 12 (E in the figure). Here, the latch pulse P2 is inverted in phase every horizontal period. Therefore, the data rate from the latch circuit 12 is 275 fh.
The line offset sub-sampled luminance signal Y ′ is output (F in the figure).

The output signal of the A / D converter 9 (see FIG. 6)
A) is a parallel / serial converter (P / S converter) 13
Is supplied to. The P / S converter 13 is supplied with the latch pulse P3 from the timing generator 4 at the timing of the sample data of the color signal C having a cycle of 1/55 fh (G in the figure), and the color signal C is latched (the same). (Figure H). The P / S converter 13 further includes 275 fh from the timing generator 4.
The clock CLK2 having the frequency is supplied (I in the figure), and each bit data of the latched sample data is sequentially output (J in the figure). At the time of this conversion, the lower 1 bit (C0) of the color signal C is truncated.

The parallel data (7 bits) luminance signal Y '(FIG. 7A) and P /
Color signal C of serial data output from the S converter 13
(B in the figure) is supplied to the switch circuit 14 as 8-bit parallel data. In this case, the 1-bit color signal C is positioned on the lower bit side of the luminance signal Y '.

The switch circuit 14 includes a timing generator 4
Then, the switching control signal SW3 and the information data INF are supplied, and the information data INF is added to the head of the data in each horizontal period.

The output signal of the switch circuit 14 is supplied to the switch circuit 15. The switching control signal SW4 is supplied from the timing generator 4 to the switch circuit 15 (C in the same figure). The switch circuit 15 alternately outputs the upper 4-bit data and the lower 4-bit data of the 8-bit parallel data at intervals of 1/550 fh (D in the same figure).

As shown in FIG. 7D, the information data I
NF is composed of 4-bit data. Here, OXE indicates whether the field is an odd number or an even number, UXV indicates whether the color signal C of the line is a U signal or a V signal, and AXB indicates that the luminance signal Y ′ of the line is a line offset sub signal. It indicates whether it is the A pattern or the B pattern of sampling. In addition, LDEC indicates that the next line will be decimated.

FIG. 8 shows the configuration of the luminance signal system from the input terminal 1Y to the low pass filter 11.

In the figure, the luminance signal Y supplied to the input terminal 1Y is supplied to the adder 3 via the resistor 2.

In the timing generator 4, the clock CL
K1 (1100 fh) is phase-inverted by the inverter 4A and then frequency-divided by the frequency divider 4B. The output signal of the frequency divider 4B is supplied as a wobbling clock WOB to the adder 3 via the resistor 5. In this case, the addition ratio of the luminance signal Y and the wobbling clock WOB in the adder 3 is determined by the resistance values of the resistors 2 and 5,
The amplitude (peak-to-peak value) of the wobbling clock WOB supplied to the adder 3 is set to be an odd multiple of 1/2 step width of the 6-bit quantization step, which is 1 in this example.

The added signal of the luminance signal Y from the adder 3 and the wobbling clock WOB is supplied to the A / D converter 9 and converted into 6-bit digital data Xn. In this case, as described above, the A / D converter 9 has the clock C.
LK1 (1100fh) is supplied as a conversion clock (sampling clock).

When the wobbling clock WOB is formed as described above, since the phase of the clock CLK1 is inverted by the inverter 4A, the changing point (rising edge and falling edge) of the wobbling clock WOB does not coincide with the sampling point. Is being done.

The 6-bit digital data Xn output from the A / D converter 9 is supplied to the digital adder 11A forming the low pass filter 11 and the data terminal D of the D flip-flop 11B. D
The clock CLK1 (110
0fh) is supplied. From the D flip-flop 11B, one clock period (1/1
Digital data Xn-1 delayed by 100 fh) is obtained, and this digital data Xn-1 is supplied to the adder 11A.

In the adder 11A, the digital data Xn and Xn-1 are added to obtain 7-bit digital data Yn.
Is output, and this digital data Yn is used as the output Y'of the low-pass filter 11.

In this case, the adder 11A and the D flip-flop 11B form a low-pass filter having a cutoff frequency of substantially 1/2 of the frequency of the clock CLK1. Therefore, the wobbling clock WOB added by the adder 3 is automatically removed by the low-pass filter 11 and does not appear in the digital data Yn.

Here, how the digital data Yn is formed will be described.

FIG. 9 shows a quantization state in a normal A / D converter. As is clear from this figure, in a normal A / D converter, the number of bits is from 6 bits (broken line) to 7 bits.
As the number of bits (one-dot chain line) increases, the input luminance signal Y (solid line) approaches, and good results can be obtained. This is because the 7-bit quantization step (Ln and Mn) is finer than the 6-bit quantization step (Ln).

In the present example, the luminance signal Y is added by the adder 3.
A wobbling clock WOB (shown by a broken line in FIG. 10A)
Is added and the signal (Y + W) supplied to the A / D converter 9 is added.
OB) is repeatedly shifted with a half step width of the 6-bit quantization step (shown by the solid line in the figure). Therefore, the digital data Xn output from the A / D converter 9 is arranged as shown by the point "." In the figure.

In the D flip-flop 11B, this digital data Xn is delayed by one clock of the clock CLK1. Therefore, the digital data Xn-1 is arranged as shown by a point "O" in FIG. 10B. Therefore, the 7-bit digital data Yn output from the adder 11A
Are arranged as shown by the points "x" in FIG.

After all, 7-bit digital data Yn
Gives the same result as the quantization by the 7-bit A / D converter (see the alternate long and short dash line in FIG. 9).

Returning to FIG. 2, the 4-bit digital data DW output from the switch circuit 15 is supplied to the movable terminal of the changeover switch 21 as a write signal to the memory. The fixed terminals on the a side and the b side of the changeover switch 21 are connected to the fixed terminals on the a side and the b side of the changeover switch 22, respectively.

The connection points of the fixed terminals on the a side of the changeover switches 21 and 22 are connected to the memory 23A, and the connection points of the fixed terminals on the b side of the changeover switches 21 and 22 are connected to the memory 23.
Connected to B.

Further, the horizontal write start signal WHS is written from the AFC circuit 8 to the memory write timing generator 24.
And a write vertical start signal WVS
Is supplied. In the timing generator 24, the write address signal WAD is generated based on the start signals WHS and WVS.
And the address signal WAD is generated by the switch circuit 2
5 is supplied to the memory 23A or 23B.

Further, from the AFC circuit 8, the synchronization generator 26
Is supplied with the signal HMDP output at the intermediate position of each horizontal period. Then, the synchronization generator 26 outputs the read horizontal start signal RH to the memory read timing generator 27.
S is supplied and read vertical start signal RV
S is supplied. The timing generator 27 uses the read address signal RA based on the start signals RHS and RVS.
D is formed, and this address signal RAD is supplied to the memory 23B or 23A via the switch circuit 25.

A changeover control signal SW5 is supplied from the timing generator 24 to the changeover switches 21 and 22. The changeover switch 21 is connected to the a side in the first half period of each horizontal period, and is connected to the b side in the latter half period. On the other hand, the changeover switch 22 is connected to the b side in the first half period of each horizontal period,
In the subsequent half period, it is connected to the a side.

The switching control signal SW5 is also supplied from the timing generator 24 to the switch circuit 25. As a result, the write address signal WAD is supplied to the memory 23A and the memory 23B is supplied in the first half of each horizontal period.
The read address signal RAD is supplied to. On the other hand, in the latter half of each horizontal period, the write address signal WAD is supplied to the memory 23B and the read address signal RAD is supplied to the memory 23A.

The memories 23A and 23B have a storage capacity of 1/2 horizontal period in the horizontal direction and a storage capacity of 1 vertical period in the vertical direction. Memory 2
The first half data is written in 3A in the first half period of each horizontal period, and the first half data is read from the memory 23A in the second half period of each horizontal period. The latter half data is written in the memory 23B in the latter half period of each horizontal period, and the latter half data is read from the memory 23B in the first half period of each horizontal period.

Here, the conversion of the number of lines and the number of fields is realized by controlling the write address signal WAD and the read address signal RAD to the memories 23A and 23B.

That is, the NTSC system (525/60
System) to the PAL system (625/50 system) (see FIGS. 26A and 27A), thinning is performed at a ratio of 1 field to 6 fields during reading, and at a ratio of 1 line to 5 lines in each field. Same line is 2
Read once.

On the contrary, when converting from the PAL system to the NTSC system (see FIGS. 26B and 27B), 6 is written at the time of writing.
The lines are thinned out at a rate of 1 line, and the same field is repeatedly read at a rate of 1 field to 5 fields during reading. , The memories 23A, 2
The memory capacity of 3B is 262 or 26 of 525/60 series.
Basically 3 lines. When capturing a 625/50 series 312 or 313 line, it is compressed and expanded in the vertical direction.

Most of the horizontal and vertical blanking periods not directly related to the screen are not stored in the memories 23A and 23B. As a result, the storage capacity of the memories 23A and 23B is 84% of the effective screen for all screens.

From the above, the memory capacity required in this example is as follows, and the memories 23A, 23
As B, for example, a general-purpose 256K-bit DRAM can be used.

{(7 × 275) + (5 × 55)} × 263 × 0.84
= 486K bits By the way, the cycle time of a general-purpose 256K bits DRAM requires 200 nsec or more from the designation of row and column address strobes to the completion of data writing or reading. This cycle time is longer than the data cycle (1/550 fh) of the write data DW output from the switch circuit 15, and writing / reading in real time becomes impossible.

Therefore, in this example, when writing and reading data, a write cycle and a read cycle system called page mode are adopted.

That is, in the normal write mode, as shown in FIG.
As shown in FIG. 1A, since both the row address strobe and the column address strobe are designated, the cycle time required from writing these to writing the data DW is 200 nsec.

On the other hand, in the write mode by the page mode, as shown in FIG. 9B, the row address strobe and the column address strobe are designated only for the first cell of each horizontal line, and for the subsequent cells. Need only specify the column address stove, so 2
The cycle time for the cells after the th is 100 nsec.

In FIG. 11, RAS bar is a row address strobe pulse, CAS bar is a column address strobe pulse, WAD is a write address signal, and
DW is write data.

The same applies to the read mode. FIG. 12A shows the timing in the normal read mode, and FIG. 12B shows the timing relationship in the page mode.
In FIG. 12, RAS is a row address strobe pulse, CAS is a column address strobe pulse, RAD is a read address signal, and DR is read data.

According to the page mode, the cycle time is the data cycle of the write data DW (1 / 550f
Since it is shorter than h), the general-purpose DRAM described above can be used.

Returning to FIG. 2 and FIG. 3, the read data DR output from the changeover switch 22 is the demultiplexer 3
1 is supplied. The horizontal synchronization pulse PH ′ is supplied from the synchronization generator 26 to the read timing generator 32. The demultiplexer 31 is supplied with the switching control signal SW6, the latch pulses P4 to P6 and the control signal CNP from the timing generator 32. From the demultiplexer 31,
The information data INF, the luminance signal Y ', and the color signal C separated from the output signal of the changeover switch 22 are output.

FIG. 13 is a diagram showing a specific configuration of the demultiplexer 31. In the figure, the read data DR (FIG. 14A) output from the changeover switch 22 is supplied to the movable terminal of the changeover switch 31A. Changeover switch 31
The switching control signal SW6 is supplied to A, and is connected to the a side in correspondence with the period of the information data INF added at the beginning of each horizontal period, and is connected to the b side in the other periods. Information data INF is obtained at the fixed terminal on the a side of the changeover switch 31A.

The signal obtained at the fixed terminal on the b side of the changeover switch 31A is the data terminal D of the latch circuits 31B and 31C.
Is supplied to. The latch pulse P4 is supplied to the latch circuit 31B at the timing of the 4-bit data Y6 'to Y3' (FIG. 14B), and the 4-bit data Y6 'to Y3' is output from the latch circuit 31B at the data rate of 275fh. (Fig. C). A latch pulse P5 is supplied to the latch circuit 31C at the timing of 4-bit data Y2 'to Y0' and C (any of C5 to C1) (D in the figure), and 4-bit data Y2 'from the latch circuit 31C. ~ Y0 ', C (C
5 to C1) is output at a data rate of 275 fh (E in the same figure).

The 4-bit data Y6 'to Y3' output from the latch circuit 31B and the 3-bit data Y2 'to Y0' output from the latch circuit 31C are the latch circuit 31.
It is supplied to the data terminal D of D. 1-bit data C output from the latch circuit 31C (any one of C5 to C1)
Is supplied to the data terminal D of the latch circuit 31E.

The latch circuits 31D and 31E have 275f.
A latch pulse P6 having a frequency of h is supplied (F in the same figure). As a result, 275 fh from the latch circuit 31D
The 7-bit luminance signal Y'is output at the data rate of (7) (G in the figure), and the 5-bit color signal C (data rate of 55 fh) is output from the latch circuit 31E as serial data (H in the figure).

The luminance signal Y'output from the latch circuit 31D is output via the phase adjuster 31F. The control signal CNP is supplied to the phase adjuster 31F based on the data AXB included in the information data INF, and the phase adjustment of the sample data of the luminance signal Y ′ in each horizontal period is performed. As a result, the data of each line of the luminance signal Y'is output while maintaining the phase relationship of the line offset.

Returning to FIG. 3, the information data INF output from the demultiplexer 31 is supplied to the synchronization generator 26 and the timing generator 32.

The luminance signal Y'output from the demultiplexer 31 is supplied to the filter circuit 33 and the fixed terminal on the side a of the changeover switch 34. The changeover switch 34 is supplied with the changeover control signal SW7 from the timing generator 32. The output signal of the changeover switch 34 is 1
It is supplied to the delay circuit 35 having a delay time of the horizontal period. The output signal of the delay circuit 35 is supplied to the filter circuit 33 and the fixed terminal on the b side of the changeover switch 34. The filter circuit 33 includes a timing generator 32.
The switching control signal SW8 is supplied.

FIG. 15 shows a specific configuration of the filter circuit 33, the changeover switch 34, and the delay circuit 35, which is a processing circuit for the line offset sub-sampled luminance signal Y '.

Here, the signal of the line sampled at a certain phase is taken as the line signal of the A pattern, and the signal of the line sampled at its inverted phase is taken as the line signal of the B pattern. These patterns are identified by the data AXB included in the information data INF as described above.

In the figure, the input signal Sin (luminance signal Y ') is supplied to a high-pass filter 33A constituting the filter circuit 33, and the high-frequency component SH of the signal Sin extracted by this high-pass filter 33A is subtracted by the subtracter 33B and It is supplied to the fixed terminal on the side a of the changeover switch 33C.

Further, the input signal Sin is supplied to the subtractor 33B via the delay circuit 33D for time adjustment. The delay time of the delay circuit 33D is set to be equal to the delay amount in the high pass filter 33A.

In the subtractor 33B, the high frequency component SH extracted by the high pass filter 33A is subtracted from the video signal Sin output from the delay circuit 33D, and the low frequency component SL of the signal Sin is subtracted.
Is output.

The input signal Sin is supplied to the fixed terminal on the side a of the changeover switch 34, the output signal of the changeover switch 34 is supplied to the delay circuit 35, and the output signal of the delay circuit 35 is on the side b of the changeover switch 34. Supplied to the fixed terminal of. The changeover switch 34 is changed over by the changeover control signal SW7.
Based on. That is, the changeover switch 34
Is a line signal of A pattern or B pattern is continuously supplied as the input signal Sin for two or more lines,
Each horizontal period from the first line of the continuous lines to the line immediately before the last line is connected to the b side, and the other horizontal periods are connected to the a side.

Here, the line signal of the A pattern or the B pattern is continuous for two lines or more because the line number may be increased by double reading in the line number conversion or may be reduced by thinning. In this example, when the signals of the 625/50 system are loaded into the memories 23A and 23B, vertical compression / expansion processing is performed due to the storage capacity. Even with this compression / expansion processing, signals of the same pattern continue for two lines or more. Sometimes.

Whether or not the same pattern continues for two or more lines is determined by the data AXB included in the information data INF separated by the demultiplexer 31.

The signal Sin 'of one horizontal period before output from the delay circuit 35 is supplied to the high-pass filter 33E, and the high-frequency component S extracted by this high-pass filter 33E.
H'is supplied to the fixed terminal on the b side of the changeover switch 33C. The high frequency component SH2 selected and output by the changeover switch 33C is supplied to the adder 33F.

The changeover switch 33C is set to 1 based on the changeover control signal SW8 supplied from the timing generator 32.
It is alternately switched to the a side and the b side by changing the / 2 sampling cycle. In this case, the high pass filter 33
It is connected to the a side in correspondence with the sampling timing of the high frequency component SH output from A. The sampling timing of the high frequency component SH is determined by the data AXB included in the information data INF separated by the demultiplexer 31.

The low frequency component SL of the signal Sin output from the subtractor 33B is supplied to the adder 33G and the fixed terminal on the a side of the changeover switch 33H.

The high frequency component SH 'of the signal Sin' output from the high pass filter 33E is supplied to the subtractor 33I,
The signal Sin 'output from the delay circuit 35 is supplied to the subtractor 33I via the delay circuit 33J for time adjustment. The delay time of the delay circuit 33J is equal to the high pass filter 3
It is set to be equal to the delay amount in 3E.

In the subtractor 33I, the high frequency component SH 'output from the high pass filter 33E is subtracted from the signal Sin' output from the delay circuit 33J. The low frequency component SL 'of the signal Sin' is output from the subtractor 33I, and this low frequency component SL 'is supplied to the adder 33G.

In the adder 33G, the video signals Sin and Si
The low frequency components SL and SL 'of n'are added and averaged, and the output signal (SL + SL') / 2 is supplied to the fixed terminal on the b side of the changeover switch 33H.

The low frequency component selected by the changeover switch 33H is supplied to the adder 33F and is added to the high frequency component SH 'selected by the changeover switch 33C. And adder 3
The output signal of 3F is the output signal Sout of the filter circuit 33.
(Y ″).

In the above configuration, first the changeover switch 3
A case where 3H is connected to the a side will be described. Signal S
When the line signals of the A pattern and the B pattern are alternately supplied as in (see FIG. 16), it becomes as follows.

When the signal Sin is an n-1 line signal, the signal Sin 'output from the delay circuit 35 is an n-2 line signal. From the changeover switch 33C, n-1
A high-frequency component SH2 in which the high-frequency component SH of the line signal and the high-frequency component SH 'of the signal of the n-2 line are alternately selected with a 1/2 sampling period is output. The signal Sout on the output line becomes an addition signal of the high frequency component SH2 and the low frequency component SL of the signal on the n-1 line (see FIG. 17A).

When the signal Sin is an n-line signal, the signal Sin 'output from the delay circuit 35 is an n-1 line signal. From the change-over switch 33C, the high frequency component SH of the n-line signal and the high frequency component SH 'of the n-1 line signal are output.
The high-frequency component SH2, which is alternately selected with 1/2 sampling period, is output. Output line signal Sout
Is the high frequency component SH2 and the low frequency component SL of the n-line signal.
17B (see FIG. 17B).

As described above, the high frequency component SH2 included in the signal Sout is sampled at a sampling cycle of substantially 1/2, and the high frequency range is improved.

When the line signals of the same pattern are continuously supplied as the signal Sin (see FIG. 18), the following occurs.

For example, as shown in FIG. 18, when the n-1 line and the n line continuously form a B pattern line signal, the line signals of the same pattern continue in the n-1 line and the n line. Therefore, the changeover switch 34 is connected to the b side during the horizontal period in which the signal of the n-1 line is supplied. Therefore, during the two horizontal periods in which the signals of the n−1 line and the n line are supplied, the delay circuit 35 outputs n−
The signals of two lines are continuously output.

Therefore, as the signal Sin, n-2 to n +
When signals of two lines are supplied (see FIG. 18), the delay circuit 35 outputs signals of n−3 to n−1 lines as the signal Sin ′ (see FIG. 19). The patterns of the Sin 'line signals are different from each other.

Therefore, the sampling timings of the high frequency components SH and SH 'output from the high pass filters 33A and 33E are always alternating, and the changeover switch 33
From C, the high frequency component SH2 sampled at substantially 1/2 sampling period is obtained.

When the signal Sin is an n-1 line signal (B pattern), the signal Si output from the delay circuit 35.
n'becomes a signal (A pattern) on the n-2 line. From the changeover switch 33C, the high frequency component SH2 of the signal of the n-1 line and the high frequency component SH 'of the signal of the n-2 line are alternately selected at a 1/2 sampling period.
Is output. The signal Sout on the output line is a signal obtained by adding the high frequency component SH2 and the low frequency component SL of the signal on the n-1 line (see FIG. 20A).

Signal Sin is an n-line signal (B pattern)
Also, the signal Sin ′ output from the delay circuit 35
Is a signal (A pattern) of the n-2 line. From the change-over switch 33C, the high frequency components SH and n
The high frequency component SH2, which is alternately selected with the high frequency component SH 'of the -2 line signal at a 1/2 sampling period, is output. The signal Sout on the output line is the high frequency component SH2.
And the low frequency component SL of the signal of the n line is added (see FIG. 20B).

Thus, even when the line signals having the same pattern are continuously supplied as the signal Sin, the changeover switch 33C outputs the high frequency component SH2 sampled at a substantially 1/2 sampling period. , The improved signal Sout in the high frequency range can be obtained.

Next, the case where the changeover switch 33H is connected to the b side will be described. The high frequency component is the same as the case where the changeover switch 33H is connected to the side a, and the description thereof will be omitted. Regarding the low frequency components, the low frequency components SL and SL 'of the signals Sin and Sin' are added and averaged by the adder 33G, and this added and averaged low frequency component (SL + SL ') / 2 is applied to the side b of the selector switch 33H. It is supplied to the adder 33F via the.

Therefore, the signal Sout output from the adder 33F is the sum of the low frequency component (SL + SL ') / 2 and the high frequency component SH2.

When the signal Sin is an n-1 line signal, the signal Sin 'output from the delay circuit 35 is an n-2 line signal. From the changeover switch 33C, n-1
A high frequency component SH2 in which the high frequency component SH of the line signal and the high frequency component SH 'of the n-2 line are alternately selected in a 1/2 sampling cycle is output. Also, the adder 33G
Outputs a low-frequency component (SL + SL ') / 2 obtained by adding and averaging the low-frequency component SL of the n-1 line signal and the low-frequency component SL' of the n-2 line signal. Output signal Sout
Is a signal obtained by adding the high frequency component SH2 and the low frequency component (SL + SL ') / 2 by the adder 33F (see FIG. 21A).

When the signal Sin is an n-line signal, the signal Sin 'output from the delay circuit 35 is an n-2 line signal. From the change-over switch 33C, the high frequency component SH of the n-line signal and the high frequency component SH 'of the n-2 line are 1
The high frequency component SH2, which is alternately selected in the / 2 sampling cycle, is output. From the adder 33G, the low-frequency component SL of the n-line signal and the low-frequency component SL 'of the n-2 line signal are added and averaged to obtain the low-frequency component (SL + SL').
/ 2 is output. The output signal Sout is the high frequency component SH.
2 and the low frequency component (SL + SL ') / 2 become the signal added by the adder 33F (see FIG. 21B).

Thus, the high frequency component of the output signal Sout is SH
Since it is 2, the high frequency band is improved, and the low frequency band component is (SL + SL ') / 2, and the signal is averaged in the vertical direction to improve the jaggedness.

Note that averaging the signals in the vertical direction generally deteriorates the resolution in the vertical direction. Therefore, in the example of FIG. 15, the changeover switch 33 is used only when the number of lines increases due to double reading, which causes a problem of jaggedness.
It is effective to connect H to the b side.

Returning to FIG. 3, the luminance signal Y ″ of the 8-bit parallel data output from the filter circuit 33 is supplied to the fixed terminal on the a side of the changeover switch 36. 37 is a pedestal level signal and a synchronization level signal. The signal generator 37 is supplied with the timing signal ST1 for generating the respective signals from the synchronization generator 26. The output signal of the signal generator 37 is the changeover switch 36.
Is supplied to the fixed terminal on the side b.

The changeover switch 36 is supplied with a changeover control signal SW9 from the synchronization generator 26. The changeover switch 36 is connected to the b side during the period of the sync signal and the pedestal signal, and is connected to the a side during the other periods. Therefore, the changeover switch 36 outputs the added luminance signal such as the synchronizing signal.

The luminance signal output from the change-over switch 36 is converted into an analog signal by the D / A converter 38, then band-limited by the low-pass filter 39 and supplied to the adder 40.

The color signal C of 1-bit serial data separated by the demultiplexer 31 is supplied to the serial / parallel converter (S / P converter) 41. The S / P converter 41 is supplied with the clock CLK3 synchronized with each bit data of the color signal C from the timing generator 32, and also with the latch pulse P7 at the timing of every 5 bits (C5 to C1).

The color signal C converted into 5-bit parallel data by the S / P converter 41 is supplied to the fixed terminals on the side a of the change-over switches 42 and 43, and also the change-over switch 44.
Is supplied to the fixed terminal on the side b.

The output signal of the changeover switch 42 is supplied to the delay circuit 45 having a delay time of one horizontal period, and the output signal of the delay circuit 45 is supplied to the fixed terminal on the b side of the changeover switch 42. The changeover switch 42 is supplied with the changeover control signal SW10 from the timing generator 32.

As described above, the color signal C before the line number is converted by writing / reading to / from the memories 23A and 23B is a line-sequential signal which becomes the V signal and the U signal every horizontal period, but the line number is converted. The color signal C after being processed becomes a line in which two lines of the same color are periodically continuous by thinning or double reading.

The changeover switch 42 has a changeover control signal SW10.
The first line of two consecutive lines is switched to the b side, and the other periods are connected to the a side. The switching control signal SW10 is formed, for example, based on the data LDEC included in the information data INF separated by the demultiplexer 31 when lines are thinned out at the time of writing, and when the same line is read twice at the time of reading. , Based on that information.

The output signal of the delay circuit 45 is the changeover switch 4
3 is supplied to the fixed terminal on the b side and also to the fixed terminal on the a side of the changeover switch 44. Changeover switch 4
The switching control signal S from the timing generator 32 is supplied to the switches 3 and 44.
W11 is supplied. The changeover switches 43 and 44 are S /
One horizontal period in which the color signal C from the P converter 41 is the U signal is connected to the a side, and conversely, one horizontal period in which the color signal C is the V signal is connected to the b side. The switching control signal SW11 is formed based on the data UXV included in the information data INF separated by the demultiplexer 31.

Here, the case where the same line is read twice at a ratio of one line to five lines and the number of lines is increased will be described. At this time, as shown in FIG. 22A, the lines of the same color are periodically output from the S / P converter 41.
A line-continuous color signal C is output.

At this time, the switching control signals SW10 and SW1
1 is formed as shown in FIGS. Therefore, the output signal of the delay circuit 45 becomes as shown in D of the same figure, and the synchronized U signal and V signal are respectively obtained from the changeover switches 43 and 44 (shown in E and F of the same figure).

Although not described, the number of lines is reduced by thinning out one line to six lines,
Even when the S / P converter 41 outputs a color signal C in which two lines of the same color are cyclically continuous, the changeover switches 43 and 44 similarly similarly synchronize the synchronized U signal and V signal, respectively. The signal is obtained.

The U signal output from the changeover switch 43 is supplied to the fixed terminal on the a side of the changeover switch 46. 47
Is a signal generator for generating burst level and blanking level signals. The signal generator 47 is supplied with the timing signal ST2 for generating the respective signals from the synchronization generator 26. The output signal of the signal generator 47 is supplied to the fixed terminal on the b side of the changeover switch 46.

The V output from the changeover switch 44
The signal is supplied to the fixed terminal on the a side of the changeover switch 48. 49 is a signal generator for generating burst level and blanking level signals. The signal generator 49 is supplied with the timing signal ST2 for generating the respective signals from the synchronization generator 26. The output signal of the signal generator 49 is supplied to the fixed terminal on the b side of the changeover switch 48.

The changeover switches 46 and 48 are provided with the synchronization generator 2.
The switching control signal SW12 is supplied from the switch 6. The changeover switches 46 and 48 are connected to the b side during the burst period and the blanking period, and are connected to the a side during the other periods. Therefore, the changeover switches 46 and 48 output the U and V signals to which the burst level signal and the like have been added.

U output from the changeover switches 46 and 48
The signal and the V signal are supplied to the color modulator 50. Color modulator 5
At 0, the color subcarrier of 4.43 MHz is used when converting from the NTSC system to the PAL system, while the color subcarrier of 3.58 MHz is used when converting from the PAL system to the NTSC system.

The 6-bit parallel data carrier color signal output from the color modulator 50 is converted to an analog signal by the D / A converter 51, and then supplied to the adder 40 via the bandpass filter 52. .. Then, the adder 40 adds the luminance signal and the carrier color signal, and the format-converted video signal SV is derived at the output terminal 53.

[0138]

By the way, the above-mentioned television system conversion device has the following problems. (1) Cross-color and dot interference at the time of inputting NTSC3.58 Input terminals 1Y and 1C have, for example, a luminance signal Y and a carrier color signal C ^* separated from a composite video signal ^.
Is supplied.

When the luminance signal Y and the carrier color signal C ^* are not sufficiently separated, the high frequency component of the luminance signal Y is the carrier color signal C.
Luminance signal Y mixed with ^* side and original carrier color signal component
The components are demodulated, producing iridescent color noise, or cross color, unrelated to the original color.

When the luminance signal Y and the carrier color signal C ^* are not sufficiently separated, the carrier color signal component is mixed in the high range of the luminance signal Y, and fine net-like noise, that is, dot interference occurs.

These are particularly conspicuous at the time of input of NTSC 3.58 in which the upper limit of the band of the luminance signal is close to the color subcarrier frequency, which causes a loss in the converted output image. (2) The number of lines is thinned out, and the figure distortion is converted by interpolation. When the system is converted, the number of lines is converted as the memory is written and read. In the case of conversion from NTSC to PAL, reading (interpolation) is performed twice at a rate of 1 line out of 5 lines and conversion is performed from 525 lines to 625 lines. On the other hand, in the case of conversion from PAL to NTSC, thinning is performed at a ratio of 1 line to 6 lines to 525 from 625 lines.
Converted to line. Therefore, as shown in FIG. 23, the graphic distortion occurs particularly in the oblique direction of the graphic. (3) Folding distortion in the diagonal direction of 45 ° due to subsampling For subsampling, the sampling position of the input data is shifted to each line by half of the sampling period, written in the memory, and the high frequency component is compensated by the arithmetic processing after reading. Thus, it is possible to reduce the memory capacity while maintaining the apparent data band for the sampling period.

That is, if the normal sampling clock is 4.3 MHz (275 fh), the bandwidth that can be handled by the sampling theorem will be 2.6 MHz or less, but if subsampling is used, the same clock will produce 3.6 MHz.
The bandwidth of can be secured. The clock at this time is 4.
Since it is the same as 3 MHz, the data amount does not change.

By the subsampling, the horizontal and vertical bands of the image are secured, but as is clear from FIG. 24, the sampling interval in the 45 ° direction remains wide because the subsampling effect is not added. for that reason,
For example, if there is a relatively wide band input such as a video signal from a laser disk reproducing device, the high frequency component of the diagonal frequency component becomes aliasing distortion, and the edges of the diagonal graphic are pulsated on the screen. It becomes unsightly. (4) Vertical Jitter In the conversion of NTSC → PAL or the conversion of PAL → NTSC, the number of lines and the number of fields are converted. As is well known, in a field of a television, an odd field "O" and an even field "E" are repeated by an interlacing operation. However, during conversion as shown in FIG. 25, an odd field to an even field and vice versa are converted. Is performed periodically.

On the screen, the line positions of the even and odd fields are shifted from each other. For example, if there are fine horizontal lines, the odd field is changed to the odd field and the odd field is changed to the even field. Cause Moreover, since this is periodically repeated, it appears as vertical jitter-like movement.

Therefore, the present invention provides a video signal processing device which eliminates the above-mentioned drawbacks.

[0146]

SUMMARY OF THE INVENTION The present invention is a low pass filter for separating a luminance signal from a composite video signal, a comb filter to which a luminance signal is supplied, and a band pass filter for separating a carrier color signal from a composite video signal. And a color demodulator that demodulates a color difference signal from the carrier color signal, and a series circuit of a low-pass filter and a vertical filter to which the color difference signal is supplied.

[0147]

The carrier color signal component contained in the luminance signal that cannot be completely removed by the low-pass filter can be removed by the comb filter arranged in the luminance signal system, and dot interference can be improved. In addition, since this comb filter also constitutes a vertical filter, lines in the vertical direction are averaged, and graphic distortion due to line number conversion (interpolation or thinning),
It is possible to improve the fold-back distortion in the diagonal direction when a wideband video signal is input and the vertical jitter due to field conversion.

Further, the cross color component of the color signal system has many high frequency components, which can be reduced by the low-pass filter arranged in the color signal system, and the cross color can be improved. Further, the vertical filter arranged in the color signal system can improve the graphic distortion due to the conversion of the number of lines like the comb filter arranged in the luminance signal system.

[0149]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

In the figure, the composite video signal SV is supplied to the input terminal 101. This video signal S
V is a low-pass filter 1 with a cut-off frequency of 3 MHz
02, and the luminance signal Y is extracted. The luminance signal Y output from the low-pass filter 102 is the resistor 10
It is supplied to the adder 106 through a series circuit of 3 and 104. The connection switch 107 is connected in parallel with the resistor 103.

The luminance signal Y output from the low-pass filter 102 is sent to the adder 106 via the series circuit of the delay circuit 108 and the resistor 109 having the delay time (63.5 μsec) of one horizontal period of the NTSC system. Supplied. The delay circuit 108 is composed of, for example, a CCD, and
0.7 MHz (3.58 MHz x 3) drive clock C
It is driven by LKa. The connection point of the delay circuit 108 and the resistor 109 is grounded via the connection switch 110.

The connection switches 107 and 110 are turned off when the video signal SV is in the NTSC system, and PAL
It is turned on when it is a system. Connection switch 107,
When 110 is off, the luminance signal Y of the current line output from the low pass filter 102 and the luminance signal of the previous line output from the delay circuit 108 are added by the adder 106. So that they are added at a ratio of 1: 1, the resistance values of the resistors 103 and 104 (R103 + R10
4) and the resistance value R109 of the resistor 109 are set.

When the connection switches 107 and 110 are on, only the luminance signal Y of the current line output from the delay circuit 102 is supplied to the adder 106, but the output of the adder 106 does not change. To be That is, by turning on the connection switch 107, it is possible to prevent the output of the adder 106 from being halved so that the resistors 103 and 104 can be prevented.
The resistance values R103 and R104 are set.

The luminance signal output from the adder 106 is a low-pass filter 11 having a cutoff frequency of 2.5 MHz.
After being band-limited and time-aligned with a color signal system to be described later at 1, the data is supplied to the A / D converter 112 and converted into digital data.

[0155] The video signal SV supplied to the input terminal 101 is a carrier chrominance signal is supplied to a band-pass filter 115 C ^* is withdrawn, the carrier chrominance signal C ^* is supplied to the color demodulation circuit 116.

The red color difference signal V (RY) output from the color demodulation circuit 116 is band-limited by the low-pass filter 117 having a cutoff frequency of 500 KHz, and then the resistor 11 is supplied.
8 to the adder 119. The red color difference signal band-limited by the low-pass filter 117 is added through the adder 1 through the resistor 121 and the delay circuit 120 having a delay time (64.0 μsec) for one horizontal period of the PAL system.
19 are supplied. The delay circuit 120 is composed of, for example, a CCD, and 13.3 MHz output from the oscillator 122.
It is driven by a drive clock CLKb of (4.43 MHz × 3). The red color difference signal output from the adder 119 is supplied to the A / D converter 112 and converted into digital data.

Also, the system of the blue color difference signal U (BY) output from the color demodulation circuit 116 is the same as the system of the red color difference signal V described above, and the low pass filter 123, the resistor 124,
The data is supplied to the A / D converter 112 via a processing circuit including a 127, an adder 125, and a delay circuit 126, and converted into digital data.

This example is constructed as described above, and is shown in FIGS.
When used in the system conversion device of the example, the luminance signal output from the low-pass filter 111 is supplied to the input terminal 1Y, and the color difference signals output from the adders 119 and 125 are supplied to the switch circuit 6. It

First, the operation of the luminance signal system will be described.

Video signal S supplied to input terminal 101
When V is the NTSC system, connection switches 107, 1
10 is turned off. The delay time of the delay circuit 108 is NT
Since it is one horizontal period of the SC system and the addition ratio of the current line and the signal one line before in the adder 106 is 1: 1, the adder 106, the delay circuit 108 and the like form a comb filter. .. Therefore, the low-pass filter 102
The carrier color signal component included in the luminance signal Y that cannot be completely removed in step S6 is removed by the comb filter. Therefore, the carrier color signal component included in the luminance signal Y output from the low-pass filter 111 is reduced, and the dot interference, which is a problem when NTSC 3.58 is input, is improved.

Further, since the adder 106, the delay circuit 108, etc. constitute a vertical filter for averaging the signal of the current line and the signal one line before, the luminance signal output from the low-pass filter 111 is of two adjacent lines. The signal will be averaged. Therefore, for example, when used in the system conversion apparatus of the examples of FIGS. 2 and 3, graphic distortion due to line number conversion (interpolation or thinning), oblique folding back when a wideband video signal is input, and field conversion. Vertical jitter is improved.

Video signal S supplied to input terminal 101
When V is the PAL system, the connection switches 107, 1
Since 10 is turned on, the adder 106 and the delay circuit 10
8 or the like does not constitute a comb-shaped filter or a vertical filter, so that it is not possible to obtain the same effect as the above-mentioned NTSC system.

If the delay circuit 108 is constructed to have a delay time of one horizontal period of the PAL system, the NTS
As in the case of the C method, it is possible to obtain the effect of the vertical filter.

Next, the operation of the color signal system will be described.

The crosstalk component due to the luminance signal component contained in the carrier color signal C ^* has many high frequency components, and the lowtalk filters 117 and 123 remove the crosstalk component contained in the color difference signals U and V.

When the video signal SV supplied to the input terminal 101 is of the PAL system, the delay circuit 120
Since (126) has a delay time for one horizontal period of the PAL system, the adder 119, the delay circuit 120, etc. (adder 1
25, the delay circuit 126, etc.) forms a vertical filter that averages the signals of the current line and the signal one line before. in this case,
In addition to averaging the signals of two adjacent lines, the cross color components not removed by the low pass filters 117 and 123 are removed.

On the other hand, when the video signal SV is of the NTSC system, the delay circuit 120 has a delay time of one horizontal period of the PAL system, but the time difference of one horizontal period is not a problem and the band of the color difference signal is not. Is sufficiently narrower than the luminance signal, the adder 119, the delay circuit 120, etc. (adder 12
5, the delay circuit 126, etc.) can obtain the vertical filter effect as in the case of the PAL system.

Therefore, the color difference signals output from the adders 119 and 125 have a reduced cross color component, and the cross color can be improved. The color difference signals output from the adders 119 and 125 are
The signals of two adjacent lines are averaged, and it is possible to improve the graphic distortion and the like due to the conversion of the number of lines as in the case of the luminance signal system.

Even if the delay times of the delay circuits 120 and 126 are set to one horizontal period of the NTSC system, the relationship between the PAL system and NTSC described above is only reversed, and a good vertical filter effect is obtained in both. Obtainable.

[0170]

According to the present invention, the carrier color signal component included in the luminance signal can be removed by the comb filter provided in the luminance signal system without being removed by the low-pass filter, and dot interference is improved. be able to. In addition, since this comb filter also constitutes a vertical filter, vertical lines are averaged, graphic distortion due to line number conversion, diagonal folding distortion when a wideband video signal is input, and field conversion. It is possible to improve vertical jitter and the like.

Further, the cross color component can be reduced by the low pass filter and the vertical filter arranged in the color signal system,
Cross color can be improved. Further, the vertical filter arranged in the color signal system can improve the graphic distortion due to the conversion of the number of lines like the comb filter arranged in the luminance signal system.

Therefore, the present invention is suitable for being arranged in the preceding stage of the television system conversion device. That is,
It is possible to prevent the deterioration of the image quality without changing the main body of the system conversion device to be LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment.

FIG. 2 is a block diagram showing an example of a television system conversion device.

FIG. 3 is a block diagram showing an example of a television system conversion device.

FIG. 4 is a connection diagram showing a configuration of an A / D conversion processing unit.

FIG. 5 is a diagram for explaining the operation of the example of FIG.

FIG. 6 is a diagram for explaining the operation of the example of FIG.

FIG. 7 is a diagram for explaining the operation of the example of FIG.

FIG. 8 is a connection diagram showing a configuration of a luminance signal quantization processing unit.

FIG. 9 is a diagram for explaining quantization in a normal A / D converter.

FIG. 10 is a diagram for explaining quantization in the example of FIG.

FIG. 11 is a diagram illustrating a memory write cycle in a normal mode and a page mode.

FIG. 12 is a diagram for explaining a memory read cycle in a normal mode and a page mode.

FIG. 13 is a connection diagram showing a configuration of a demultiplexer.

FIG. 14 is a diagram for explaining the operation of the demultiplexer.

FIG. 15 is a connection diagram showing a configuration of a sub-sampling data processing circuit.

FIG. 16 is a diagram showing sub-sampling data.

FIG. 17 is a diagram for explaining the signal processing of the example of FIG.

FIG. 18 is a diagram showing sub-sampling data (double reading).

FIG. 19 is a diagram showing data of a main part of the processing circuit of the example of FIG.

20 is a diagram for explaining the signal processing of the example of FIG.

FIG. 21 is a diagram for explaining the signal processing of the example of FIG. 15.

FIG. 22 is a diagram for explaining color signal synchronization processing.

FIG. 23 is a diagram for explaining graphic distortion due to interpolation and thinning.

FIG. 24: Subsampling (diagonal folding distortion)
It is a figure for explaining.

FIG. 25 is a diagram for explaining vertical jitter.

FIG. 26 is a diagram for explaining conversion of the number of lines in the system conversion.

FIG. 27 is a diagram for explaining field number conversion in system conversion.

[Fig. 28] Fig. 28 is a diagram for describing line number conversion in system conversion.

[Explanation of symbols]

 101 input terminal 102,111,117,123 low-pass filter 106,119,125 adder 108,120,126 delay circuit 115 band-pass filter 116 color demodulation circuit

Claims (1)

[Claims] 1. A low-pass filter for separating a luminance signal from a composite video signal, a comb filter to which the luminance signal is supplied, a band-pass filter for separating a carrier color signal from the composite video signal, and the carrier color signal. A video signal processing device comprising a color demodulator for further demodulating a color difference signal, and a series circuit of a low-pass filter and a vertical filter to which the color difference signal is supplied.