JP3295670B2 - Television system converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television system converter.

[0002]

2. Description of the Related Art Currently, the television (TV) system adopted in the world mainly has the following three types in view of the structure of a composite video signal.
Divided into methods. Method name Scanning line / frame Color subcarrier Modulation method NTSC 525/60 3.58 MHz Quadrature two-phase modulation PAL 625/50 4.43 MHz Quadrature two-phase modulation However, V axis phase inversion for each scanning line SECAM Same as above 4.25 MHz 4.206 MHz FM Modulation Further, NTSC and PAL mutually have a combination of the number of scanning lines / frames and the color modulation method, and are as follows. Method name Scanning line / frame number Color subcarrier V-phase inversion per scanning line 4.43 NTSC 525/60 4.43 MHz None M-PAL 525/60 3.58 MHz Available N-PAL 625/50 3.58 MHz Available , NTSC, M-PAL, N-PAL 3.58
MHz is slightly different from each other.

[0003] From these, requirements necessary for mutual conversion between television systems are summarized in the following two. (1) Conversion of scanning line / number of frames (line / field) 525
/ 60, 625/50 (2) Conversion of color modulation method Carrier frequency (fsc) Quadrature two-phase modulation, FM modulation Presence or absence of V-axis phase inversion (2) is suitable for each method as a color signal demodulator and modulator By using one, it can be easily performed. However, (1) generally requires an image memory because a time lag occurs between signals before and after conversion.

[0004] In some cases, the application is limited to viewing on a television receiver, and the system conversion is performed using only the conversion process (2).

Although it is expected that the vertical synchronizing circuit of the 625/50 system TV has a large allowable capacity and can sufficiently cope with the 525/60 system TV signal, it is necessary to re-adjust the vertical synchronization slightly. In essence, it is inevitable that the figure is crushed up and down and becomes flat.

[0006] Also, as described above, it is limited to TV viewing only.
Even if it is possible to view and listen to the 525/60 system TV signal, it is impossible to record and reproduce it on a 625/50 system VTR or the like because the tolerance for the difference in vertical synchronization is small in the VTR. However, in terms of cost, it can be realized at low cost because only the demodulation of the color signal is performed.

When the conversion of (1) is also performed, first, the number of lines must be converted. 525/60 →
In the case of 625/50 system conversion, 100 per field
This is a line increase, and it is necessary to increase the ratio by one line for every five lines (illustrated in FIG. 41A). 625/50 →
In the case of the 525/60 conversion, the number of lines is reduced by 100 lines per field, and it is necessary to reduce the number of lines by one line per six lines (shown in FIG. B). This increase or decrease in the number of lines
Simply, the same line can be realized by duplication or thinning.

[0008] From strict calculations, simple duplication of every five lines or thinning out of every six lines results in the number of lines after conversion being ± 5 lines, which is absorbed during the vertical blanking period. .

As is clear from FIG. 41, the line number conversion requires an image memory for one line or more. In the figure, it looks as if one line is enough, but in order to convert all one field, an image memory for one field or more is required as shown below.

FIG. 42 shows field number conversion.
Looking at the conversion part of the m + 4 → m + 4 ′ field in FIG. A, the last line of the m + 4 field shifts to the m + 4 ′ field (arrow P1), which coincides with the timing of the last line of the m + 5 field. Therefore, m +
It is necessary to delay the last line of the four fields by one field.

On the other hand, looking at the conversion part of the n → n ′ field in FIG. 1B, the last line of the n field is n−n.
This coincides with the timing of the last line of the 1 'field (arrow P2), and a delay of one field is required.
The same occurs in the conversion part of the n + 5 → n + 5 ″ field (arrow P3).

Strictly speaking, the above-mentioned line coincidence
Because a slight line difference does not completely match,
No field delay is required, but here one field is used for simplicity.

A one-field delay is now commonly realized by digitizing the signal and using digital memory as the image memory.

Horizontal resolution: 320 lines, luminance (Y) S / N
Is 46 dB, and the color (C) S / N ratio is 36 dB or more. The format required for converting a standard TV signal into one field has the following memory capacity. However, in the C system, the color difference signals RY = V, B
It is assumed that demodulation has been performed to the state of −Y = U, and two systems are required.

[0015] Here, Y type, C type sampling frequency and gradation of, consider the following settings.

[0016] Y-sampling frequency: 8 MHz tone: 8-bit C system Sampling frequency: 3 MHz tone: 6 bits also considering the interconversion of 525/60 system and the 625/50 system, one field 625/50 system (In the case of FIG. 42B).

From the above, the memory capacity of one field can be obtained by the following equation. ^{{8 × 8 × 10 6 +} (6 × 3 × 10 6 × 2)} ÷ 50 = 1.8 × 10 6 = 1.8M bits Note that the resolution set in the above, when improvement of gradation is required In addition, the memory capacity is increased.

Further, looking at the line number conversion in more detail, since the TV signal is interlaced in both the 525/60 system and the 625/50 system, a simple field signal as shown in FIG. In the unit line number conversion, the vertical image quality may be impaired.

FIG. 43 shows in detail the position of each line when displaying in the same image size at the time of system conversion from the 525/60 system to the 625/50 system. Indicates the line position of the even field and is interlaced, so both
They are arranged alternately.

FIG. 2A shows a state of conversion in the case where a field memory is used, and shows the same kind of field (odd number → odd number or even number → even number). There are portions where the vertical positional relationship is reversed, such as the z ″ and a ″ lines, and there are portions where the positions are shifted downward by approximately one line, such as the a ′ to a ″ lines.

FIG. 1B shows a state of conversion in the case where a field memory is used, and shows a field between different kinds of fields (odd number → even number or even number → odd number). Again,
Upside-down reversal is performed on the lines f ′ to e ″ to f ″, and the position is significantly shifted downward on the lines f ′ to f ″.

By the way, as is apparent from FIG. 42, one field overlap (n + 5 ″ in FIG. B) and thinning out (m + 5 in FIG. A) occur during conversion. Periodic transition with is inevitable.

Each field is interlaced in the order of a → c → e. However, since it is visible to the eyes continuously from a to k, the upper and lower lines are reversed as shown in FIGS. The displacement is recognized as a vertical figure distortion.

On the other hand, in FIG. 3C, since a conversion field is formed from two fields (one frame),
There is no reversal of the upper and lower lines and the positional deviation is suppressed to a maximum of 0.5 line, and the graphic distortion in the vertical direction is greatly improved.

Conventional TV system converters are mostly used for broadcasting and business use, and they do not like image quality deterioration. Therefore, the memory capacity per field is large and the TV system converter shown in FIG.
In order to convert the number of lines in one frame, a memory for one frame is required. Actually, in order to further improve the image quality, those having a memory of several frames are mainly used.

As is apparent from FIG. 42, the TV system converter must be able to simultaneously write (write) and read (read) this memory in order to immediately convert and output the input signal. In addition, since each data position changes sequentially with time, the above field memory (or frame memory) must have two asynchronous write / read ports. As a memory meeting this condition, a video memory (V-RAM) developed for such image processing is used, or an asynchronous operation is apparently performed by driving a large number of general-purpose memories by serial / parallel conversion. I had to do it.

The advantages and disadvantages of each conversion are summarized as follows. (A) Line / field conversion + color modulation system conversion Advantages: Complete TV system conversion capable of recording on a VTR or the like.

Disadvantages: A large-capacity memory capable of asynchronous write / read and guaranteeing image quality is required, which is expensive and complicated. (B) Conversion using only the color modulation method Advantages: Simple and inexpensive because only the chroma demodulation circuit is used.

Disadvantages: Recording on a VTR or the like is not possible because half of the circuit depends on the circuit of the TV receiver. Also,
The TV needs to be resynchronized vertically. Further, the screen is flattened vertically.

[0030]

As described above, the VTR
In order to perform the conversion of (a) so that recording to
There is a disadvantage that a large-capacity expensive dedicated video memory or a large amount of general-purpose memory is required.

Therefore, according to the present invention, a television system converter for performing line / field conversion is constructed inexpensively without using a large-capacity memory, and even if a large deviation occurs in the horizontal synchronization of an input video signal, the output screen is converted. In order to avoid the impact on

[0032]

SUMMARY OF THE INVENTION The present invention, which has a storage capacity of 1/2 horizontal period with respect to the horizontal direction, the first and second having a storage capacity of 1 vertical period with respect to vertical <br/> straight direction comprising a second memory, write the first half of one horizontal period of the data constituting the input video signal in the first half period of each horizontal period in the first memory Mutotomoni, from the first memory
One horizontal line constituting the output video signal in the latter half of each horizontal period
And by sea urchin control reading the first half of the period of data, structure of the input video signal to the second memory in the second half period of each horizontal period
Write Mutotomo write the second half of one horizontal period of the data to be formed
Output from the second memory during the first half of each horizontal period.
Is to assume a television standards converter for converting controlled to Suyo read out <br/> the first half of one horizontal period of data constituting a video signal, the number of lines and the number of fields.

When the system conversion is not performed, the horizontal synchronization and the vertical synchronization on the reading side of the memory are synchronized with the horizontal synchronization and the vertical synchronization on the writing side, respectively, near the vertical synchronization position on the writing side of the memory. In this case, the horizontal synchronization on the reading side is synchronized with the horizontal synchronization on the writing side near the vertical synchronization position on the reading side without synchronizing the vertical synchronization on the reading side with the vertical synchronization on the writing side.

When the format conversion is performed, the phase difference between the horizontal synchronization of the input video signal and the horizontal synchronization on the writing side is detected, and the image signal of the video signal written to the first and second memories is detected in accordance with the phase difference. It changes the frame.

Further, the phase difference is detected every predetermined period, and when the substantially same phase difference continues two or more times, the image frame is changed according to the phase difference.

[0036]

The number of lines and the number of fields are converted by controlling the first and second memories alternately in a writing state and a reading state every 1/2 horizontal period, so that an inexpensive general-purpose memory is used instead of an expensive video RAM. It can be configured only by using two memories (storage capacity for 0.5 fields).

When a large phase shift occurs in the horizontal synchronization of the input video signal, the influence is transmitted to the reading side during the vertical blanking period of the reading side, so that the appearance of skew on the output screen can be reduced. Can be avoided.

Further, since the picture frame of the video signal to be written in the first and second memories is changed according to the phase shift between the horizontal synchronization of the input video signal and the horizontal synchronization on the writing side, even if the phase shift becomes large, The alternate operation of writing and reading of the first and second memories will not fail.
In this case, by detecting the phase shift every predetermined period, the image frame can be prevented from deteriorating without frequently changing the image frame.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

In the figure, a luminance signal Y is supplied to an input terminal 1Y. This luminance signal Y is supplied to the adder 3 via the resistor 2. The wobbling clock WOB output from the write timing generator 4 is supplied to the adder 3 via the resistor 5. Then, the luminance signal Y to which the wobbling clock WOB output from the adder 3 has been added is supplied to the switch circuit 6.

A carrier color signal C ^* is supplied to the input terminal 1C. This color signal C ^* is supplied to the color demodulator 7. The red difference signal RY (V signal) and the blue difference signal BY (U signal) output from the color demodulator 7 are supplied to the switch circuit 6.

The luminance signal Y supplied to the input terminal 1Y is supplied to an AFC circuit 8 having a synchronization separation circuit and the like. A horizontal synchronization pulse PH (frequency fh) is supplied from the AFC circuit 8 to the timing generator 4 as a synchronization reference signal, and a clock, a latch pulse, a switching control signal, and the like are formed based on the synchronization signal PH.

The switch circuit 6 is supplied with the switching control signals SW1 and SW2 from the timing generator 4, and outputs the luminance signal Y
And the V signal and the U signal are combined. The composite signal output from the switch circuit 6 is supplied to an A / D converter 9. A /
The D converter 9 receives the clock CLK from the timing generator 4.
1 (frequency is 1100 fh) and the synthesized signal is 1
It is converted into a 6-bit sampled digital signal. In this case, conversion is performed after removing the synchronization signal to secure S / N.

FIG. 3 shows the switch circuit 6 and the A / D converter 9.

In the same figure, 6A and 6B are changeover switches constituting the switch circuit 6. The V signal is supplied to the v-side fixed terminal of the changeover switch 6A, and the U signal is supplied to its u-side fixed terminal. The changeover of the changeover switch 6A is performed based on the changeover control signal SW1, and the changeover switch 6A is connected to the v side and the u side in one horizontal period alternation. As a result, the color signal C which becomes the V signal and the U signal alternately is output from the changeover switch 6A every one horizontal period.

The color signal C output from the changeover switch 6A
(FIG. 4B) is supplied to a fixed terminal on the c side of the changeover switch 6B, and a luminance signal Y (A in FIG. 4A) is supplied to the fixed terminal on the y side.

The output signal of the changeover switch 6B is supplied to the A / D converter 9. In this A / D converter 9, 1/11
Clock CLK1 having the period of 00f h is converted into a digital signal with a (FIG E) (Fig F).

The output signal of the changeover switch 6B is supplied to the A / D converter 9. In this A / D converter 9, 1/11
The signal is converted into a digital signal by a clock CLK1 having a period of 00fh (FIG. E) (FIG. F).

Returning to FIG. 1, the output signal of the A / D converter 9 (FIG. 5A) is supplied to the latch circuit 10. The latch pulse P1 is supplied to the latch circuit 10 at the timing of each sample data of the luminance signal Y from the timing generator 4 (B in the figure), and the luminance signal Y is latched (C in the figure).

The luminance signal Y latched and output by the latch circuit 10 is supplied to a digital low-pass filter 11. The clock CLK1 is supplied from the timing generator 4 to the low-pass filter 11, and low-pass processing is performed. By this low-pass processing, a 7-bit luminance signal Y 'is output from the low-pass filter 11 (D in the figure).

The luminance signal Y 'output from the low-pass filter 11 is supplied to the latch circuit 12. A latch pulse P2 having a frequency of 275 fh is supplied from the timing generator 4 to the latch circuit 12 (E in the figure). Here, the phase of the latch pulse P2 is inverted every horizontal period. Therefore, the data rate from the latch circuit 12 is 275 fh
The luminance signal Y 'subjected to the line offset sub-sampling is output (FIG. 11F).

The output signal of the A / D converter 9 (FIG. 5)
A) is a parallel / serial converter (P / S converter) 13
Supplied to The latch pulse P3 is supplied to the P / S converter 13 from the timing generator 4 at the timing of the sample data of the color signal C having a period of 1/55 fh (G in the figure), and the color signal C is latched (see FIG. (Figure H). The P / S converter 13 further receives 275 fh from the timing generator 4.
Is supplied (I in the figure), and each bit data of the latched sample data is sequentially output (J in the figure). During this conversion, the lower one bit (C0) of the color signal C is truncated.

The luminance signal Y '(FIG. 6A) of parallel data (7 bits) output from the latch circuit 12 and P /
Color signal C of serial data output from S converter 13
(FIG. 2B) is supplied to the switch circuit 14 as 8-bit parallel data. In this case, the one-bit color signal C is located on the lower bit side of the luminance signal Y '.

The switch circuit 14 includes a timing generator 4
The switching control signal SW3 and the information data INF are supplied, and the information data INF is added to the head of the data in each horizontal period.

The output signal of the switch circuit 14 is supplied to the switch circuit 15. The switching control signal SW4 is supplied from the timing generator 4 to the switching circuit 15 (C in the figure). In the switch circuit 15, 8-bit parallel data is alternately selected and output as upper 4-bit data and lower 4-bit data at intervals of 1/550 fh (D in the figure).

As shown in FIG. 6D, the information data I
NF is composed of 4-bit data. Here, OX indicates whether the field is odd or even, UXV indicates whether the chrominance signal C of the line is a U signal or a V signal, and AXB indicates that the luminance signal Y 'of the line is a line offset sub. It indicates whether it is a sampling A pattern or a B pattern. In addition, LDEC indicates that the next line will be culled.

FIG. 7 shows the configuration of a luminance signal system from the input terminal 1Y to the low-pass filter 11.

In the figure, a luminance signal Y supplied to an input terminal 1Y is supplied to an adder 3 via a resistor 2.

In the timing generator 4, the clock CL
After K1 (1100fh) is inverted in phase by the inverter 4A, the frequency is divided by 2 by the frequency divider 4B. The output signal of the frequency divider 4B is supplied to the adder 3 via the resistor 5 as a wobbling clock WOB. In this case, the addition ratio of the luminance signal Y and the wobbling clock WOB in the adder 3 is determined by the resistance values of the resistors 2 and 5,
The amplitude (peak-to-peak value) of the wobbling clock WOB supplied to the adder 3 is set to be an odd multiple of a half step width of the 6-bit quantization step, in this example, one.

An addition signal of the luminance signal Y and the wobbling clock WOB from the adder 3 is supplied to an A / D converter 9 and converted into 6-bit digital data Xn. In this case, the clock C is supplied to the A / D converter 9 as described above.
LK1 (1100fh) is supplied as a conversion clock (sampling clock).

When the wobbling clock WOB is formed as described above, the change point (rising edge and falling edge) of the wobbling clock WOB does not match the sampling point because the phase of the clock CLK1 is inverted by the inverter 4A. It has been like that.

The 6-bit digital data Xn output from the A / D converter 9 is supplied to a digital adder 11A constituting the low-pass filter 11 and to a data terminal D of a D flip-flop 11B. D
The clock CLK1 (110
0fh). From the D flip-flop 11B, the digital data Xn is output for one clock period (1/1).
Digital data Xn-1 delayed by 100 fh) is obtained, and this digital data Xn-1 is supplied to the adder 11A.

In the adder 11A, the digital data Xn and Xn-1 are added and the 7-bit digital data Yn is added.
And the digital data Yn is used as the output Y 'of the low-pass filter 11.

In this case, the adder 11A and the D flip-flop 11B constitute a low-pass filter having a cutoff frequency of substantially half the frequency of the clock CLK1. Therefore, the wobbling clock WOB added by the adder 3 is automatically removed by the low-pass filter 11 and does not appear in the digital data Yn.

Here, how the digital data Yn is formed will be described.

FIG. 8 shows a state of quantization in a normal A / D converter. As is apparent from this figure, in the ordinary A / D converter, the number of bits is changed from 6 bits (broken line) to 7 bits.
As the number of bits increases (indicated by a dashed line), the luminance signal approaches the input luminance signal Y (solid line), and good results can be obtained. This is because the 7-bit quantization step (Ln and Mn) is finer than the 6-bit quantization step (Ln).

In this example, the luminance signal Y
(Shown by a broken line in FIG. 9A) is added with a wobbling clock WOB, and a signal (Y + WO) supplied to the A / D converter 9 is added.
B) is repeatedly shifted with a half step width of the 6-bit quantization step (shown by a solid line in the figure). Therefore, the digital data Xn output from the A / D converter 9 is arranged as indicated by "." Points in FIG.

In the D flip-flop 11B, the digital data Xn is delayed by one clock of the clock CLK1, so that the digital data Xn-1 is arranged as shown by the "○" point in FIG. 9B. Therefore, the 7-bit digital data Yn output from the adder 11A
Are arranged as indicated by "x" points in FIG.

After all, 7-bit digital data Yn
Gives the same result as the quantization by the 7-bit A / D converter (see the dashed line in FIG. 8).

Returning to FIG. 1, 4-bit digital data DW output from the switch circuit 15 is supplied to the movable terminal of the changeover switch 21 as a write signal to the memory. The fixed terminals on the a and b sides of the changeover switch 21 are connected to the fixed terminals on the a and b sides of the changeover switch 22, respectively.

The connection point between the fixed terminals on the a side of the changeover switches 21 and 22 is connected to the memory 23A, and the connection point between the fixed terminals on the b side of the changeover switches 21 and 22 is stored in the memory 23A.
B.

The AFC circuit 8 writes the horizontal write start signal WHS to the memory write timing generator 24.
And the write vertical start signal WVS
Is supplied. The timing generator 24 writes the write address signal WAD based on the start signals WHS and WVS.
The address signal WAD is applied to the switch circuit 2
5 is supplied to the memory 23A or 23B.

Further, the AFC circuit 8 supplies the synchronization generator 26
Is supplied with a signal HMDP output at an intermediate position of each horizontal period. Then, the synchronization generator 26 reads the horizontal start signal RH from the memory read timing generator 27.
S is supplied and the read vertical start signal RV
S is supplied. The timing generator 27 reads the read address signal RA based on the start signals RHS and RVS.
D is formed, and the address signal RAD is supplied to the memory 23B or 23A via the switch circuit 25.

The changeover switches 21 and 22 are supplied with a changeover control signal SW5 from the timing generator 24. The changeover switch 21 is connected to the a side during the first half of each horizontal period, and is connected to the b side during the latter half of each horizontal period. On the other hand, the changeover switch 22 is connected to the b side during the first half of each horizontal period,
After that, it is connected to the a side for a half period.

The switching control signal SW5 is also supplied from the timing generator 24 to the switch circuit 25. Thus, in the first half of each horizontal period, the write address signal WAD is supplied to the memory 23A and the memory 23B
Is supplied with a read address signal RAD. On the other hand, in the latter half of each horizontal period, the write address signal WAD is supplied to the memory 23B and the read address signal RAD is supplied to the memory 23A.

The memories 23A and 23B have a storage capacity for a half horizontal period in the horizontal direction, and a storage capacity for one vertical period in the vertical direction. Memory 2
The first half of each horizontal period is written in 3A, and the first half of each horizontal period is read from the memory 23A. The latter half of each horizontal period is written into the memory 23B, and the latter half of the horizontal period is read out from the memory 23B.

Here, the conversion of the number of lines and the number of fields is realized by controlling the write address signal WAD and the read address signal RAD to the memories 23A and 23B.

That is, the NTSC system (525/60
When converting data from the PAL system to the PAL system (625/50 system) (see FIGS . 41A and 42A), at the time of reading, data is thinned out at a rate of one field to six fields, and at the rate of one line to five lines in each field. Read the same line twice.

Conversely, when converting from the PAL system to the NTSC system (see FIG. 41B and FIG.
One line is thinned out for one line, and the same field is repeatedly read out at a rate of one field for every five fields at the time of reading . Your name, memory 23A, 23
The storage capacity of B is 262 or 263 of the 525/60 system.
Line is the basis. When fetching 312 or 313 lines of the 625/50 system, they are compressed and expanded in the vertical direction.

Most of the horizontal and vertical blanking periods not directly related to the screen are not stored in the memories 23A and 23B. As a result, the storage capacity of the memories 23A and 23B is only 84% of the effective screen with respect to the entire screen.

As described above, the memory capacity required in this example is as follows, and the memories 23A and 23
B can be configured using, for example, a general-purpose 256-Kbit DRAM.

{(7 × 275) + (5 × 55)} × 263 × 0.84 = 486 Kbits By the way, the cycle time of a general-purpose 256 Kbit DRAM is determined by designating the row and column address strobes, and It takes 200 nsec or more to complete writing or reading. This cycle time is longer than the data cycle (1 / 550fh) of the write data DW output from the switch circuit 15, and writing and reading in real time becomes impossible.

Therefore, in this example, a write cycle and a read cycle system called a page mode are employed in writing and reading data.

That is, in the normal write mode, FIG.
As shown in FIG. 0A, since both the row address strobe and the column address strobe are specified, the cycle time required from the specification of these to the writing of the data DW is 200 nsec.

On the other hand, in the write mode in the page mode, as shown in FIG. B, a row address strobe and a column address strobe are designated only for the first cell of each horizontal line, and for the subsequent cells. Since only the column address stove needs to be specified, 2
The cycle time for the subsequent cells is 100 nsec.

In FIG. 10, RAS bar is a row address strobe pulse, CAS bar is a column address strobe pulse, WAD is a write address signal,
DW is write data.

The same applies to the read mode. FIG. 11A shows the timing in the normal read mode, and FIG. 11B shows the timing relationship in the page mode.
In FIG. 11, RAS represents a row address strobe pulse, CAS represents a column address strobe pulse, RAD represents a read address signal, and DR represents read data.

According to the page mode, the cycle time is determined by the data cycle (1 / 550f) of the write data DW.
h), the use of the above-mentioned general-purpose DRAM becomes possible.

Returning to FIGS. 1 and 2, the read data DR output from the changeover switch 22 is
1 is supplied. The horizontal synchronization pulse PH ′ is supplied from the synchronization generator 26 to the read timing generator 32. The switching control signal SW6, the latch pulses P4 to P6, and the control signal CNP are supplied from the timing generator 32 to the demultiplexer 31. From the demultiplexer 31,
The information data INF, the luminance signal Y 'and the color signal C separated from the output signal of the changeover switch 22 are output.

FIG. 12 is a diagram showing a specific configuration of the demultiplexer 31. As shown in FIG. In the figure, read data DR (FIG. 13A) output from the changeover switch 22 is supplied to the movable terminal of the changeover switch 31A. Selector switch 31
A is supplied with the switching control signal SW6, and is connected to the a side corresponding to the period of the information data INF added to the head of each horizontal period, and is connected to the b side in other periods. Information data INF is obtained at the fixed terminal on the a side of the changeover switch 31A.

The signal obtained at the fixed terminal on the b side of the changeover switch 31A is applied to the data terminals D of the latch circuits 31B and 31C.
Supplied to Latch pulse P4 is supplied to latch circuit 31B at the timing of 4-bit data Y6 'to Y3' (FIG. 13B), and 4-bit data Y6 'to Y3' are output from latch circuit 31B at a data rate of 275 fh. (Fig. C). A latch pulse P5 is supplied to the latch circuit 31C at the timing of the 4-bit data Y2 'to Y0' and C (any of C5 to C1) (FIG. D), and the 4-bit data Y2 'is output from the latch circuit 31C. ~ Y0 ', C (C
5 to C1) is output at a data rate of 275 fh (E in the same figure).

The 4-bit data Y6 'to Y3' output from the latch circuit 31B and the 3-bit data Y2 'to Y0' output from the latch circuit 31C are applied to the latch circuit 31.
D is supplied to the data terminal D. 1-bit data C output from the latch circuit 31C (any of C5 to C1)
Is supplied to the data terminal D of the latch circuit 31E.

The latch circuits 31D and 31E have 275f
The latch pulse P6 having the frequency h is supplied (FIG. F). As a result, 275fh is output from the latch circuit 31D.
A 7-bit luminance signal Y 'is output at the data rate (G in the figure), and a 5-bit color signal C (data rate is 55 fh) is output from the latch circuit 31E as serial data (H in the figure).

The luminance signal Y 'output from the latch circuit 31D is output via the phase adjuster 31F. The control signal CNP is supplied to the phase adjuster 31F based on the data AXB included in the information data INF, and the phase adjustment of the sample data of the luminance signal Y 'in each horizontal period is performed. As a result, the data of each line of the luminance signal Y 'is output while maintaining the phase relationship of the line offset.

Returning to FIG. 2, information data INF output from demultiplexer 31 is supplied to synchronization generator 26 and timing generator 32.

The luminance signal Y 'output from the demultiplexer 31 is supplied to the filter circuit 33 and also to the fixed terminal on the a side of the changeover switch 34. The changeover switch 34 is supplied with a changeover control signal SW7 from the timing generator 32. The output signal of the changeover switch 34 is 1
It is supplied to a delay circuit 35 having a delay time of a horizontal period. The output signal of the delay circuit 35 is supplied to the filter circuit 33 and also to the fixed terminal on the b side of the changeover switch 34. The filter circuit 33 includes a timing generator 32
Then, the switching control signal SW8 is supplied.

FIG. 14 shows a specific configuration of the filter circuit 33, the changeover switch 34, and the delay circuit 35, and is a processing circuit for the line offset sub-sampled luminance signal Y '.

Here, a signal of a line sampled at a certain phase is defined as a line signal of an A pattern, and a signal of a line sampled at an inverted phase thereof is defined as a line signal of a B pattern. These patterns are identified by the data AXB included in the information data INF as described above.

In the figure, an input signal Sin (luminance signal Y ') is supplied to a high-pass filter 33A constituting a filter circuit 33. The high-frequency component SH of the signal Sin extracted by the high-pass filter 33A is subtracted by a subtracter 33B It is supplied to the fixed terminal on the a side of the changeover switch 33C.

The input signal Sin is supplied to a subtracter 33B via a delay circuit 33D for time adjustment. The delay time of the delay circuit 33D is set to be equal to the delay amount in the high-pass filter 33A.

In the subtracter 33B, the high-frequency component SH extracted by the high-pass filter 33A is subtracted from the video signal Sin output from the delay circuit 33D, and the low-frequency component SL of the signal Sin is subtracted.
Is output.

The input signal Sin is supplied to the fixed terminal on the a side of the changeover switch 34. The output signal of the changeover switch 34 is supplied to the delay circuit 35, and the output signal of the delay circuit 35 is changed to the b side of the changeover switch 34. Is supplied to the fixed terminal of The changeover of the changeover switch 34 is performed by the changeover control signal SW7.
It is performed based on. That is, the changeover switch 34
When two or more line signals of the pattern A or pattern B are continuously supplied as the input signal Sin,
Each horizontal period from the first line of the continuous line to the line immediately before the last line is connected to the b side, and the other horizontal periods are connected to the a side.

Here, the line signal of the pattern A or the pattern B is continuous for two or more lines in some cases when the number of lines is increased by reading twice in line number conversion or the number of lines is reduced by thinning out. In this example, when the signals of the 625/50 system are taken into the memories 23A and 23B, compression / expansion processing in the vertical direction is performed due to the storage capacity. Even in this compression / expansion processing, two or more lines of the same pattern signal continue. Sometimes.

It is to be noted that whether or not the same pattern is continuous for two or more lines is determined by the data AXB included in the information data INF separated by the demultiplexer 31.

The signal Sin ′ one horizontal period before output from the delay circuit 35 is supplied to the high-pass filter 33E, and the high-frequency component S extracted by the high-pass filter 33E is output.
H 'is supplied to the fixed terminal on the b side of the changeover switch 33C. The high-frequency component SH2 selected and output by the changeover switch 33C is supplied to the adder 33F.

The changeover switch 33C is set to 1 based on the changeover control signal SW8 supplied from the timing generator 32.
Switching to the a-side and the b-side alternately at a change of / 2 sampling period. In this case, the high-pass filter 33
Connected to the a side corresponding to the sampling timing of the high frequency component SH output from A. The sampling timing of the high frequency component SH is determined by the data AXB included in the information data INF separated by the demultiplexer 31.

The low frequency component SL of the signal Sin output from the subtractor 33B is supplied to the adder 33G and also to the fixed terminal on the a side of the changeover switch 33H.

The high-frequency component SH 'of the signal Sin' output from the high-pass filter 33E is supplied to a subtractor 33I.
The signal Sin 'output from the delay circuit 35 is supplied to the subtracter 33I via a time adjustment delay circuit 33J. The delay time of the delay circuit 33J is
It is set to be equal to the delay amount in 3E.

The subtractor 33I subtracts the high-frequency component SH 'output from the high-pass filter 33E from the signal Sin' output from the delay circuit 33J. The low-pass component SL 'of the signal Sin' is output from the subtractor 33I, and the low-pass component SL 'is supplied to the adder 33G.

In the adder 33G, the video signals Sin and Si
The low-pass components SL and SL 'of n' are added and averaged, and the output signal (SL + SL ') / 2 is supplied to the fixed terminal on the b side of the changeover switch 33H.

The low-frequency component selected by the changeover switch 33H is supplied to the adder 33F, and is added to the high-frequency component SH 'selected by the changeover switch 33C. And adder 3
The output signal of 3F is the output signal Sout of the filter circuit 33.
(Y ″).

In the above configuration, first, the changeover switch 3
The case where 3H is connected to the a side will be described. Signal S
When the line signals of the A pattern and the B pattern are alternately supplied as in (see FIG. 15), the following is performed.

When the signal Sin is an n-1 line signal, the signal Sin 'output from the delay circuit 35 is an n-2 line signal. From the changeover switch 33C, n-1
A high-frequency component SH2 in which the high-frequency component SH of the signal of the line and the high-frequency component SH 'of the signal of the n-2 line are alternately selected in a 1/2 sampling cycle is output. The signal Sout on the output line is an addition signal of the high-frequency component SH2 and the low-frequency component SL of the signal on the (n-1) th line (see FIG. 16A). When the signal Sin is an n-line signal, the signal Sin 'output from the delay circuit 35 is an (n-1) -th line signal. From the changeover switch 33C, the high frequency component S of the signal of the nth line is output.
A high-frequency component SH2 in which H and the high-frequency component SH 'of the signal of the (n-1) -th line are alternately selected at a 1/2 sampling period is output. The signal Sout on the output line is an addition signal of the high-frequency component SH2 and the low-frequency component SL of the n-line signal (see FIG. 16B).

As described above, the high-frequency component SH2 included in the signal Sout is sampled at a sampling period of substantially 1/2, and the high-frequency component is improved.

When line signals of the same pattern are successively supplied as the signal Sin (see FIG. 17), the following occurs.

For example, as shown in FIG. 17, when the (n-1) -th line and the n-th line are continuous to form a B-pattern line signal, the (n-1) -th line and the n-th line have the same pattern of line signals. Therefore, during the horizontal period in which the signal of the (n-1) th line is supplied, the changeover switch 34 is connected to the b side. For this reason, the delay circuit 35 outputs n-
Two lines of signals are output continuously.

Therefore, the signal Sin is n−2 to n +
When signals of two lines are supplied (see FIG. 17), signals of lines n-3 to n-1 are output from the delay circuit 35 as signal Sin '(see FIG. 18), and signals Sin and Sin in each horizontal period are output. The line signal patterns of Sin 'are different from each other.

Therefore, the sampling timings of the high-frequency components SH and SH 'output from the high-pass filters 33A and 33E always alternate, and the changeover switch 33
From C, a high-frequency component SH2 sampled at a substantially 1/2 sampling period is obtained.

When the signal Sin is an n-1 line signal (B pattern), the signal Si output from the delay circuit 35
n 'is a signal of the (n-2) th line (A pattern). From the changeover switch 33C, the high frequency component SH2 in which the high frequency component SH of the signal of the n-1 line and the high frequency component SH 'of the signal of the n-2 line are alternately selected at a 1/2 sampling period.
Is output. The signal Sout on the output line is a signal obtained by adding the high-frequency component SH2 and the low-frequency component SL of the signal on the (n-1) th line (see FIG. 19A).

The signal Sin is an n-line signal (pattern B)
, The signal Sin 'output from the delay circuit 35
Is a signal of the n-2 line (A pattern). From the changeover switch 33C, the high frequency components SH and n
A high-frequency component SH2 is output in which the high-frequency component SH 'of the -2 line signal is alternately selected at a 1/2 sampling period. The signal Sout of the output line is the high-frequency component SH2
And a signal obtained by adding the low-frequency component SL of the n-line signal (see FIG. 19B).

As described above, even when line signals of the same pattern are continuously supplied as the signal Sin, the changeover switch 33C outputs the high-frequency component SH2 sampled at a substantially 1/2 sampling cycle. , An improved signal Sout in a high frequency range can be obtained.

Next, the case where the changeover switch 33H is connected to the b side will be described. The high-frequency component is the same as that in the case where the changeover switch 33H is connected to the a-side, and a description thereof will be omitted.

As for the low-frequency components, the low-frequency components SL and SL 'of the signals Sin and Sin' are averaged by the adder 33G, and the averaged low-frequency component (SL + SL ') / 2
Is supplied to the adder 33F via the b side of the changeover switch 33H.

Therefore, the signal Sout output from the adder 33F is the sum of the low-frequency component (SL + SL ') / 2 and the high-frequency component SH2.

When the signal Sin is an n-1 line signal, the signal Sin 'output from the delay circuit 35 is an n-2 line signal. From the changeover switch 33C, n-1
A high-frequency component SH2 in which the high-frequency component SH of the signal of the line and the high-frequency component SH 'of the n-2 line are alternately selected in a 1/2 sampling cycle is output. Also, the adder 33F
Output a low-frequency component (SL + SL ') / 2 obtained by averaging the low-frequency component SL of the signal of the n-1 line and the low-frequency component SL' of the signal of the n-2 line. Output signal Sout
Is a signal obtained by adding the high-frequency component SH2 and the low-frequency component (SL + SL ') / 2 (see FIG. 20A).

When the signal Sin is an n-line signal, the signal Sin 'output from the delay circuit 35 is an n-2 line signal. From the changeover switch 33C, the high-frequency component SH of the signal of the n-th line and the high-frequency component SH 'of the n-2th line are set to 1
The high-frequency component SH2 selected alternately at the / 2 sampling period is output. The adder 33F outputs a low-frequency component (SL + SL ') obtained by averaging the low-frequency component SL of the n-th line signal and the low-frequency component SL' of the n-2th line signal.
/ 2 is output. The output signal Sout is the high-frequency component SH
2 and a low-frequency component (SL + SL ') / 2 are added (see FIG. 20B).

As described above, the high frequency component of the output signal Sout is SH
Since it is 2, the high-frequency component is improved, and the low-frequency component is (SL + SL ') / 2, and the signal is averaged in the vertical direction to reduce the jaggedness.

Note that, by averaging the signals in the vertical direction, the resolution in the vertical direction generally deteriorates. Therefore, in the example shown in FIG. 14, the changeover switch 33 is used only when the jaggedness is a problem due to the increase in the number of lines due to double reading.
H is connected to the b side, which is effective.

Returning to FIG. 2, the luminance signal Y ″ of 8-bit parallel data output from the filter circuit 33 is supplied to the fixed terminal on the a side of the changeover switch 36. Reference numeral 37 denotes a pedestal level and synchronization level signal. The signal generator 37 is supplied with a timing signal ST1 for generating each signal from the synchronization generator 26. The output signal of the signal generator 37 is a changeover switch 36.
Is supplied to the fixed terminal on the b side.

The changeover switch 36 is supplied with a changeover control signal SW9 from the synchronization generator 26. The switch 36 is connected to the b side during the period of the synchronization signal and the pedestal signal, and is connected to the a side during the other periods. Therefore, the changeover switch 36 outputs an added luminance signal such as a synchronization signal.

The luminance signal output from the changeover switch 36 is converted into an analog signal by a D / A converter 38, band-limited by a low-pass filter 39, and supplied to an adder 40.

The color signal C of 1-bit serial data separated by the demultiplexer 31 is supplied to a serial / parallel converter (S / P converter) 41. A clock CLK3 synchronized with each bit data of the color signal C is supplied from the timing generator 32 to the S / P converter 41, and a latch pulse P7 is supplied at a timing of every five bits (C5 to C1).

The color signal C converted into 5-bit parallel data by the S / P converter 41 is supplied to fixed terminals on the a side of the changeover switches 42 and 43, and the changeover switch 44
Is supplied to the fixed terminal on the b side.

The output signal of the changeover switch 42 is supplied to a delay circuit 45 having a delay time of one horizontal period, and the output signal of the delay circuit 45 is supplied to the fixed terminal on the b side of the changeover switch 42. The changeover switch 42 is supplied with a changeover control signal SW10 from the timing generator 32.

As described above, the color signal C before conversion of the number of lines by writing and reading to and from the memories 23A and 23B is a line-sequential signal that becomes a V signal and a U signal every one horizontal period. After the color signal C has been thinned out or read twice, two lines of the same color are periodically continuous.

The changeover switch 42 has a changeover control signal SW10
Are connected to the b-side during the period of the first two consecutive lines, and to the a-side during the other periods. The switching control signal SW10 is formed based on the data LDEC included in the information data INF separated by the demultiplexer 31 when lines are thinned out at the time of writing, and when the same line is read twice at the time of reading. , Based on the information.

The output signal of the delay circuit 45 is
3 and to the fixed terminal on the a side of the changeover switch 44. Changeover switch 4
Switching control signals S from the timing generator 32
W11 is supplied. The changeover switches 43 and 44 are set to S /
One horizontal period in which the color signal C from the P converter 41 is a U signal is connected to the side a, and conversely, one horizontal period in which the color signal C is a V signal is connected to the side b. The switching control signal SW11 is formed based on the data UXV included in the information data INF separated by the demultiplexer 31.

Here, a case where the same line is read twice at a ratio of one line to five lines to increase the number of lines will be described. At this time, the S / P converter 41 periodically changes the line of the same color to two as shown in FIG. 21A.
A line continuous color signal C is output.

At this time, the switching control signals SW10, SW1
1 are formed as shown in FIGS. As a result, the output signal of the delay circuit 45 becomes as shown in FIG. D, and the U and V signals synchronized with each other are obtained from the changeover switches 43 and 44 (shown in FIGS. E and F).

Although the description is omitted, the number of lines is reduced by thinning out one line for every six lines.
Similarly, when the S / P converter 41 outputs a color signal C in which two lines of the same color are successively output from the S / P converter 41, the changeover switches 43 and 44 similarly output the synchronized U signal and V signal respectively. A signal is obtained.

The U signal output from the changeover switch 43 is supplied to the fixed terminal on the a side of the changeover switch 46. 47
Is a signal generator for generating burst level and blanking level signals. The signal generator 47 is supplied with a timing signal ST2 for generating respective signals from the synchronization generator 26. The output signal of the signal generator 47 is supplied to a fixed terminal on the b side of the changeover switch 46.

Also, the V output from the changeover switch 44
The signal is supplied to the fixed terminal on the a side of the changeover switch 48. Reference numeral 49 denotes a signal generator for generating a signal of a burst level and a signal of a blanking level. The signal generator 49 is supplied with a timing signal ST2 for generating respective signals from the synchronization generator 26. The output signal of the signal generator 49 is supplied to a fixed terminal on the b side of the changeover switch 48.

The synchronizing generator 2 is connected to the changeover switches 46 and 48.
6 supplies a switching control signal SW12. The changeover switches 46 and 48 are connected to the b side during the burst period and the blanking period, and are connected to the a side during the other periods. Thus, the changeover switches 46 and 48 output the added U signal and V signal such as the burst level signal.

U output from changeover switches 46 and 48
The signal and the V signal are supplied to the color modulator 50. Color modulator 5
At 0, a 4.43 MHz chrominance subcarrier is used when converting from NTSC to PAL, while a 3.58 MHz chrominance subcarrier is used when converting from PAL to NTSC.

The carrier color signal of 6-bit parallel data output from the color modulator 50 is converted into an analog signal by the D / A converter 51, and then supplied to the adder 40 via the band-pass filter 52. . Then, the adder 40 adds the luminance signal and the carrier chrominance signal, and the output terminal 53 derives a format-converted video signal SV.

In the present embodiment, the number of lines and the number of fields are converted by controlling the memories 23A and 23B alternately in the writing state and the reading state every 1/2 horizontal period. Therefore, a general-purpose 256-Kbit DRAM can be used as each of the memories 23A and 23B, and a system converter that also performs line / field conversion can be configured at low cost.

In this embodiment, the line offset subsampling process is performed on the luminance signal Y 'on the writing side to reduce the data rate and save the capacity of the memories 23A and 23B.
Using the delay circuit 35 and the filter circuit 33, the high-frequency components of the current line and the signal immediately before the previous line are alternately selected at a サ ン プ リ ン グ sampling period to improve the high frequency. Even when line signals of the same pattern are continued by the reading, the first and second patterns are alternately selected, so that high-frequency improvement can be performed satisfactorily.

Further, in this example, the memories 23A, 2A
In order to save the capacity of 3B, the U signal and the V signal are line-sequentially written and read, and are synchronized on the read side using the changeover switches 42 to 44 and the delay circuit 45. Even when line signals of the same color continue due to thinning or double reading, synchronization can be favorably performed.

Next, the synchronous system on the write side and the read side of the memories 23A and 23B will be described in detail with reference to FIGS. The synchronization system on the writing side is A
The synchronization system on the reading side is configured in a synchronization generator 26 (see FIGS. 1 and 2).

In FIG. 22, a composite synchronizing signal CSYNC supplied to an input terminal 61 is supplied to a falling edge detector 63 via a buffer 62. Edge detector 6
3 is supplied to the input side of the connection switch 64.

The synchronization pulse CSYNCP obtained at the output of the connection switch 64 is supplied to the input of the OR gate 65. The output signal of the OR gate 65 is supplied to a load terminal LO of a 10-bit binary up counter (write-side horizontal counter) 66. The load data of the counter 66 is set to “1 DAH”. Here, "H" indicates a hexadecimal number, and the same applies to the following.

The clock terminal CK of the counter 66 has 1
A system clock CLK having a frequency of 100 fh is supplied. 1 obtained at the terminals Q9 to Q0 of the counter 66
The 0-bit count data is converted to an 11-bit decoder 67.
Is supplied to the data terminal D.

The synchronization pulse CSYNCP obtained at the output of the connection switch 64 is supplied to the input of the OR gate 68. The output signal of the OR gate 68 is the inverter 6
9 is supplied to the data terminal D of the D flip-flop 70. The signal S1 obtained at the Q terminal of the flip-flop 70 is supplied to the input side of the OR gate 68,
The data is supplied to the data terminal D of the decoder 67 in parallel with the 10-bit count data of the counter 66 described above.

From the decoder 67, the signal S1 is "1",
Regardless of the value of “0”, the count data is “3FF
When the signal S1 becomes "H", a signal S2 which becomes "1" is outputted. When the signal S1 becomes "1" and the count data becomes "34FH", a write horizontal start signal WHS which becomes "1" is outputted. If the count data is "3"
When it becomes "FFH", a signal HMDP which becomes "1" is output. Here, "1" and "0" indicate logical levels, and the same applies to the following.

The signal S output from the decoder 67
2 is supplied to the input side of the OR gates 65 and 72 via the connection switch 71. The synchronization pulse CSYNCP obtained at the output side of the connection switch 64 is supplied to the flip-flop 73 and has a pulse width (period of “1”) corresponding to two clocks of the system clock CLK (frequency of 1100 fh). It is supplied to the connection switch 71 as an on / off control signal. The connection switch 71 is turned off during a pulse width period of two clocks, and turned on during the other periods.

The synchronization pulse CSYNCP obtained at the output side of the connection switch 64 is supplied to the input side of the OR gate 72 via the connection switch 74. The connection switch 74 includes a signal S1 obtained at the Q terminal of the flip-flop 70.
Is supplied as an on / off control signal. Connection switch 7
4 is turned off when the signal S1 is “0” and “1”
When it is, it is turned on. The output signal of the OR gate 72 is supplied to the enable input terminal EN of the flip-flop 70. The flip-flop 70 transmits the data of the input D terminal to the output terminal in synchronization with the system clock CLK only during the period when the enable input terminal is “1”.

The composite synchronizing signal CSYNC supplied to the input terminal 61 is supplied to an integrator 75. Integrator 75
Is supplied to the rising edge detector 77 via the buffer 76. When the integration output exceeds the threshold value Vth, the edge detector 77 outputs a vertical synchronization pulse VP. This synchronization pulse VP is supplied to a load terminal L of a 4-bit binary up counter (write-side vertical counter) 78.
O is supplied. The load data of the counter 78 is “3
H ”. The signal obtained at the Q8 terminal of the counter 66 is supplied to the enable input terminal EN of the counter 78 via the falling edge detector 79. Counter 78
Counts up by the system clock CLK only when the enable input terminal EN is "1". Since the output of the edge detector 79 is only within one clock, the count is incremented by one each time the edge pulse of the Q8 terminal comes.

4 obtained at the Q3 to Q0 terminals of the counter 78
The bit count data is supplied to the data terminal D of the 4-bit decoder 80. The decoder 80 outputs a signal S3 which becomes "1" when the count data becomes "AH" and "BH".
When it becomes "H", a signal S4 which becomes "1" is output.

The signal S3 output from the decoder 80 is supplied to the connection switch 64 as an on / off control signal.
The connection switch 64 is turned on during a period when the signal S3 is “1”, and is turned off during other periods. That is, the connection switch 64 sets the count data of the counter 78 to “A
H "and" BH ", and is turned on for only about one horizontal period in a period during which there is no serration pulse or equivalent pulse in the vertical synchronization period.

The signal S4 output from the decoder 80 is supplied to the input side of the AND gate 81. AND Gate 8
1 is also supplied with the output signal of the OR gate 72. The output signal of the AND gate 81 is the write vertical start signal WV
Output as S.

In FIG. 23, the signal HMDP output from the decoder 67 is supplied to the input side of the OR gate 82. The output signal of the OR gate 82 is supplied to a load terminal LO of a 10-bit binary up counter (read-out horizontal counter) 83. The load data of the counter 83 is set to “1 DAH”. The clock terminal CK of the counter 83 is supplied with the system clock CLK.

1 obtained at the terminals Q9 to Q0 of the counter 83
When the 0-bit count data becomes “3FFH”,
A carry signal of "1" is output from the CO terminal of the counter 83. The carry signal is supplied to the input side of the OR gate 82 and is also supplied to the input side of the OR gate 88.

The signal HMDP is supplied to the input side of the OR gate 85. The output signal of the OR gate 85 is supplied to the data terminal D1 of the D flip-flop 87 via the inverter 86. The signal S5 obtained at the Q1 terminal of the flip-flop 87 is supplied to the input side of the OR gate 85, and is also supplied to the data terminal D of the decoder 84 in parallel with the count data of the counter 83. Decoder 84
, The signal S5 is "1" and the count data is "369".
The read horizontal start signal RHS which becomes "1" when it becomes "H" is output.

The signal HMDP is supplied to the input side of the OR gate 88 via the connection switch 89. The connection switch 89 is supplied with a signal S5 obtained at the Q1 terminal of the flip-flop 87 as an on / off control signal. The connection switch 89 is turned off when the signal S5 is "0" and turned on when the signal S5 is "1".

The output signal of the OR gate 88 is supplied to the enable input terminal EN of the flip-flop 87 and a 10-bit binary up counter (reading vertical counter) 90.
Of the OR gate 92 via the connection switch 91. The output signal of the OR gate 92 is supplied to the load terminal LO of the counter 90.

The select terminal SEL of the counter 90 has
The read control signal R525 is supplied from the input terminal 95. The read control signal R525 is supplied to the 525/60 system (N
It is set to "1" at the time of output of the TSC system, and is set to "0" at the time of output of the 625/50 system (PAL system). The load data of the counter 90 is set to "1F3H" when the read control signal R525 is "1", and is set to "18FH" when the read control signal R525 is "0".

1 obtained at the terminals Q9 to Q0 of the counter 90
When the 0-bit count data becomes “3FFH”,
A carry signal is output to the CO terminal of the counter 90,
This carry signal is supplied to the data terminal D2 of the flip-flop 87. The signal obtained at the Q2 terminal of the flip-flop 87 is supplied to the input side of the OR gate 92 via the rising edge detector 94.

The count data of the counter 90 is supplied to the data terminal D of the 10-bit decoder 93. The decoder 93 outputs a signal S6 which becomes "1" when the count data becomes "3E6H" and "3E7H", and outputs a read vertical start signal RVS which becomes "1" when the count data becomes "3FFH". Is done.

The signal S6 output from the decoder 93 is supplied to the connection switch 91 as an on / off control signal.
The connection switch 91 is turned on when the signal S6 is "1", and is turned off when the signal S6 is "0".

The control of the flip-flops 70 and 87 and the binary up-counters 78 and 90 enables the input terminal E
N is performed in order to operate them completely in synchronization with the system clock CLK. Thus, there is almost no need to consider the influence of the propagation delay time of elements such as gates. This is the basic technique of LSI design.

In the above configuration, the operation of the horizontal synchronization system will be described first.

A composite synchronizing signal CSY as shown in FIG. 24B
It is assumed that NC is supplied to the input terminal 61 and the edge detector 63 outputs a synchronization pulse CSYNCP as shown in FIG. Then, the connection switch 64 is turned on when the synchronization pulse CSYNCP is at the time t1, based on the signal S3 output from the decoder 80, as will be described later.
It is assumed that the control is turned off at the time point 2. FIG. 2A shows the system clock CLK.

The synchronization pulse CSYNCP at the time t1 is supplied to the load terminal LO of the counter 66 via the connection switch 64 and the OR gate 65 (FIG. D), and the counter 66 is loaded with data of "1 DAH" (FIG. E).

The synchronization pulse CSYNC at time t1
P is supplied to the OR gate 68 via the connection switch 64, and a signal of "0" is supplied to the data terminal D of the flip-flop 70 (H in FIG. 7).
Since the SYNCP is supplied to the enable input terminal EN of the flip-flop 70 via the connection switches 64 and 74 and the OR gate 72 (I in the figure), the flip-flop 70 is loaded when the counter 66 is loaded with the data of “1 DAH”. The signal S1 obtained at the Q terminal is “0” (J in the same figure).

The counter 66 is sequentially incremented by the system clock CLK (E in the figure). After 550 counts, the count data of the counter 66 becomes “3FF
When it becomes "H", the output signal S2 of the decoder 67 becomes "1" (G in the figure). Since this signal S2 is supplied to the load terminal LO of the counter 66 via the OR gate 65, the data of "1 DAH" is loaded into the counter 66 (E in the figure).

Since this signal S2 is supplied to the enable input terminal EN of the flip-flop 70 via the OR gate 72 (I in FIG. 17), the counter 66 outputs "1 DA".
At the point when the data of "H" is loaded, the signal S1 obtained at the Q terminal of the flip-flop 70 becomes "1" (J in the figure).

In the same manner, the counter 66 sets “1DAH” to “3F” in the first half and the second half of each horizontal period, respectively.
FH "is repeated (E in the same figure) and the signal S obtained at the Q terminal of the flip-flop 70 is repeated.
1 becomes "0" in the first half of each horizontal period, and becomes "1" in the latter half thereof (J in the figure).

Thus, the signal S is output from the decoder 67.
1 is “1” and the count data of the counter 66 is “34F
Each time the signal H becomes "H", the write horizontal start signal WHS is output, and the signal HMDP is output each time the signal S1 becomes "0" and the count data of the counter 66 becomes "3FFH" (FIG. M). This signal HMDP has a shift of 水平 horizontal period with respect to the horizontal synchronization of the composite synchronization signal CSYNC.

The connection switch 64 is turned on during one horizontal period in which the count data of the counter 78 becomes “AH” and “BH”, and only the synchronization pulse CSYNCP output from the edge detector 63 during that period is supplied to the connection switch 64 and the connection switch 64. Load terminal L of counter 66 via OR gate 65
O, and the data of “1 DAH” is loaded into the counter 66. As a result, the composite synchronization signal CSYNC is synchronized with the horizontal synchronization.

As described above, except for the period during which the data of “1 DAH” is loaded into the counter 66 based on the synchronization pulse CSYNCP, the counter 66 is supplied with “1 DAH” based on the signal S 2 output from the decoder 67 as described above. The data is loaded, and the counter 66 enters a self-reset state.

Although not described above, the generator of the system clock CLK having a frequency of 1100 fh is configured as shown in FIG. The composite synchronization signal CSYNC and the signal S2 are compared by the phase comparator 201, and the comparison error signal is VCO2
02 is supplied as a control signal. Thus, even in the self-reset state, the frequency itself of the system clock CLK is controlled, and the synchronization with the horizontal synchronization of the composite synchronization signal CSYNC is maintained.

As described above, the connection switch 64 is turned on, and the synchronization pulse CSY is used for the load control of the counter 66 and the like.
When the NCP is used, the output signal of the flip-flop 73 becomes “1” (FIG. 24F), and the connection switch 71
Is turned off, the signal S output from the decoder 67 is output.
2 is blocked.

The synchronization pulse CSYNCP cannot be supplied to the OR gate 72 during the period when the signal S1 obtained at the Q terminal of the flip-flop 70 is "0", that is, in the first half of the horizontal period. During this period, the connection switch 74 is turned off, so that the influence of noise is prevented.

The signal obtained at the Q8 terminal of the counter 66 is as shown in FIG. 24K. From the edge detector 79, a signal which becomes "1" when the count data of the counter 66 becomes "295H" is obtained. The signal is supplied to the enable input terminal EN of the counter 78 (L in the figure).

The signal H output from the decoder 67
The MDP (M in the figure) receives the counter 8 through the OR gate 82.
3 is supplied to the load terminal LO of FIG.
3 is loaded with data of "1 DAH" (O in the figure).

The signal HMDP is supplied to the OR gate 85, and a signal of "0" is supplied to the data terminal D1 of the flip-flop 87 (Q in the figure). The signal HMDP is supplied to the connection switch 89 and the OR gate 88. Is supplied to the enable input terminal EN of the flip-flop 87 through the counter 83 (R in the figure), and the counter 83 outputs “1DA”.
At the point in time when the data of "H" is loaded, the signal S5 obtained at the Q1 terminal of the flip-flop 87 becomes "0" (S in the same figure).

The counter 83 is sequentially incremented by the system clock CLK (O in the figure). 550 is counted and the count data of the counter 83 is “3FF
When it becomes "H", a carry signal is output to its CO terminal (P in the figure), and the carry signal is supplied to the load terminal LO of the counter 83 via the OR gate 82 (N in the figure), and the counter 83 is given "1 DAH". Is loaded.

The carry signal output from the counter 83 is supplied to the flip-flop 87 via the OR gate 88.
Is supplied to the enable input terminal EN (R in the figure), the signal S5 obtained at the Q1 terminal thereof becomes “1” (S in the figure).

In the same manner, the counter 83 outputs the signal H
In the first half and the second half of each cycle of MDP (one horizontal period), the counting operation from “1DAH” to “3FFH” is repeated (O in the same figure), and Q1 of the flip-flop 87 is changed.
The signal S5 obtained at the terminal becomes "0" in the first half of each cycle, and becomes "1" in the latter half (S in the same figure).

As a result, the signal S is output from the decoder 84.
5 is “1” and the count data of the counter 83 is “369”.
Every time it becomes "H", the read horizontal start signal RHS is output.

The signal HMDP cannot be supplied to the OR gate 88 during the period when the signal S5 obtained at the Q1 terminal of the flip-flop 87 is "0", that is, in the first half of each cycle of the signal HMDP. In this period, the connection switch 89
Is turned off, the effect of noise is prevented.

Next, the operation of the vertical synchronization system (odd field) will be described.

When the composite synchronizing signal CSYNC is supplied to the input terminal 61 as shown in FIG. 25A, the output signal of the integrator 75 becomes as shown in FIG. When the level of the integration output exceeds the threshold value Vth, a vertical synchronization pulse VP is output from the edge detector 77, and the load terminal LO of the counter 78 is output.
(C in the figure).

At the timing of the synchronizing pulse VP, the counter 7
8, data of "3H" is loaded (E in FIG. 8). The output signal of the edge detector 79 is supplied to the enable input terminal EN of the counter 78 (FIG. D), and the counter 78 is sequentially incremented (FIG. E).

When the count data of the counter 78 is "AH"
And "BH", the signal S3 output from the decoder 80 becomes "1" (FIG. 9F), and the connection switch 64 is turned on as described above, and the synchronization pulse CSYNC is output.
P is taken in, and the counting operation of the counter 66 is synchronized with the horizontal synchronization of the composite synchronization signal CSYNC (G in FIG. 8).

When the count data of the counter 78 becomes "DH", the signal S4 output from the decoder 80 becomes "1" (J in the figure), and the output signal of the OR gate 72 corresponding to this period (J in the figure). I) AND gate 81
This is output as a write vertical start signal WVS (K in the figure). When the counter 78 counts up to "FH", it stops itself and waits for the next load.

As described above, the count operation of the counter 83 is performed in synchronization with the signal HMDP (FIG. H) output from the decoder 67 (FIG. L), and the output signal of the OR gate 88 is as shown in FIG. become.

The counter 90 is sequentially incremented by the output signal of the OR gate 88. When the count data of the counter 90 becomes "3E6H" and "3E7H", the output signal S6 of the decoder 93 becomes "1" (N in FIG. 7), and in this period, the connection switch 91 is turned on and the output signal of the OR gate 88 becomes The signal is supplied to the load terminal LO of the counter 90 via the connection switch 91 and the OR gate 92. Then, the initial data is loaded into the counter 90. Initial data is read out from the 525/60 system (NT
SC system), it is "1F3H", and 625/50 system (PAL system) is "18FH" (O in the figure).

When the count data of the counter 90 is "3FF
"H", a carry signal is output to the CO terminal (P in FIG. 4), and the carry signal is supplied to the flip-flop 8
7 is supplied to the data terminal D2. As a result, the output signal of the edge detector 94 becomes as shown in FIG.
And the counter 90 is loaded with initial data.

Thus, the counter 90 repeats the counting operation from the initial data to “3FFH”.
In this case, the count data becomes “3FFH” because
When the reading is of the 525/60 system, it is the 525th count after the initial data is loaded, while when the reading is of the 625/50 system, it is the 625th count since the initial data is loaded. The read vertical start signal RVS is output from the decoder 93 every time the count data of the counter 90 becomes "3FFH" (R in the figure).

The operation of the vertical synchronization system in the even field is based on the count data of the counter 78 and the composite synchronization signal CS.
Only the relationship between the YNC and the horizontal synchronization is shifted by 水平 horizontal period, and the other relationship is the same as that in the odd field described above. 26A to 26G show signals corresponding to FIGS. 25A to 25G.

Incidentally, in order to simplify the explanation, FIG.
In FIG. 26A, as the composite synchronization signal CSYNC, N
This shows a TSC system. In the case of the PAL system, the number of serration pulses and equivalent pulses differs, but the operation is performed in the same manner.

In the examples of FIGS. 1 and 2 described above, the phase difference between the writing and reading of the memories 23A and 23B is reduced by 水平 horizontal period (actually, in order to secure the first access time of the page mode, In order to keep (a shift of several clocks is provided), the following is required.

(A) The horizontal synchronization cycle of the input video signal is constant.

(B) The write address signal and the read address signal must be synchronized (it is not necessary to keep them constant, it is important to keep the phase difference constant), and the same clock is used.

Regarding (a), the horizontal synchronizing signal of the video signal output from the video signal generator, tuner, LD player, etc. is accurate. Regarding consumer VTRs,
For self-recording only, the deviation of the horizontal synchronizing signal depends only on the jitter performance of the VTR.
0 ns). In this case, the memory 23
On A and 23B, there is only a fluctuation of about one data, and there is some margin in the memory capacity and the horizontal direction.

However, when a tape recorded on another VTR is reproduced on another VTR, the deviation of the horizontal synchronizing signal every one vertical period may vary depending on the mounting angle accuracy of the head chip on the rotary head of the VTR. Occurs.

That is, the tape on which the horizontal synchronizing signal is recorded exactly every horizontal period (1H) is reproduced by the heads HA and HB attached at exactly 180 ° angular intervals as shown in FIG. In this case, 1H is maintained as the horizontal synchronization cycle at the switching point of the heads HA and HB (FIG. 29A).

However, as shown in FIG.
When reproduced by the head HC not attached to the head HA at an angular interval of 180 °, the head H
The cycle of horizontal synchronization at the switching point between A and HC is 1H '(≠ 1H) (FIG. 29B).

If the deviation exceeds the horizontal margin of the memories 23A and 23B, the writing and reading operations overlap on the same memory, and the operation is broken.

As for (b), when a large shift occurs in the horizontal synchronization period at the head switching point as described above, the operation of the AFC that generates a clock synchronized with the input video signal, that is, the clock The frequency is disturbed (skew).

FIG. 30 schematically shows the mode conversion, in which the vertical synchronization position of the output screen with respect to the input screen is on a cylinder rotating at a field ratio of 50:60. When the clock is shared between the input and output, it can be seen that the skew of the clock is immediately transmitted to the output side, and the skew originally at the lower end of the input screen moves over the entire screen as the output screen cylinder rotates.

FIGS. 31 and 32 are block diagrams of a synchronous system in which skew does not occur on the output screen even if a large shift occurs in the horizontal synchronization cycle of the input video signal. In these figures, parts corresponding to FIGS. 22 and 23 include:
The same reference numerals are given and the detailed description is omitted.

In this example, the signal HMDP output from the decoder 67 is supplied to the input side of the OR gate 82 via the connection switch 101.

Further, signals S3, S
In addition to the signal S4, a signal S7 which becomes "1" when the count data of the counter 78 becomes "BH" and "CH" is output, and a signal which becomes "1" when the count data becomes "EH". S8 is output. The decoder 84 outputs “1” when the count data of the counter 83 becomes “300H” in addition to the read horizontal start signal RHS.
Is output.

Signal S7 output from decoder 80 is D
The data is supplied to the data terminal D of the flip-flop 102.
The signal S9 output from the decoder 84 is supplied to the enable input terminal EN of the flip-flop 102, and the signal S10 obtained at the Q terminal thereof is
Supplied to the fixed terminal on the side. The enable input terminal EN of the flip-flop 102 is provided to operate in synchronization with the system clock CLK, like the flip-flops 70 and 87 up to now. The signal S6 output from the decoder 93 is supplied to the fixed terminal on the b side of the changeover switch 103.

An output signal S11 of the changeover switch 103 is supplied to the connection switch 101 as an on / off control signal. The connection switch 101 is turned on when the signal S11 is “1”, and is turned off when the signal S11 is “0”.

The signal S output from the decoder 80
8 is supplied to the connection switch 91 via the connection switch 104 as an on / off control signal. Connection switch 91
Is turned on when the signal S8 is “1” and “0”
If it is, it is turned off.

The input terminal 105 is supplied with a write control signal W525. Write control signal W525
Is "1" when the writing side is the 525/60 system, and is "0" when the writing side is the 625/50 system. The write control signal W525 is supplied to an exclusive OR gate (EX OR gate) 106 together with the read control signal R525 supplied to the input terminal 95.

The output signal S12 of the EX OR gate 106 is supplied to the changeover switch 103 as a changeover control signal.
The changeover switch 103 is connected to the b side when the signal S12 is “1”, and is connected to the a side when the signal S12 is “0”.
Connected to the side.

The output signal S of the EX OR gate 106 is
Reference numeral 12 is supplied to the connection switch 104 as an on / off control signal. The connection switch 104 sets the signal S12 to “1”.
Is off, and when it is "0", it is on.

The present example is configured as described above, and the rest is configured similarly to the examples of FIGS. 22 and 23.

First, the case where the system on the writing side and the system on the reading side are the same and no system conversion is performed will be described.

At this time, the output signal S12 of the EX OR gate 106 becomes "0", and the changeover switch 103 is connected to the a side. In the flip-flop 102, the decoder 8
The output signal S7 of 0 is latched by the output signal S9 of the decoder 84. And Q of the flip-flop 102
A signal S whose terminal is synchronized with the horizontal synchronization on the read side.
10 is output and supplied to the connection switch 101 via the a side of the changeover switch 103.

Therefore, the vertical counter 78 on the writing side is used.
When the count data of "BH" and "CH" becomes
The signal HMDP is taken into the read-side synchronization system via the connection switch 101. The operation of the horizontal synchronization system on the read side is controlled based on the signal HMDP.
The operation of this horizontal synchronization system is the same as in the examples of FIGS. 22 and 23 (see FIG. 24). As a result, the horizontal counter 66 on the writing side and the horizontal counter 83 on the reading side become １ ／.
Locking is performed with the phase difference in the horizontal period.

The output signal S of the EX OR gate 106 is
12 is "0", the connection switch 104 is turned on, and the output signal S8 of the decoder 80 is connected to the connection switch 10
4 to the connection switch 91. for that reason,
When the count data of the vertical counter 78 on the write side is "E
When "H", the connection switch 91 is turned on, the output signal of the OR gate 88 is supplied to the load terminal LO of the counter 90 via the connection switch 91 and the OR gate 92, and the counter 90 is loaded with initial data. As a result, the vertical synchronization positions on the writing side and the reading side substantially match.

When the system conversion is not performed,
Even if a phase shift occurs in the composite synchronization signal CSYNC input to the input terminal 61, the horizontal counter 83 on the reading side is reset during the vertical blanking period on the reading side, and no skew appears on the screen. .

Next, a case where the system on the writing side and the system on the reading side are different and the system conversion is performed will be described.

At this time, the output signal S12 of the EX OR gate 106 becomes "1", the connection switch 104 is turned off, and the connection switch 91 is always turned off.

The horizontal counter 83 on the read side is sequentially incremented by the system clock CLK (see FIG. 3).
3J), the counting operation is repeatedly performed from “1DAH” to “3FFH”. When the count data of the counter 83 becomes "3FFH", a carry signal (K in the figure) obtained at the CO terminal is supplied to the enable input terminal EN of the vertical counter 90 on the read side via the OR gate 88, and the counter 90 is sequentially incremented. (L in the figure).

When the count data of the counter 90 is "3FF
When "H" is reached, a carry signal (M in the figure) obtained at the CO terminal of the counter 90 is supplied to the data terminal D2 of the flip-flop 87, and a signal (N in the figure) output from the edge detector 94 is supplied to the OR gate 92. Through the counter 90
Is supplied to the load terminal LO. As a result, the counter 90 is in the self-reset state, and the initial data to “3F
The count operation of "FH" is repeated. In this case, the count operation of the counter 90 is asynchronous with respect to the vertical synchronization on the writing side.

The output signal S of the EX OR gate 106 is
Since 12 is “1”, the changeover switch 103 is connected to the b side, and the output signal S6 of the decoder 93 is supplied to the connection switch 101 via the b side of the changeover switch 103. When the count data of the counter 90 becomes "3E6H" and "3E7H", the signal S6 becomes "1" (I in the same figure), and the connection switch 101 is turned on. Therefore, the signal HMDP (H in the figure) during this period is taken into the read-side synchronization system via the connection switch 101, and data of “1 DAH” is loaded into the read-side horizontal counter 83 (J in the figure). As a result, after the reading side enters the vertical blanking period, the horizontal synchronization on the reading side is synchronized with the horizontal synchronization on the writing side.

FIGS. 33A to 33G show the same signals as those in FIGS. 25A to 25G. The same applies to the operation of the even field.

As described above, even if the composite synchronizing signal CSYNC supplied to the input terminal 61 has a phase shift and the horizontal counter 66 on the writing side is reset, the horizontal counter 83 on the reading side is not immediately reset but read out. Reset during the vertical blanking period on the side. Therefore, skew due to reset does not appear on the output screen.

In the synchronous system configured as shown in FIGS. 31 and 32, when the system on the writing side and the system on the reading side are different from each other and the system conversion is performed as described above, the vertical synchronization on the reading side is changed to that on the writing side. By synchronizing the horizontal synchronization on the reading side with the horizontal synchronization on the writing side near the vertical synchronization on the reading side without synchronizing with the vertical synchronization, skew due to the phase shift of the composite synchronization signal CSYNC is prevented from appearing on the output screen. ing.

In this case, since the horizontal synchronization on the reading side is not synchronized with the horizontal synchronization on the writing side until near the vertical synchronization on the reading side, when the phase shift of the composite synchronization signal CSYNC becomes large, the writing and reading on the same memory are performed. The operations overlap, and the alternate operation of writing and reading of the memories 23A and 23B is broken. Composite synchronization signal C
The phase shift of SYNC becomes large when dubbing is repeated many times with a VTR having a shifted head (HB and HC in FIG. 28).

FIGS. 34 and 36 show the composite synchronizing signal CSYN.
Even if the phase shift of C becomes large, the memories 23A and 23B
FIG. 9 is a block diagram of a synchronous system in which the alternate operation of writing and reading is performed satisfactorily. In these figures, portions corresponding to those in FIGS. 31 and 32 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 34, signals HMDPM, HMDPP and WHDP are output from decoder 67 in addition to write horizontal start signal WHS and signal HMDP. The decoder 67 has a select signal SSE
L is supplied. The select signal SSEL is set to “1” when the image frame is set to 80% and widened as described later, and is set to “0” when the image frame is set to 70% and narrowed.
It is said.

Signals WHS, HMDPM, HMDP, HM
DPP and WHDP are output at the following timings according to the state of the select signal SSEL. Here, the 11-bit data supplied to the data terminal D of the decoder 67 is defined as WWCNT.

The signal WHS is output when the data WCNT becomes "289H" and "61FH" when the select signal SSEL is "1".
When EL is “0”, the data WWCNT is “2C1
H "and" 61FH ".

The signal HMDPM is the select signal SSEL
Is "1", the data WWCNT is "3B2H".
Is output when the select signal SSEL is "0", and is output when the data WWCNT becomes "37AH".

The signal HMDP is the data WHC regardless of whether the select signal SSEL is “1” or “0”.
Output when NT becomes "3FFH".

The signal HMDPP is the select signal SSEL
Is "1", the data WWCNT is "624H".
Is output when the select signal SSEL is "0", and is output when the data WWCNT becomes "65CH".

The signal WHDP is the data WHC regardless of whether the select signal SSEL is “1” or “0”.
Output when NT becomes "1 DAH".

The decoder 80 outputs signals S3 and S
A signal S13 is output in addition to the signals S4, S7, and S8. The signal S13 is set to "1" when the count data of the counter 78 becomes "DH". The signal S13 is the AND gate 11
1 and the output signal of the OR gate 72 is also supplied to the AND gate 111. The signal SYV is output from the AND gate 111.

As shown in FIG. 36, the decoder 84 is supplied with a select signal SSEL. Here, the 11-bit data supplied to the data terminal D of the decoder 84 is referred to as RHCNT. The read horizontal start signal RHS output from the decoder 84 is the select signal SSEL.
Is "1", the data RHCNT is "289H".
And "61FH", and when the select signal SSEL is "0", the data RHCNT is "2".
It is output when it becomes "C1H" and "61FH".

A signal HMDPR is supplied to the input side of the connection switch 101. The signal HMDPR and the above-described select signal SSEL are formed by the block shown in FIG.

In FIG. 27, the same 11-bit data WWCNT as supplied to the data terminal D of the decoder 67 is shown.
Is supplied to the data terminal D of the decoder 112. The output terminals Q0 to Q7 of the decoder 112 respectively receive the signal WHD
Eight timing pulses TP1 to TP8 indicating time points -t4 to t4 before and after the center of P are output.

Here, assuming that one horizontal period is 100%, time points -t4, -t3, -t2, -t1, t1, t2, t
3, and t4 are -26.5%, -16.5%, -9.5%, -2.5 with respect to the timing of the signal WHDP, respectively.
%, 2.5%, 9.5%, 16.5%, and 26.5% (see FIG. 37).

The timing pulses TP1 to TP8 are supplied to the phase shift detection circuit 113. Terminal I of detection circuit 113
A signal S14 obtained at the output side of the connection switch 64 (FIG. 34) is supplied to N. In the detection circuit 113, the terminal I
The timing of the synchronizing pulse CSYNCP supplied to N corresponds to the above-described time points -t4, -t3, -t2, -t1, t1,
Range -L3, -L2, -L divided by t2, t3, t4
1, L0, L1, L2, L3 (see FIG. 37).

The write vertical start signal WVS output from the AND gate 81 (FIG. 34) is
It is supplied to 14 enable input terminals EN. A carry signal is output to the CO terminal of the counter 114 every 64 counts. This carry signal is output to the connection switch 11
5 is supplied to the enable input terminal EN of the detection circuit 113. When the carry signal is supplied, the detection circuit 113 outputs data indicating the range detected as described above in synchronization with the system clock CLK.

The connection switch 115 has an AND gate 1
11 (FIG. 34) is supplied as an on / off control signal. The connection switch 115 outputs the signal S
It is turned on when YV is "1".

The terminal ON of the detection circuit 113 has E
Signal S1 output from X OR gate 106 (FIG. 36)
2 are supplied. Signals R525 and W525 are both "1"
Or, when it is “0” and the signal S12 becomes “0”,
That is, when the system conversion is not performed, data indicating the range S0 is output from the detection circuit 113 regardless of the range detected as described above.

Data indicating the detection range output from detection circuit 113 is supplied to data terminal D of D flip-flop 117.
Supplied to The carry signal obtained at the CO terminal of the counter 114 is supplied to the enable input terminal EN of the flip-flop 117 via the connection switch 115. When the carry signal is supplied, data indicating the detection range supplied to the data terminal D is latched in synchronization with the system clock CLK.

Data S15 obtained at output terminal Q of flip-flop 117 is supplied to data terminal D of D flip-flop 118. The carry signal obtained at the CO terminal of the counter 114 is supplied to the enable input terminal EN of the flip-flop 118 via the connection switch 115. When the carry signal is supplied, data S15 indicating the detection range supplied to the data terminal D is latched in synchronization with the system clock CLK.

Data S15 and S16 obtained at output terminals Q of flip-flops 117 and 118 are supplied to terminals A and B of match detection circuit 119, respectively. Detection circuit 1
19 enable input terminal EN, and AND gate 11
1 (FIG. 34) is supplied via a delay circuit 120 having a delay time of three clocks. When the signal SYV supplied to the enable input terminal EN becomes “1”, the detection circuit 119 detects whether or not the data S15 and S16 match in synchronization with the system clock CLK. Then, when they match, the data is output.

Data DP output from detection circuit 119
Is supplied to the decoder 121. In the decoder 121,
Signal HMDP output from decoder 67 (FIG. 34)
M, HMDP and HMDP are supplied. Decoder 12
1, the signal HMDPM,
HMDP or HMDPP is selected and the signal HM
This signal is output as DPR, and this signal HMDPR is supplied to the input side of the connection switch 101 (FIG. 36) as described above.

That is, when data DP indicates a range of -L2, -L1, signal HMDP is selected. When data DP indicates a range of L0, signal HMDP is selected, and any of L1, L2 is selected. If the range is shown, signal HMDPP is selected (see FIG. 37).

In decoder 121, select signal SSEL is formed according to the range indicated by data DP. That is, it is set to "0" when the data DP indicates any range of -L2, L2, and is set to "1" when the data DP indicates any range of -L1, L0, L1. The select signal SSEL formed in this way is supplied to the decoders 67 and 84 as described above.

When data DP indicates any range between -L3 and L3, decoder 121 outputs signal WDIS. Thereby, the memory write timing generator 24 is controlled and the memories 23A and 23B are controlled.
Is stopped, and a still image is output.

This example is configured as described above, and the rest is configured similarly to the examples of FIGS. 31 and 32.

Next, an operation for forming signal HMDPR and select signal SSEL in the block shown in FIG. 35 will be described. The case where the states of the write control signal W525 and the read control signal R525 are different and the output signal S12 of the EX OR gate 106 becomes "1", that is, the case where the system conversion is performed will be described.

First, the case where the internal counter is behind the input composite synchronizing signal CSYNC will be described with reference to the timing chart of FIG.

FIG. 38A is a composite synchronizing signal CSYNC supplied to the terminal 61, FIG. 38B is a signal S3 output from the decoder 80, FIG. 38C is a signal supplied to the load terminal LO of the counter 66, and FIG. E shows the output S1 of the flip-flop 70, F shows the output of the OR gate 72, H shows the falling edge of the Q8 output of the counter 66, and I shows the output of the counter 78. This is the same as described in the other embodiments described above.

The signal WHDP is output from the decoder 67 when the output of the counter 66 becomes "1 DAH" and the output S1 of the flip-flop 70 becomes "0" (FIG. 38G). The signal WHDP corresponds to the horizontal synchronization position of the internal counter.

In the phase shift detecting circuit 113, the decoder 1
12 based on the timing pulses TP1 to TP8 from the signal WHDP as described above.
3 is set (J in the figure). When the output of the counter 78 is "A
H "and" BH ", the output signal S of the decoder 80
3 becomes “1”, the connection switch 64 is turned on, and the synchronization pulse CSYNCP is supplied to the terminal IN of the phase shift detection circuit 113. Thereby, the synchronization pulse CSYNP
-N (-L3, -L2, -L1, L0) corresponding to
Is detected (K in the figure).

In this state, when the output of the counter 78 becomes "CH", the output signal S of the AND gate 111 is output.
The YV becomes “1” (L in the figure), and the connection switch 115
Turns on. At this time, when the count value of the counter 114 is “3FH” and a signal of “1” is output to the terminal CO as a carry signal, the detection circuit 113
Is supplied to the enable input terminal EN, the detection circuit 113 outputs data indicating the range −n detected as described above (M in FIG. 8).

In this state, when the output of the counter 78 becomes "DH", the signal WVS is output from the AND gate 81.
Is output (N in FIG. 8), and the count data of the counter 114 is incremented from “3FH” to “0H” (O in FIG. 9).

After one vertical period (after 1 V) from this state, the signal SYV becomes “1”.
Is output to the detection circuit 113.
Output does not change. Further, since the signal WVS is output, the counter 114 is incremented. The same is repeated until after 63V.

After 64 V, the signal SYV becomes “1” and the signal “1” is output to the terminal CO of the counter 114 (P in FIG. 27), so that the enable input terminal EN of the flip-flop 117 becomes “1”. The signal "1" is supplied, and the data output to the detection circuit 113 is latched (Q in the figure). Also, since a signal of “1” is supplied to the enable input terminal EN of the detection circuit 113 with a delay of one clock, data indicating the range −n detected after 64 V is output to the detection circuit 113 (see FIG. (Figure M). Further, the count data of the counter 114 is incremented from "3FH" to "0H" (O in the same figure).

Then, after 128 V, the same operation as after 64 V is performed, a signal of "1" is supplied to the enable input terminal EN of flip-flop 118, and the output data of flip-flop 117 is latched ( (R), a signal of “1” is supplied to the enable input terminal EN of the flip-flop 117, and the output data of the detection circuit 113 is latched. Then, a signal of "1" is supplied to the enable input terminal EN of the detection circuit 119 with a delay of three clocks after the signal SYV becomes "1", and the output data S15 and S of the flip-flops 117 and 118 are supplied.
Sixteen matches are detected. That is, it is detected whether or not the data indicating the range −n detected at a distance of 64 V matches. When they match, the data DP is output from the detection circuit 119 (S in the figure).

When data DP is output in this manner, decoder 121 outputs H according to data DP as described above.
The MDPR is selected and the select signal SSEL is determined. FIG. T shows an example in which HMDPM is selected as HMDPR.

Next, a case where the internal counter is advanced with respect to the input composite synchronizing signal CSYNC will be described with reference to the timing chart of FIG.

FIGS. 39A to 39J show signals corresponding to A to J in FIG.

The outputs of the counter 78 are "AH" and "B
"H", the output signal S3 of the decoder 80 becomes "1", the connection switch 64 is turned on, and the synchronization pulse CS
YNCP is supplied to the terminal IN of the phase shift detection circuit 113. As a result, a range + n (L0, L1, L2, L3) corresponding to the synchronization pulse CSYNP is detected (K in the figure).

In this state, when the output of the counter 78 becomes "CH", the output signal S of the AND gate 111 is output.
The YV becomes “1” (L in the figure), and the connection switch 115
Turns on. At this time, when the count value of the counter 114 is “3FH” and a signal of “1” is output to the terminal CO as a carry signal, the detection circuit 113
Is supplied to the enable input terminal EN, the detection circuit 113 outputs data indicating the range + n detected as described above (M in FIG. 8).

In this state, when the output of the counter 78 becomes "DH", the signal WVS is output from the AND gate 81.
Is output (N in FIG. 8), and the count data of the counter 114 is incremented from “3FH” to “0H” (O in FIG. 9).

The following operates in the same manner as the timing chart of FIG. 38 described above, and a description thereof will not be repeated.

When the state of the write control signal W525 and the state of the read control signal R525 are the same and the output signal S12 of the EX OR gate 106 is "0", that is, when no system conversion is performed, the output of the detection circuit 113 becomes L0.
, The output data DP of the detection circuit 119 also becomes data indicating the range of L0. Therefore, HMDP is selected as HMDP by the decoder 121, and the select signal SSEL is set to "1".

The operation of generating signals WHS, WVS, RHS, and RVS in the blocks shown in FIGS. 34 and 36 is the same as the operation of the blocks shown in FIGS. 31 and 32, and will not be described. .

Next, write and read timings of the memories 23A and 23B when the signal HMDPR is selected and the select signal SSEL is formed as described above will be described with reference to FIG. MEMA, ME
MB indicates the memories 23A and 23B, respectively.

First, writing to the memories 23A and 23B will be described.

FIG. 40A shows the composite synchronizing signal CSYNC, FIG. 40B shows the output of the counter 66, and FIG.
The output S1 of 0 is shown.

When select signal SSEL is "1" (wide)
When the write horizontal start signal WHS is output from the decoder 67 at the timings of “289H” and “61FH” (D in FIG. 11), the write to the memory 23A is “289H” as shown in FIG. The writing to the memory 23B is started at the timing of “61FH”, and the frames 23 are stored in the memories 23A and 23B.
A video signal corresponding to 0% is written.

On the other hand, when the select signal SSEL is “0” (narrow) and the write horizontal start signal WHS is output from the decoder 67 at the timing of “2C1H” and “61FH” (FIG. D), As shown in FIG. F, writing to the memory 23A starts at the timing of “2C1H”, and writing to the memory 23B starts at “61F”.
H ", and a video signal corresponding to the image frame 70% is written to the memories 23A and 23B.

Next, reading from the memories 23A and 23B will be described. FIG. 40G shows the signal HMDPR supplied to the connection switch 101.

When the signal HMDPM is selected as the signal HMDPR and the select signal SSEL is "0" (narrow), the counter 83 is reset to "1 DAH" at the timing "37AH" on the write side (H in FIG. ). FIG. 11 shows the output S5 of the flip-flop 87 at that time. At this time, the read horizontal start signal RHS output from the decoder 84 is output at the timings of “2C1H” and “61FH” (J in FIG.
As shown in FIG. K, reading from the memory 23A is “2
C1H ", reading from the memory 23B is started at" 61FH "(K in the figure), and video signals corresponding to 70% of the image frame are read from the memories 23A and 23B.

The signal HMDP is used as the signal HMDP.
When M is selected and the select signal SSEL is “1” (wide), the counter 83 is reset to “1DAH” at the timing “3B2H” on the write side (L in FIG. 4). At this time, the read horizontal start signal RHS output from the decoder 84 is output at the timings of “289H” and “61FH” (M in FIG. 8), and as shown in FIG.
H ", and the reading from the memory 23B is started at the timing" 61FH ".
Video signals corresponding to 80% of the image frame are read from 3A and 23B.

The signal HMDP is used as the signal HMDP.
Is selected and the select signal SSEL is "1" (wide)
, The counter 83 is reset to “1 DAH” at the timing of “3FFH” on the write side (O in FIG. 8). At this time, the read horizontal start signal RHS output from the decoder 84 is “289H” and “61F”.
H) (P in FIG. 8), reading from the memory 23A is started at a timing of “289H”, reading from the memory 23B is started at a timing of “61FH” as shown in FIG. Memory 23A,
A video signal corresponding to 80% of the image frame is read from 23B.

The signal HMDP is used as the signal HMDP.
When P is selected and the select signal SSEL is "1" (wide), the counter 83 is reset to "1 DAH" at the timing of "624H" on the write side (R in the figure). At this time, the read horizontal start signal RHS output from the decoder 84 is output at the timings of “289H” and “61FH” (S in FIG. 10), and as shown in FIG.
H ", and the reading from the memory 23B is started at the timing" 61FH ".
Video signals corresponding to 80% of the image frame are read from 3A and 23B.

The signal HMDP is used as the signal HMDP.
When P is selected and the select signal SSEL is "0" (narrow), the counter 83 is reset to "1 DAH" at the timing of "65CH" on the write side (U in the figure). At this time, the read horizontal start signal RHS output from the decoder 84 is output at the timings of “2C1H” and “61FH” (V in FIG. 5), and as shown in FIG.
H ", and the reading from the memory 23B is started at the timing" 61FH ".
Video signals corresponding to 70% of the image frame are read from 3A and 23B.

When signal WDIS is output from decoder 121 (FIG. 35), memory 2 is output as described above.
Writing to 3A and 23B is stopped, but reading is repeated in the state immediately before. Therefore, the output state of the still image of the image frame 80% or 70% is obtained.

Thus, in the examples of FIGS. 34 to 36, corresponding to the phase shift of the internal counter with respect to the composite synchronization signal CSYNC, the picture frame 80% (wide) or picture frame 70% (narrow) is stored in the memories 23A and 23B. Is written and read.

As shown in FIG. 40, in both the operation of the image frame 80% and the operation of the image frame 70%, during the period from the start of writing to the memory 23B to the end of writing to the memory 23A, the start of reading from the memory 23A To the end of reading of the memory 23B. In both the operation of the image frame 80% and the operation of the image frame 70%, the memory 23B starts writing from the memory 23B.
Switching of reading from the memory 23A to the memory 23B is performed during a period until the writing start of A.

Therefore, even if the internal counter has a phase shift with respect to the composite synchronization signal CSYNC, the memory 23
A failure does not occur in the alternate operation of writing and reading of A and 23B.

In FIGS. 34 and 36, 64 V
, The phase shift of the internal counter with respect to the composite synchronization signal CSYNC is detected, and when the same phase shift is detected twice, the signal HMDPR and the select signal SSEL are changed.
The read state does not change frequently, and image quality degradation can be prevented.

Although not described in the above embodiment,
For example, when the image frame is 70%, the outside of the image frame becomes an unsightly noise screen.

[0298]

According to the present invention, the number of lines and the number of fields are converted by controlling the first and second memories alternately in the write state and the read state every half horizontal period. Can be configured using an inexpensive general-purpose memory (storage capacity for 0.5 fields) instead of an expensive video RAM as each memory.
A method conversion device that also performs field conversion can be configured at low cost.

Also, when a shift occurs in the horizontal synchronization of the input video signal, the influence is transmitted to the reading side during the vertical blanking period of the reading side regardless of the presence or absence of system conversion. Can be satisfactorily avoided.

Further, since the picture frame of the video signal to be written in the first and second memories is changed according to the phase shift between the horizontal synchronization of the input video signal and the horizontal synchronization on the writing side, even if the phase shift becomes large, The alternate operation of writing and reading of the first and second memories will not fail.
In this case, by detecting the phase shift every predetermined period, the image frame can be prevented from deteriorating without frequently changing the image frame.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a block diagram illustrating a configuration of an embodiment.

FIG. 3 is a connection diagram illustrating a configuration of an A / D conversion processing unit.

FIG. 4 is a diagram for explaining the operation of the example of FIG. 3;

FIG. 5 is a diagram for explaining the operation of the embodiment.

FIG. 6 is a diagram for explaining the operation of the embodiment.

FIG. 7 is a connection diagram illustrating a configuration of a quantization processing unit for a luminance signal.

FIG. 8 is a diagram for explaining quantization in a normal A / D converter.

FIG. 9 is a diagram for explaining quantization in the example of FIG. 7;

FIG. 10 is a diagram for explaining a memory write cycle in a normal mode and a page mode.

FIG. 11 is a diagram for explaining a memory read cycle in a normal mode and a page mode.

FIG. 12 is a connection diagram illustrating a configuration of a demultiplexer.

FIG. 13 is a diagram for explaining the operation of the demultiplexer.

FIG. 14 is a connection diagram illustrating a configuration of a sub-sampling data processing circuit.

FIG. 15 is a diagram showing sub-sampling data.

FIG. 16 is a diagram for explaining signal processing in the example of FIG. 14;

FIG. 17 is a diagram showing sub-sampling data (read twice).

18 is a diagram illustrating data of a main part of the processing circuit in the example of FIG. 14;

FIG. 19 is a diagram for explaining signal processing in the example of FIG. 14;

FIG. 20 is a diagram for explaining signal processing in the example of FIG. 14;

FIG. 21 is a diagram for explaining color signal synchronization processing.

FIG. 22 is a block diagram showing a synchronous system on a write side and a read side.

FIG. 23 is a block diagram showing a synchronization system on a writing side and a reading side.

FIG. 24 is a diagram for explaining the operation of the horizontal synchronization system in the example of FIGS. 22 and 23;

FIG. 25 is a diagram for explaining an operation (an odd field) of the vertical synchronization system in the examples of FIGS. 22 and 23;

FIG. 26 is a diagram for explaining an operation (even field) of the vertical synchronization system in the examples of FIGS. 22 and 23;

FIG. 27 is a block diagram showing a configuration of a system clock generator.

FIG. 28 is a diagram showing an overview of a rotary head device.

FIG. 29 is a diagram for explaining a phase shift in horizontal synchronization.

FIG. 30 is a schematic diagram showing a state of system conversion.

FIG. 31 is a block diagram showing a synchronization system on a writing side and a reading side.

FIG. 32 is a block diagram showing a synchronous system on the write side and the read side.

FIG. 33 is a view for explaining the operation (odd field) of the vertical synchronization system in FIGS. 31 and 32;

FIG. 34 is a block diagram showing a synchronous system on a write side and a read side.

FIG. 35 is a block diagram showing a synchronization system on a writing side and a reading side.

FIG. 36 is a block diagram showing a synchronization system on a writing side and a reading side.

FIG. 37 is a diagram showing the relationship between the amount of phase shift and signals SSEL and HNDPR.

FIG. 38 is a diagram for explaining an operation of determining a synchronization deviation (when an internal counter is behind input CSYNC);

FIG. 39 is a diagram for explaining the operation of determining a synchronization shift (when an internal counter is advanced with respect to input CSYNC);

FIG. 40 shows the writing of the memory in FIGS. 34 to 36;
FIG. 4 is a diagram for explaining read timing.

FIG. 41 is a diagram for explaining line number conversion in system conversion;

FIG. 42 is a diagram for explaining field number conversion in system conversion;

FIG. 43 is a diagram for explaining line number conversion in system conversion;

[Explanation of symbols]

1Y, 1C input terminal 2, 5 resistor 3, 40 adder 4 write timing generator 6, 14, 15, 25 switch circuit 7 color demodulator 8 AFC circuit 9 A / D converter 10, 12 latch circuit 11 digital low-pass Filter 13 P / S converter 21, 22, 34, 36, 42 to 44, 46, 48 Switch 23A, 23B Memory 24 Memory write timing generator 26 Synchronization generator 27 Memory read timing generator 31 Demultiplexer 32 Read timing Generator 33 Filter circuit 35, 45 Delay circuit 37, 47, 49 Signal generator 38, 51 D / A converter 39 Low-pass filter 41 S / P converter 50 Color modulator 52 Band-pass filter 53 Output terminal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 7/01

Claims (2)

(57) [Claims] With claim 1, having a storage capacity of 1/2 horizontal period with respect to the horizontal direction, comprising a first and a second memory having a storage capacity of 1 vertical period with respect to vertical direction, to the first memory Input video signal during the first half of each horizontal period
Constituting one write the first half of the horizontal period of data-free
With the first memory during the latter half of each horizontal period.
The first half of the data for one horizontal period that constitutes the output video signal
Min and by controlled so read out, the second memory to write the second half of one horizontal period <br/> of data constituting the input video signal in the second half period of each horizontal period write Mutotomoni, the second Note
The output video signal in the first half of each horizontal period
One horizontal period control to read out Suyo the first half of the data of
And, a television standards converter for converting the number of lines and the number of fields, when not a system conversion, in the vicinity of the vertical synchronizing position of the writing side of the memory, the horizontal synchronization and vertical synchronization of the read side of the memory When performing the system conversion by synchronizing with the horizontal synchronization and vertical synchronization of the writing side, respectively, without synchronizing the vertical synchronization of the reading side with the vertical synchronization of the writing side, in the vicinity of the vertical synchronization position of the reading side, when the system conversion with the horizontal synchronization of the reading side is synchronized with the horizontal synchronizing the writing side detects a phase difference between the horizontal synchronization of the horizontal sync and the write side of the input video signal, to the phase difference A television system conversion apparatus, wherein an image frame of a video signal to be written into the first and second memories is changed in accordance with the change. 2. The image frame according to claim 1, wherein said phase difference is detected at predetermined intervals, and said picture frame is changed in accordance with said phase difference when substantially the same phase difference continues two or more times. Television system converter.