JP3456495B2 - Television system converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is, for example, 525/60.
The present invention relates to a television system converter capable of mutually converting a system between a system and a 625/50 system.

[0002]

2. Description of the Related Art The television (TV) system currently adopted in the world is mainly composed of the following three types because of the structure of a composite video signal.
It is divided into methods.

System name Scan line / number of frames Color subcarrier Modulation system NTSC 525/60 3.58 MHz Quadrature two-phase modulation PAL 625/50 4.43 MHz Quadrature two-phase modulation However, V axis phase inversion SECAM for each scan line Same as above 4.25 MHz 4.206 MHz FM modulation Furthermore, NTSC and PAL each have a combination of scanning line / frame number and color modulation method, and are as follows.

System name Scan line / number of frames Color subcarrier V-axis phase inversion for each scan line 4.43 NTSC 525/60 4.43 MHz None M-PAL 525/60 3.58 MHz Yes N-PAL 625/50 3. 58MHz Yes, but NTSC, M-PAL, N-PAL 3.58
Each MHz is slightly different.

From these, the requirements necessary for mutual conversion between television systems are summarized in the following two. (1) Conversion of scanning line / number of frames (line / field) 525
/ 60,625 / 50 (2) Conversion of color modulation system Carrier frequency (fsc) Quadrature two-phase modulation, FM modulation Presence / absence of V-axis phase inversion (2) is suitable for each system as a demodulator and modulator of color signal It can be easily done by using a thing.
In the case of (1), there is a time lag between the signals before and after the conversion, so that processing using an image memory is generally required.

If the conversion of (1) is also performed, the number of lines must be converted first. 525/60 series → 625/5
In the case of 0-system conversion, there is an increase of 100 lines per field, and it is necessary to increase the ratio of 1 line to 5 lines as shown in FIG. 46A. Conversely, 625/50 series → 525
In the case of conversion of the / 60 system, the number of lines is reduced by 100 lines per field, and it is necessary to reduce the number of lines every 6 lines as shown in FIG. The number of lines can be increased or decreased by simply overlapping or thinning the same line. From the exact calculation, the number of lines after conversion will be ± 5 lines excess or deficiency by simple duplication every 5 lines or thinning out every 6 lines.
This can be absorbed in the vertical blanking period.

As is clear from FIG. 46, the conversion of the number of lines requires an image memory for one line or more. Although it seems that one line is enough in the figure, in order to convert all one field, an image memory for one field or more is required as shown below.

FIG. 47A shows a 525/60 system → 625/50.
The field number conversion of the system is shown in FIG.
The field number conversion from 50 system to 525/60 system is shown. Looking at the conversion portion of the m + 4 → m + 4 ′ field in FIG. A, the last line of the m + 4 field is m + 4 ′.
The shift to the field of (arrow P1) coincides with the timing of the last line of the m + 5 field. for that reason,
It is necessary to delay the last line of the m + 4 field by one field. Further, looking at the conversion portion of the n → n ′ field in FIG. 6B, the last line of the n field is n−
This coincides with the timing of the last line of the 1'field (arrow P2), and a delay of 1 field is required.
The same thing occurs in the conversion part of the n + 5 → n + 5 ″ field (arrow P3). Strictly speaking, the above-mentioned line coincidence does not completely coincide with a slight line difference, so that the line coincides completely. Although the delay amount of one field is not necessary, one field is used here for simplification of description.

The delay of one field is usually realized at present by digitizing a signal and using a digital memory as an image memory.

Horizontal resolution is 320 lines, luminance (Y) S / N
The memory capacity of one field required for format conversion of a standard TV signal of 46 dB for SNR and 36 dB or more for color (C) S / N is as follows. However, in consideration of the conversion of (2) described above, the C system already has color difference signals R−Y = V, B.
It is assumed that demodulation has been completed in the state of -Y = U and two systems are required.

Here, the following set values are considered for the sampling frequencies and gradations of the Y and C systems. Y system Sampling frequency: 8 MHz Gradation: 8 bits C system Sampling frequency: 3 MHz Gradation: 6 bits Also, considering the mutual conversion of 525/60 system and 625/50 system, one field is based on 625/50 system. Think

From the above, the memory capacity of one field is obtained by the following equation. {8 × 8 × 10 ⁶ + (6 × 3 × 10 ⁶ × 2)} ÷ 50 = 1.8 × 10 ⁶ = 1.8 Mbits If the resolution and gradation set above are required to be improved, , The memory capacity will be larger.

Furthermore, looking at the state of line number conversion in more detail, since the TV signal is interlaced in both the 525/60 system and the 625/50 system, a simple field as shown in FIG. 46 is used. The conversion of the number of lines per unit may impair the image quality in the vertical direction.

48A to 48C show a 525/60 system → 625 /
The position of each line when displayed in the same image size when converting the 50-series system is shown in detail. The solid line shows the line position of the odd field and the dotted line shows the line position of the even field. Therefore, the two are alternately arranged.

FIG. 1A shows a state of conversion when a field memory is used, and represents the same type of field (odd → odd or even → even). There are some parts where the vertical positional relationship is reversed, such as the z ″ and a ″ lines, and there are parts where the positions are shifted downward by almost one line, such as the a ′ to a ″ lines.

FIG. 6B shows a state of conversion when a field memory is used, and shows between different fields (odd → even or even → odd). Also in this case,
The f'-e "-f" lines are reversed upside down, and the f'-f "lines are significantly shifted downward.

Incidentally, as is apparent from FIG. 47, during conversion, one field duplication (n + 5 ″ in FIG. B) and thinning (m + 5 in FIG. A) occur, so conversion between same-type fields and conversion between different types of fields. The cyclical change with is inevitable.

In each field, a->c-> e is interlaced, but since it is continuously visible from a to k in the eyes, vertical line reversal and a significant line position as shown in FIGS. The shift is recognized as vertical graphic distortion.

On the other hand, in FIG. 6C, since the conversion field is formed from two fields (one frame),
There is no reversal of the upper and lower lines, and the positional deviation is suppressed to a maximum of 0.5 lines, and the figure distortion in the vertical direction is greatly improved.

Most of the conventional TV system converters are for broadcasting and for business use, and because they do not like image quality deterioration, they also have a large memory capacity per field and the above-mentioned FIG. 48C.
Since the number of lines is converted in each frame, a memory for one frame is required. Actually, in order to further improve the image quality, the one having a memory of several frames is the mainstream.

[0021]

As described above, the conventional television conversion device requires a large-capacity memory when line / field conversion is performed while suppressing large graphic distortion. was there.

Therefore, the present invention provides a television system converter which does not require a large-capacity memory and which suppresses image quality deterioration such as graphic distortion.

[0023]

A television system converter according to the present invention sequentially writes a memory having a storage capacity for one field and video data constituting an input video signal of the first system into this memory. A memory write control means, a memory read control means for reading video data of continuous first and second lines from the memory in parallel, and a first read by the memory read control means.
And interlace using video data of the second line
Arithmetic processing means for performing video interpolation to obtain video data of each line forming an output video signal of a second method different from the first method, and first and second memory read control means. The memory read control means is provided with a field inversion detection means for detecting occurrence of field inversion in which a field at the time of writing video data of a line is different from a field at the time of reading , and the memory read control means reads out a field at the time of writing in an odd field.
When field when the field inversion an even field is detected, shifting twice readings or thinning of lines with one line shift line out read, full
Field inversion means even field
Field is an odd field when reading
Double reading or
The thinning line is shifted .

For example, field identification data for identifying a field at the time of writing is added to each line of video data which constitutes an input video signal written in a memory,
The field inversion detection means detects field inversion on a line-by-line basis by using field identification data.

[0025]

According to the present invention, a memory having a storage capacity for one field is provided, and the memory capacity can be small and the cost can be reduced. In addition, the video data of the first and second continuous lines are read in parallel from the memory to perform a coefficient calculation process to obtain a desired interpolation line, and read when necessary when field inversion is detected. Interlace interpolation is performed by shifting the line by one line and shifting the double-reading or thinning-out line, so that even if field inversion occurs, it is possible to reduce the occurrence of figure distortion due to double-reading or thinning-out of the line. It will be possible. Field identification data that identifies the field at the time of writing is added to each line of the video data, and field inversion detection is performed line by line using the field identification data to reduce the figure distortion due to field inversion. It is possible to immediately perform shift processing and the like.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a television system converter according to the present invention will be described below with reference to FIGS. This example is an example in which the NTSC system and the PAL system can be mutually converted.

In the figure, the luminance signal Y is applied to the input terminal 1.
Is supplied. This luminance signal Y is sent to the low pass filter 2 for sampling frequency f in the A / D converter in the subsequent stage.
It is supplied to the clamp circuit 3 after being band-limited to 1/2 of s. The clamp pulse YCLP is supplied to the clamp circuit 3, and the pedestal level is clamped to a constant value so as to match the input range of the A / D converter in the next stage. The luminance signal Y output from the clamp circuit 3 is supplied to the A / D converter 4.

A sampling clock ADCLK (shown in FIG. 4A) is supplied to the A / D converter 4, and a luminance signal Y (shown in FIG. 4B) is supplied as one sample 8-bit digital luminance data ADY (shown in FIG. 4C). ) Is converted to. When the frequency of the sampling clock ADCLK is fwck, the horizontal frequency fh of the input video signal (luminance signal Y supplied to the input terminal 1) is set as follows. That is, fwck = 1128fh when the input video signal is the NTSC system, and fw when the PAL system is the input video signal.
ck = 1152fh is set. The reason for this setting will be described later.

The luminance data ADY output from the A / D converter 4 is converted by the conversion circuit 5 from the normal binary display (offset binary) to the two's complement display and supplied to the multiplexer 6. The conversion circuit 5 also performs rounding processing. That is, in the conversion circuit 5, the MSB data of the brightness data ADY from the A / D converter 4 is inverted to be converted into 2's complement display. For example, in the case of 8-bit data, "10000" is displayed.
Cannot be displayed. Therefore, in such a case, "1" is added to the LSB data to obtain "1000000".
The process of "1" is the rounding process.

Further, the carrier color signal C is supplied to the input terminal 7. The carrier color signal C is supplied to the chroma decoder 8. The chroma decoder 8 is supplied with the composite sync signal WCSYNC which is separated from the luminance signal Y supplied to the input terminal 1. Further, one end of the crystal oscillators 9 and 10 is connected to the chroma decoder 8, and the other ends thereof are connected via the n side and the p side of the changeover switch 11. The oscillation frequency of the crystal oscillator 9 is 3.579 MHz (fscn) which is the color subcarrier frequency of the NTSC system, while the oscillation frequency of the crystal oscillator 10 is 4.433 MHz (fscp) which is the color subcarrier frequency of the PAL system. .

A system controller (not shown) supplies the changeover switch 11 with a system identification signal Wn / p indicating whether the input video signal is the NTSC system or the PAL system as a changeover control signal. PAL
When it is the system, it is connected to the p side, and when it is the NTSC system, it is connected to the n side. This system identification signal Wn /
p is also supplied to the chroma decoder 8.

The chroma decoder 8 extracts the burst signal from the carrier color signal C by a burst gate pulse formed from the composite synchronizing signal WCSYNC as is well known in the art, and converts it into a continuous wave signal by the crystal oscillator 9 or 10 to generate a reference color signal. A subcarrier is obtained, and synchronous detection is performed on the RY axis and the BY axis using the reference color subcarrier to obtain a red color difference signal RY and a blue color difference signal BY.

The color difference signals RY and BY output from the chroma decoder 8 are low pass filters 12R and 1R, respectively.
After being band-limited to 1/4 of the sampling frequency fs in the A / D converter in the subsequent stage by 2B, the clamp circuit 1
It is supplied to 3R and 13B. Clamp circuit 13R, 13
The clamp pulse YCLP is supplied to B, and A /
The blanking level is clamped to a constant value so as to match the input range of the D converter.

The color difference signals RY and BY output from the clamp circuits 13R and 13B are respectively connected to the connection switch 14.
It is supplied to the A / D converter 15 via R and 14B. To the connection switches 14R and 14B, select signals SELR and SELB, each having a cycle four times as long as the sampling clock ADCLK (shown in FIG. 4A) and having a phase inversion relationship with each other, are supplied as on / off control signals. These select signals SELR and SELB are 1
It is formed by shifting by one clock for each line. Figure 4
D and E indicate select signals SELR and SELB corresponding to even lines (2n lines), and I and J in the same figure indicate select signals corresponding to odd lines (2n + 1 lines).

The connection switches 14R and 14B are turned on when the select signals SELR and SELB are at high level "H", and turned off when they are at low level "L". Therefore, the color difference signals RY and BY output from the clamp circuits 13R and 13B are connected to the connection switch 1 respectively.
The signals are alternately selected by 4R and 14B every 4 clock cycles and supplied to the A / D converter 15 as a color difference point sequential signal Cr / b. FIG. 4F shows the color difference point sequential signal Cr /
FIG. 9B shows the color difference point sequential signal Cr / b of the odd line.

The color difference point sequential signal Cr / b input to the A / D converter 15 becomes discontinuous and unstable at the switching portion of the color difference signals RY and BY (FIG. 4F,
The switching part is continuously shown in K for simplification of the drawing). Therefore, the rising and falling edges of the select signals SELR and SELB described above are set so as to coincide with the rising edge of the sampling clock ADCLK so that the A / D converter 15 does not sample the switched portion. By the way, A / D
In the converter 15, the sampling clock ADCLK
Sampling is performed at the falling edge of.

The sampling clock ADCLK is supplied to the A / D converter 15, and the color difference point sequential signal Cr /
b is converted into a 1-sample 8-bit digital color signal ADC. FIG. 4G shows digital color data A of even lines.
DC is shown, and L in the drawing shows digital color data ADC of odd lines. This A / D converter 15
The output color data ADC is converted by the conversion circuit 16 from the normal binary display to the two's complement display and supplied to the multiplexer 6. The conversion circuit 16 also performs the rounding process as in the conversion circuit 5 described above.

The multiplexer 6 has a switching control signal SW1.
Are supplied, and the sample data of the luminance data ADY and the color data ADC are alternately selected to generate the video data VDAT.
A is formed. In this case, of the continuous two sample data of the color difference signals R-Y and B-Y which form the color data ADC, the stable second data is selected instead of the unstable first data immediately after switching. . Further, the brightness data ADY is selected so as to have a line offset relationship. As a result, the line offset subsampling is performed on the luminance data ADY. Figure 4
H indicates video data VDATA of an even line,
The same figure M shows the video data VDATA of the odd line.

The upper 4 bits and the lower 4 bits of the video data VDATA output from the multiplexer 6 are supplied to the multiplexers 17 and 18, respectively. The multiplexer 17 has 4-bit ID data O indicating whether the input video signal is an odd field or an even field.
DD / EVEN is supplied. For example, each bit data is "0" in the odd field and each bit data is "1" in the even field. Further, the multiplexer 18 has 4-bit ID data SUBNSE indicating whether the input video signal is an odd line or an even line.
Q is supplied. For example, each bit data is "0" on the odd line and each bit data is "1" on the even line.

A switching control signal SW2 is supplied to the multiplexers 17 and 18, and video data VDATA of each line is supplied.
ID data ODD / EVEN, S at the timing immediately before
UBNSEQ is selected. That is, in the multiplexers 17 and 18, the ID data ODD / EVEN and SUBSEQ are added to the head of the video data VDATA of each line to form the write data WDATA.

The write data WDATA output from the multiplexers 17 and 18 is supplied to the field memory 19 and sequentially written. The memory 19 has three ports. That is, there are one write port and two read ports. Each system operates completely asynchronously, and reading can always be continued independently for writing. The memory 19 is, for example, 306 rows × 9
60 columns x 8 bits, NTSC system and P
It is designed to be compatible with both AL systems.

For example, when the input video signal is of the NTSC system, each line is composed of 1128 clocks, the odd field is composed of 262 lines and the even field is composed of 263 lines as shown in FIG. 5A. Then, the video data VDATA for the 166th clock to the 936th clock is written in the horizontal direction, and from the 11th line in the vertical direction to 2 in the odd field (O).
Video data VDATA of 50 lines and 251 lines of even field (E) are written.

On the other hand, when the input video signal is of the PAL system, each line is composed of 1152 clocks, the odd field is composed of 312 lines, and the even field is composed of 313 lines as shown in FIG. 5B. Then, the video data VDATA for 190th to 936th clocks is written in the horizontal direction, and the video data VD for the 301st line to 301st line is written in the vertical direction.
ATA is written.

FIG. 6 shows the structure of write data WDATA for each line with respect to the memory 19. That is, the ID data ODD / EVEN, SUB for 8 clocks is added to the head of the video data VDATA for 936 clocks.
NSEQ is added and follows the video data WDATA 16
The clock portion is an unused area. ID for 8 clocks
The same ID data is continuously written in the data area.

FIG. 7 shows the structure of the field memory 19. In the figure, 19a is a memory cell having a structure of 306 rows × 960 columns × 8 bits, 19b is an input buffer, 19c is a write address counter, and 19d1,1.
9d2 is a read address counter, and 19e1 and 19e2
Is the output buffer. The write data WDATA is transferred to the memory cell 19a via the input buffer 19b. The write enable signal WE is supplied to the input buffer 19b and the write clock WMC is supplied.
K is supplied. In this case, write data WDATA
Is accepted at the rising timing of the write clock WMCK when the write enable signal WE is at the low level “L”, and is not accepted when the write enable signal WE is at the high level “H”.

The write address counter 19c has a write clock WMCK, a horizontal clear signal HCLR0,
Vertical clear signal VCLR0 and increment signal I
NC0 is supplied. The count value of the counter 19c is supplied to the memory cell 19a as write address data. In this case, the horizontal clear signal HCLR0 controls the horizontal direction, and the vertical clear signal VCLR0 and the increment signal INC0 control the vertical direction.

Further, the read address counter 19d
Read clocks RMCK are provided at 1 and 19d2, respectively.
1, RMCK2, horizontal clear signals HCLR1, HCLR
2. Vertical clear signals VCLR1 and VCLR2 and increment signals INC1 and INC2 are supplied. The count values of the counters 19d1 and 19d2 are supplied to the memory cell 19a as read address data of 0H port and 1H port, respectively. In this case, the horizontal clear signals HCLR1 and HCLR2 control the horizontal direction, and the vertical clear signals VCLR1 and VCLR2 and the increment signals INC1 and INC2 control the vertical direction.

Read data RDATA1, RDA output from the 0H port and 1H port of the memory cell 19a.
TA2 is output via the output buffers 19e1 and 19e2, respectively. In this case, the 0H port is used for normal read and the 1H port is 1 for normal read.
It is used for reading that is delayed by the horizontal period. for that reason,
The common clock RMCK is used for the read clocks RMCK1 and RMCK2, and the horizontal clear signal HCLR is used.
A common horizontal clear signal HCLR is used for 1 and HCLR2, and a common increment signal INC is used for increment signals INC1 and INC2. The vertical clear signal VCLR2 is delayed by one horizontal period from the vertical clear signal VCLR1.

Read data RDATA1, RDATA obtained at the 0H port and 1H port of the memory cell 19a.
2 is output via the output buffers 19e1 and 19e2, respectively. The output buffers 19e1 and 19e2 are supplied with the read clocks RMCK1 and RMCK2 and the read enable signals RE1 and RE2, respectively. The output buffers 19e1 and 19e2 are three-state outputs.

Therefore, the read enable signal RE
When RE1 and RE2 are at a low level "L", the read clocks RMCK1 and RMCK2 are enabled from the output sides of the output buffers 19e1 and 19e2, respectively, in the enable state.
Read data RDATA1, RDATA2 in synchronization with
Is output. On the other hand, the read enable signal RE1,
When RE2 is high level "H", output buffer 1
The outputs of 9e1 and 19e2 are in a high impedance state. In this example, the read enable signals RE1,
RE2 is fixed at the low level "L", and the output buffers 19e1 and 19e2 are always enabled.

FIG. 8 shows a write operation to the field memory 19. The same figure A shows the write side composite sync signal WCSYNC, the same figure B shows the write side clock WCK (same as the sampling clock ADCLK) formed in synchronization with the composite sync signal WCSYNC, and the same figure C shows the clock WCK and the phase inversion relationship. Write clock WMC
K, the same D is the vertical clear signal VCLR0, the same E is the horizontal clear signal HCLR0, and the same F is the increment signal I.
NC0 and G in the figure are write data WDATA.

The write address counter 19c is supplied with the vertical clear signal VCLR0 to return the write address to the first line of the memory cell 19a, and the counter 19c is supplied with the horizontal clear signal HCLR0 to supply the line of the memory cell 19a. Return to the top of. The vertical clear signal VCLR0 is the input video signal N
It is supplied on the 11th line when the TSC system is used and at the timing of the 166th clock, while it is supplied on the 10th line when the input video signal is the PAL system and 190
It is supplied at the timing of the clock. The horizontal clear signal HCLR0 is supplied at the timing of the 166th clock when the input video signal is the NTSC system.
On the other hand, when the input video signal is of the PAL system, it is supplied at the timing of the 190th clock.

As described above, the input video signal is NTS.
It has been explained that when the C system is used, the video data is written to the memory 19 from the 166th clock, and when the input video signal is the PAL system, the video data is written to the memory 19 from the 190th clock ( (Refer to FIG. 5). Actually, the conversion processing by the conversion circuits 5 and 16 and the processing of the multiplexers 6, 17 and 18
Since there is a delay by the clock, the horizontal clear signal HCLR is supplied at the timing of the 166th clock when the input video signal is the NTSC system, and at the timing of the 190th clock when the input video signal is the PAL system. The ID data ODD / EVE for 8 clocks added to the beginning of the video data VDATA
All the write data WDATA of each line including N and SUBNSEQ are written in the memory 19 (see FIG. 6).

When the increment signal INC0 is supplied to the counter 19c, the line of the write address is incremented. The increment signal INC0 is the next horizontal clear signal HCLR0 after the input of a certain horizontal clear signal HCLR0.
Is supplied only once until is input. In this example, the increment signal INC0 is supplied at the timing of the 169th clock when the input video signal is the NTSC system, and is supplied at the timing of the 193rd clock when the input video signal is the PAL system.

When the input video signal is of the NTSC system, the horizontal clear signal HCLR0 and the increment signal INC0 are not supplied to the 260th line in the odd field, so that the writing from the 261st line onward is not performed, while the even field is 261st. Since the horizontal clear signal HCLR0 and the increment signal INC0 are not supplied to the line, writing is not performed for the line 262 and thereafter. Further, when the input video signal is of the PAL system, the horizontal clear signal HCLR0 and the increment signal INC0 are not supplied to the 310th line in the odd and even fields, so that the writing from the 311th line onward is not performed.

9 and 10 show the field memory 1
The read operation from 9 is shown. 9A shows a read side composite sync signal RCSYNC, and FIG. 9B shows a read clock R formed in synchronization with the composite sync signal RCSYNC.
MCK1, RMCK2, and C in the figure are vertical clear signals VCL
R1, VCLR2, D in the figure shows a horizontal clear signal HCLR
1, HCLR2, read data RDATA
1, RDATA2, F in the same figure are increment signals INC
1 and INC2. 10A shows a vertical synchronizing signal RVD on the reading side, and FIG. 10B shows a horizontal synchronizing signal RH on the reading side.
D and C in the figure are vertical clear signals VCLR1, and D in the figure are vertical clear signals VCLR2.

Read address counters 19d1 and 19
Vertical clear signals VCLR1 and VCLR2 are applied to d2, respectively.
Is supplied, the read address returns to the first line of the memory cell 19a, and the counter 19d
Horizontal clear signals HCLR1 and HC to 1 and 19d2, respectively
By supplying LR2, the read address returns to the beginning of the line of the memory cell 19a.

The vertical clear signal VCLR1 is the 13th line (275) when the output video signal is the NTSC system.
Line) and at the timing of the 75.5th clock. On the other hand, when the output video signal is the PAL system, it is supplied at the 18th line (the 330th line) and at the timing of the 93.5th clock. . Further, the vertical clear signal VCLR2 is the 14th line (276th line) when the output video signal is the NTSC system, and is 7
It is supplied at the timing of the 5.5th clock. On the other hand, when the output video signal is the PAL system, the 19th line (33
It is supplied on the first line) and at the timing of the 93.5th clock. Then, the output buffers 19e1 and 19e2
Read data RD from the 140th clock
ATA1 and RDATA2 are obtained.

Further, by supplying the increment signals INC1 and INC2 to the counters 19d1 and d2, the line of the read address is incremented. The increment signals INC1 and INC2 are after the input of certain horizontal clear signals HCLR1 and HCLR2, and the next horizontal clear signals HCLR1 and HCLR.
One is basically supplied until 2 is input.

As will be described later, the input video signal is NTS.
When the output video signal in the C method is the PAL method and the number of lines is about 5: 6 when converting from 525 lines to 625 lines, the same line should be read at a ratio of 1 line to 5 lines (2 Reading is done).
In this case, assuming that one horizontal period of the NTSC system and the PAL system is the same and the ratio of the number of lines is 5: 6, 1
Since the ratio of the number of fields that can be displayed per second is 6: 5, if the number of lines is converted at the ratio of 5: 6, the number of fields is naturally converted to the ratio of 6: 5.

On the contrary, if the input video signal is the PAL system and the output video signal is the NTSC system, 625 lines to 5
When converting to 25 lines, the number of lines is about 6: 5.
Therefore, the line is skipped and read out (thinning out) at a rate of 1 line out of every 6 lines. In this case, assuming that one horizontal period of the PAL system and the NTSC system is the same and the ratio of the number of lines is 6: 5, the ratio of the number of fields that can be displayed in one second is 5: 6. If the conversion is performed with the ratio of 6: 5, the number of fields is naturally converted into the ratio of 5: 6.

As described above, the double reading can be performed by not supplying the increment signals INC1 and INC2 described above. On the other hand, the thinning-out can be performed by supplying two increment signals INC1 and INC2 described above. FIG. 9F shows the increment signal INC.
The figure shows the case of supplying 1 and 1 INC2, for example, at the timing of the 516.5th clock. When two increment signals INC1 and INC2 are supplied, they are supplied, for example, at the timing of the 518.5th clock in addition to the timing of the 516.5th clock.

When the input video signal and the output video signal are of the NTSC system or the PAL system and the number of lines is not converted, after a certain horizontal clear signal HCLR1 and HCLR2 is input, The supply of one unit is repeated until the horizontal clear signals HCLR1 and HCLR2 are input.

Returning to FIG. 1 and FIG. 2, read data RDATA1, R output from the field memory 19 is read.
DATA2 is supplied to the latch circuits 21Y1 and 21Y2, respectively. Latch pulses YLT0 and YLT1 are supplied to the latch circuits 21Y1 and 21Y2, and the luminance data is latched from the read data RDATA1 and RDATA2, respectively. As described above, the line offset subsampling is substantially performed on the luminance data by the processing on the writing side of the memory 19. This line offset sub-sampling is performed in order to sufficiently obtain the resolution of the luminance signal from the limited data amount.

Here, the line offset subsampling will be briefly described. First, as shown in FIG. 11A, atomic sampling is performed at a frequency of fs.
“●” is a sampling point, n, n + 1, n + 2, ...
Indicates the line number. Then, as shown in FIG. 9B, data is thinned out for each sample, and an offset for one sample is provided for each line. “X” mark indicates thinned sample points. At this point the amount of data is 1 /
It becomes 2. When this is seen in the frequency domain, a folding component (hatched portion) occurs around fs / 2 as shown in FIG.

As shown in FIG. 11D, in order to reproduce the high frequency component lost by folding after writing and reading the signal in which the data amount is half and the folding component is superimposed in the memory 19 as described above, the signal is reproduced. Further, the sampling points may be interpolated by the high frequency components of the adjacent lines. “◯” indicates the interpolated sample points. In other words, the high-frequency components are opposite in phase due to the offset between a certain line and its adjacent line, so by adding the high-frequency component of the line adjacent to it to the signal of a certain line, the lost high-frequency component is It can be reproduced. However, the addition here means not the simple addition but the synthesis by the switching sample hold.

FIG. 12 is a diagram showing this.
The same figure A shows the signal of a certain line on which the folding component (hatched portion) is superimposed, and the same figure B shows the high frequency component of the adjacent line. Therefore, by adding the high frequency component of the line adjacent to the signal of a certain line, the aliasing component is removed and the high frequency component is reproduced as shown in FIG.

Returning to FIG. 2, the latch circuits 21Y1 and 21Y1
The luminance data latched by Y2 is supplied to the high-pass filters 22Y1 and 22Y2, respectively. The high frequency components extracted by the high pass filters 22Y1 and 22Y2 are supplied to the a side and the b side of the changeover switch 23, respectively. The changeover control signal SW3 is supplied to the changeover switch 23, and the high frequency components extracted by the high pass filters 22Y1 and 22Y2 are alternately selected. As a result, the high frequency components of a certain line and the line adjacent thereto are combined by the changeover switch 23 to reproduce the high frequency components. The high frequency component output from the changeover switch 23 is supplied to the adder 24.

The luminance data latched by the latch circuits 21Y1 and 21Y2 are respectively delayed by the delay circuit 2 for time adjustment.
It is supplied to the subtractors 26Y1 and 26Y2 via 5Y1 and 25Y2. The high frequency components extracted by the high pass filters 22Y1 and 22Y2 are supplied to the subtractors 26Y1 and 26Y2, respectively. In this case, the high pass filter 22Y
1, the delay circuit 25Y1 and the subtractor 26Y1 form a low-pass filter and a high-pass filter 22Y.
2, the delay circuit 25Y2 and the subtractor 26Y2 form a low-pass filter. Therefore, the subtractors 26Y1, 26
From Y2, low-frequency components extracted from the luminance data latched by the latch circuits 21Y1 and 21Y2 are obtained, and these low-frequency components are rounded by limiters 27Y1 and 27Y2 to obtain 8-bit data, and the coefficient ROM28Y1 is obtained. , 2
It is supplied to 8Y2.

As described above, the input video signal is NTS.
When the output video signal in the C system is the PAL system and the conversion is performed from 525 lines to 625 lines, two lines are read at a rate of one line for every five lines. Conversely, if the input video signal is the PAL system and the output video signal is the NTSC system and conversion is performed from 625 lines to 525 lines, 6
Thinning is performed at the rate of one line per line.

When the number of lines is converted, if the lines are simply read twice and thinned out repeatedly, diagonal lines become discontinuous and graphic distortion occurs. Therefore, in this example, the memory 1
The read data RDATA1 and RDATA2 of two adjacent lines output in parallel from 9 are calculated, and line interpolation processing is performed so that the distances between the lines become equal.

In this case, since the number of fields is converted in accordance with the conversion of the number of lines as described above, the line that was an odd field at the time of writing to the memory 19 becomes an even field at the time of writing, or an even field at the time of writing. However, the lines interpolated at this time become vertical jitter because the upper and lower lines are reversed for each field.
In order to prevent this vertical jitter, in this example, when the read line is different from the field at the time of writing, the line is shifted by one line, and the interlace interpolation for shifting the line for double reading or thinning is performed. Be done.

FIG. 13 shows the states of line interpolation and interlace interpolation when the input video signal is the NTSC system and the output video signal is the PAL system and conversion is performed from 525 lines to 625 lines. In the figure,
"○" and "□" are odd numbers (OD
D) shows the positions of field lines and even (EVEN) field lines. Further, “●” and “Δ” respectively indicate the positions of the odd field lines and the even field lines obtained by the interpolation.

For example, when a line that was an odd field at the time of writing is read to an odd field,
Lines 2 and 1 are read out and coefficients k = 0,
(1-k) = 6/6 is multiplied and then added to form the line-●. Next, the lines 2 and 1 are read out and multiplied by the coefficients k = 5/6 and (1-k) = 1/6, respectively, and then added to form a line − ●. In this case, the lines 1 and 2 are read twice. Next, the lines 3 and 2 are read out, and the coefficients k = 4/6 and (1-k) = 2/6 are respectively multiplied and then added to form a line − ●. Then line 4,
3 is read out and the coefficient k = 3/6, (1-
k) = 3/6 is multiplied and then added to obtain the line −
● is formed. Next, the lines 5 and 4 are read out, and the coefficients k = 2/6 and (1-k) = 4/6 are respectively multiplied and then added to form a line − ●. Next, the lines 6 and 5 are read out and the coefficient k = 1
/ 6, (1-k) = 5/6 are multiplied and then added to form a line-●. Hereinafter, the interpolation line is formed by repeating the above. The same applies when a line that was an even field at the time of writing is read to an even field.

Here, it is assumed that the lines 2 and 1 are read in the even field to obtain the line -Δ. However, if the read line is not the even field but the odd field lines 2 and 1, the -Δ interpolation line cannot be obtained from these two lines. In such a case, the read line is shifted by one line,
Lines 1 and 0 are read and the coefficient k = 3 /
6, (1−k) = 3/6 are multiplied and then added to form the line −Δ. In this way, when a line that was an odd field at the time of writing is read to an even field, the line is shifted by one line and interpolated by changing the coefficient to be multiplied. The one-line shift operation is executed by stopping the supply of only one increment signal INC1 and INC2 described above.

In this case, the lines 1 and 0 are read out, and the coefficients k = 3/6 and (1-k) = 3/6 are respectively multiplied and then added to form the line -Δ. Next, the lines 2 and 1 are read and the coefficient k = 2
/ 6, (1−k) = 4/6 are multiplied and then added to form the line −Δ. Next, the lines 3 and 2 are read out, and the coefficients k = 1/6 and (1-k) = 5 for the respective lines.
/ 6 is multiplied and then added to form the line -Δ. Next, the lines 4 and 3 are read out, and the coefficients k = 0 and (1−k) = 6/6 are respectively multiplied and added to form a line −Δ. Then line 4,
3 is read out and the coefficient k = 5/6, (1-
k) = 1/6 is multiplied and then added to obtain the line −
Δ is formed. In this case, the lines 4 and 3 are read twice. Next, the lines 5 and 4 are read out, and the coefficients k = 4/6 and (1-k) = 2/6 are respectively multiplied and then added to form a line -Δ. Hereinafter, the interpolation line is formed by repeating the above.

On the contrary, in the odd field, the lines 2 and 1 are read to obtain the line −. However, when the read line is not the odd field but the even field lines 2 and 1, the interpolated line of-● cannot be obtained from the two lines unless the coefficient is changed. In such a case, the lines 1 and 2 are read without shifting the read line and the coefficient k
= 3/6, (1-k) = 3/6 are multiplied and then added to form a line-●. In this way, when a line that was an even field at the time of writing is read to an odd field, interlace interpolation is performed by changing the coefficient to be multiplied.

In this case, the lines 2 and 1 are read out, and the coefficients k = 3/6 and (1-k) = 3/6 are respectively multiplied and added to form the line-●. Next, lines 3 and 2 are read out, and the coefficient k = 2
/ 6, (1-k) = 4/6 are multiplied and then added to form a line-●. Next, the lines 4 and 3 are read out, and the coefficients k = 1/6 and (1-k) = 5 are read into the respective lines.
/ 6 is multiplied and then added to form the line-●. Next, the lines 5 and 4 are read out, and the coefficients k = 0 and (1−k) = 6/6 are respectively multiplied and added to form a line − ●. Next, line 5,
4 are read out, and coefficients k = 5/6, (1-
k) = 1/6 is multiplied and then added to obtain the line −
● is formed. In this case, the lines 5 and 4 will be read twice. Next, the lines 6 and 5 are read out, and the coefficients k = 4/6 and (1-k) = 2/6 are respectively multiplied and then added to form a line − ●. Hereinafter, the interpolation line is formed by repeating the above.
In addition, in FIG. 13, a double part of “◯” and “□” indicates a double reading line.

FIG. 14 shows the state of line interpolation and interlace interpolation when the input video signal is the PAL system and the output video signal is the NTSC system and conversion is performed from 625 lines to 525 lines. In the figure,
“O” and “□” respectively indicate the positions of the odd field line and the even field line during writing. Further, “●” and “Δ” respectively indicate the positions of the odd field lines and the even field lines obtained by the interpolation.

For example, when a line that was an odd field at the time of writing is read to an odd field,
Lines 2 and 1 are read out and coefficients k = 0,
(1-k) = 6/6 is multiplied and then added to form the line-●. Next, the lines 3 and 2 are read out, and the coefficients k = 1/6 and (1-k) = 5/6 are respectively multiplied and then added to form the line − ●. Next, the lines 4 and 3 are read out, and the coefficients k = 3/6 and (1-k) = 3/6 are respectively multiplied and then added to form a line − ●. Next, line 5,
4 is read out and the coefficient k = 3/6, (1-
k) = 3/6 is multiplied and then added to obtain the line −
● is formed. Next, the lines 6 and 5 are read out, and the coefficients k = 5/6 and (1-k) = 1/6 are respectively multiplied and added to form a line − ●. Next, the lines 8 and 7 are read out and the coefficient k =
0, (1−k) = 6/6 are multiplied and then added to form a line − ●. In this case, the lines 7 and 6 are thinned out. Hereinafter, the interpolation line is formed by repeating the above. The same applies when a line that was an even field at the time of writing is read to an even field.

Here, it is assumed that the lines 2 and 1 are read in the even field to obtain the line -Δ. However, if the read line is not the even field but the odd field lines 2 and 1, the -Δ interpolation line cannot be obtained from these two lines. In such a case, the read line is shifted by one line,
Lines 1 and 0 are read and the coefficient k = 3 /
6, (1−k) = 3/6 are multiplied and then added to form the line −Δ. In this way, when a line that was an odd field at the time of writing is read to an even field, the line is shifted by one line and interpolated by changing the coefficient to be multiplied.

In this case, the lines 1 and 0 are read out, and the coefficients k = 3/6 and (1-k) = 3/6 are respectively multiplied and then added to form the line -Δ. Next, the lines 2 and 1 are read out, and the coefficient k = 4 is read for each.
/ 6, (1−k) = 2/6 are multiplied and then added to form the line −Δ. Next, the lines 4 and 3 are read out, and the coefficients k = 0 and (1−k) = 6/6 are read out respectively.
Are multiplied and then added to form the line -Δ. In this case, the lines 3 and 2 are thinned out. Next, the lines 5 and 4 are read out, and the coefficients k = 0 and (1−k) = 6/6 are respectively multiplied and then added to form a line −Δ. Next, the lines 6 and 5 are read out and the coefficients k = 2/6 and (1-k) =
4/6 are multiplied and then added to form the line-[Delta]. Hereinafter, the interpolation line is formed by repeating the above.

On the contrary, in the odd field, the lines 2 and 1 are read to obtain the line −. However, when the read line is not the odd field but the even field lines 2 and 1, the interpolated line of-● cannot be obtained from the two lines unless the coefficient is changed. In such a case, the lines 2 and 1 are read out without shifting the read line and the coefficient k
= 3/6, (1-k) = 3/6 are multiplied and then added to form a line-●. In this way, when a line that was an even field at the time of writing is read to an odd field, interlace interpolation is performed by changing the coefficient to be multiplied.

In this case, the lines 2 and 1 are read out, and the coefficients k = 3/6 and (1-k) = 3/6 are multiplied respectively and then added to form the line −. Next, lines 3 and 2 are read out, and the coefficient k = 4 is read for each.
/ 6, (1-k) = 2/6 are multiplied and then added to form a line-●. Next, the lines 5 and 4 are read out, and the coefficients k = 0 and (1-k) = 6/6 are read into the respective lines.
Are multiplied and then added to form a line- ●. In this case, the lines 4 and 3 are thinned out. Next, the lines 6 and 5 are read out, and the coefficients k = 0 and (1−k) = 6/6 are respectively multiplied and then added to form the line − ●. Next, the lines 7 and 6 are read out and the coefficients k = 2/6 and (1-k) =
They are multiplied by 4/6 and then added to form the line- ●. Hereinafter, the interpolation line is formed by repeating the above. In addition, in FIG. 14, double portions of “◯” and “□” indicate thinning lines.

As described above, when a line which was an odd field at the time of writing is read to an even field, or when a line which is an even field at the time of writing is read to an odd field, that is, when field inversion occurs. 1 line shift and coefficient change operations are performed.

When the field inversion occurs during the vertical blanking period, the 1-line shift operation is performed during the vertical blanking period. When the field inversion occurs during the video signal period, V rattling appears on the screen. Since it is difficult to predict from which position (line) the field inversion occurs, V rattling is reduced by selecting the coefficient that is the closest to the desired interpolation line for the first line where the field inversion occurs suddenly. However, it is known from the next line that the field has already been inverted, so the one-line shift operation is performed.

The operation when field inversion occurs during the video signal period will be described with reference to FIG. For example, assume that when lines 5 and 4 of an even field are read, field inversion occurs here and lines 5 and 4 of an odd field are read. The desired interpolation line is at the position of-△, but at this point the operation of shifting by one line is not possible, so the coefficient of line 6/6,
Line 5 is multiplied by a coefficient of 0 to be most approximated to the position of -Δ. Then, a desired interpolation line can be obtained by performing a 1-line shift operation from the next line.

As described above, if the position of the read line of the memory 19 and the relationship between the field at the time of writing data and the field at the time of reading data are known, interlaced interpolation becomes possible.
As described above, in this example, the ID data ODD / EVEN indicating whether the data in the horizontal blanking period is the odd field or the even field is used as the write data WDATA.
Is inserted, and the occurrence of field inversion is detected in the horizontal period on the reading side, as will be described later. Even if not mentioned above, if the method is not converted, k = 0, (1-
k) = 6/6.

If the input video signal is the PAL system and the output video signal is the NTSC system, 625 lines to 5
When converting to 25 lines, it is thinned out at a ratio of 1 line to 6 lines, so originally, 0, 1/5, ..., 5/5
By using a total of 6 coefficient data up to, it is possible to perform the line interpolation processing with high accuracy. However, in that case, in addition to the coefficient data 0, 1/6, ..., 6/6, the coefficient data of 0, 1/5 ,. Coefficient ROM 28Y1, 28 described above
Coefficient control data CFD1, C supplied to Y2
FD2 becomes 4-bit data, and when input data is 8-bit and output data is 8-bit, coefficient RO
8 bits x 4096 words x as M28Y1 and 28Y2
A capacity of 2 is required.

Therefore, in this example, when the input video signal is the PAL system and the output video signal is the NTSC system and the conversion is performed from 625 lines to 525 lines, the coefficient data 0, 1/6 ,. By using / 6 (see FIG. 14), coefficient control data CFD1, C
FD2 is set to 3-bit data, and coefficient ROM 28
The capacity of Y1 and 28Y2 is halved.

Returning to FIG. 2, the coefficient ROMs 28Y1 and 28Y2 each have coefficient control data C formed based on the position of the read line of the memory 19 and the relationship between the data writing and reading fields.
FD1 and CFD2 are supplied. Coefficient ROM 28Y1,
The output data obtained by multiplying the input data by the coefficients k and (1-k) is obtained from 28Y2, and the respective output data are added by the adder 29 to obtain the luminance data of the interpolation line.

The luminance data of 9-bit low-frequency component output from the adder 29 is rounded by the limiter 30 to be 8-bit data, and then supplied to the adder 24 to be added with the luminance data of high-frequency component. It The 9-bit luminance data RADY output from the adder 24 is rounded by the limiter 31 into 8-bit data as shown in FIG. 3, rounded by the rounding circuit 32, and blanked by the blanking addition circuit 33. The ranking signal RBLK is added, and the sync addition circuit 34 further adds the composite sync signal RCS.
After YNC is added, it is supplied to the conversion circuit 35. Then, after being converted from 2's complement display to normal binary display by the conversion circuit 35, it is converted into an analog signal by the D / A converter 36 and derived as a luminance signal Yout at the output terminal 37.

FIG. 15 shows the configuration of the luminance system from the latch circuits 21Y1 and 21Y2 to the limiter 31. 15, parts corresponding to those in FIGS. 2 and 3 are designated by the same reference numerals. FIG. 16A shows frequency characteristics of the high pass filters 22Y1 and 22Y2, and FIG.
Shows the frequency characteristics of the low-pass filter composed of the high-pass filter 22Y1, the delay circuit 25Y1 and the subtractor 26Y1, and the low-pass filter composed of the high-pass filter 22Y2, the delay circuit 25Y2 and the subtractor 26Y2.

As described above, the sub-sampling process improves the high frequency component of the luminance signal, and the line interpolation process improves the graphic distortion. Since both of these two processes operate between two adjacent lines, generally the sub-sampling process is performed first. This is because if the line interpolation process is performed first, a coefficient is also applied to the high frequency components of each line, and the effect of the subsampling process changes line by line. The sub-sampling process is originally a process for improving high frequency components, while the line interpolation process (including interlace interpolation process) reduces low frequency components such as improvement of diagonal jaggedness and vertical direction jitter. This is a process for improving. Therefore, in the present example, as described above, the line interpolation processing and the interlace interpolation processing that perform the coefficient operation only on the low frequency component are performed, and the high frequency component is not subjected to the coefficient operation and only the sub-sampling processing is performed. It

The point to be noted here is that the low-frequency components extracted by the low-pass filter and output from the subtracters 26Y1 and 26Y2 are 1 / fs (fs is the sampling frequency, which is the sampling frequency in the horizontal direction. Then read clock R
It is the same as the frequency of MCK), so that the addition of the two lines forms a horizontal low-pass filter. The transfer function is H _(z)
= 1 + Z ⁻¹ . In practice, the low-frequency component is multiplied by the coefficient and added, so that the transfer function is as follows.

H _(z) = k × (1/4 + Z ⁻² / 2 + Z ⁻⁴ / 4) + (1−k) × (Z ⁻¹ / 4 + Z ⁻³ / 2 + Z ^{−5 /4)...(1} ) However, k = 6 / 6,5 / 6,4 / 6,3 / 6,2 /
It is 6, 1/6, 0. 17A, B, 18A, B
Shows the low-pass filter characteristics when the coefficient k is changed. Although the characteristics change depending on the difference in the coefficient, it can be seen that all are affected in the band of fs / 4 or more. FIG. 17A is the same as when the coefficient k is 6/6, 0, that is, when normal sub-sampling is performed, and in FIG. 18B, when the coefficient k is 3/6, the highest high frequency component is dropped. . If the high frequency component is dropped, it naturally affects the band reproduced by subsampling, but −
The point at 3 dB is fs / 3, which is about 5.9 MHz when the sampling frequency fs is 17.734 MHz. This is sufficient as a band of a normal television signal, which is 470 TV lines in terms of resolution.

FIG. 19 shows how the low frequency component and the high frequency component are reproduced by the sub-sampling process of this example. A in the figure is a signal of a certain line on which a folded component (hatched portion) is superimposed (a low-frequency component is multiplied by a coefficient k), and B in the same figure is a signal of an adjacent line (a low-frequency component). The components are multiplied by the factor 1-k).
Therefore, by adding the signal of the line adjacent to the signal of a certain line, the low frequency component and the high frequency component are reproduced as shown in FIG.

As described above, in this example, the line interpolation process and the interlace interpolation process are performed only on the low frequency component, and it is possible to obtain the high resolution image quality with the improved graphic distortion, and the circuit configuration is simplified. (See FIG. 15).

Returning to FIG. 2, read data RDATA1 and RDATA2 output from the field memory 19 are read.
Are supplied to the latch circuits 41R1 and 41R2, respectively. Latch pulse RL is applied to the latch circuits 41R1 and 41R2.
T0 and RLT1 are supplied, and the red color difference data is latched from the read data RDATA1 and RDATA2, respectively.

The red color difference data output from the latch circuits 41R1 and 41R2 are respectively up-convert circuits 42R.
Supplied to 1,42R2. As described above, in the video data VDATA written in the field memory 19, the sample data of the red color difference data and the blue color difference data is arranged at a ratio of one in four (see FIGS. 4H and 4M). Therefore, the sample rate of the red color difference data and the blue color difference data latched from the read data RDATA1 and RDATA2 is fs / 4.

In the up-converting circuits 42R1 and 42R2, the sampling rate of the red color difference data is up-converted from fs / 4 to fs by the interpolation processing and the filtering processing. Up-conversion circuit 42R1, 42R2
The red color difference data output from the above is supplied to the adder 43R, added and averaged, and then supplied to the fixed terminal on the c side of the changeover switch 44R. The red-difference data output from the up-conversion circuit 42R2 is supplied to the t-side fixed terminal of the changeover switch 44R. The changeover switch 44R has a system conversion (NTSC → PAL or PAL → NTS).
A conversion instruction signal CONV indicating whether to perform C) is supplied as a switching control signal. In this case, the changeover switch 44
R is connected to the c side when the system conversion is performed, and is connected to the t side when the system conversion is not performed.

The read data RDATA1 and RDATA2 output from the field memory 19 are supplied to the latch circuits 41B1 and 41B2, respectively. Latch pulses BLT0 and BL are applied to the latch circuits 41B1 and 41B2.
T1 is supplied and read data RDATA is supplied to each.
1, blue difference data is latched from RDATA2.

The blue color difference data output from the latch circuits 41B1 and 41B2 are respectively up-convert circuits 42B.
At 1, 42B2, the sample rate is up-converted from fs / 4 to fs, then added and averaged by the adder 43B and supplied to the fixed terminal on the c side of the changeover switch 44B. The blue difference data output from the up-conversion circuit 42B2 is supplied to the fixed terminal on the t side of the changeover switch 44B. The conversion instruction signal CONV is supplied to the changeover switch 44B.
Is supplied as a switching control signal, and is connected to the c side when the system conversion is performed, and is connected to the t side when the system conversion is not performed.

The red color difference data RADR, RADB output from the changeover switches 44R, 44B are changed over by the changeover switches 46R, 46B after the blanking signal RBLK is added by the blanking addition circuits 45R, 45B as shown in FIG. A side fixed terminal and changeover switch 4
It is supplied to the a-side fixed terminal of 7R and 47B. Burst level signals (red color difference data and blue color difference data) are supplied from the burst level circuits 48R and 48B to the fixed terminals on the b side of the changeover switches 47R and 47B, respectively.

The burst level circuits 48R and 48B include
A system identification signal Rn / p indicating whether the output video signal is the NTSC system or the PAL system is supplied. As a result, burst level circuits 48R and 48B output burst level signals corresponding to the output video signal system.

The burst gate pulse RBGP is supplied to the changeover switches 47R and 47B as a changeover control signal. The changeover switches 47R and 47B are connected to the b side during the burst period, and are connected to the a side during the other periods. The color difference data RADR, RADB added with the burst level signals output from the changeover switches 47R, 47B is supplied to the chroma encoder 50 via the chroma asynchronous circuit 49.

Reference numeral 51 is an oscillator circuit, and the oscillator circuit 51 includes an NTSC system 4fsc (14.318 MH).
crystal oscillator 52n and PA having an oscillation frequency of z)
A crystal oscillator 52p having an L-system 4 fsc (17.734 MHz) oscillation frequency is connected. The system identification signal Rn / p is supplied to the oscillator circuit 51 as an oscillation frequency switching control signal, and the output video signal from the oscillator circuit 51 is NT.
When the SC system is used, the frequency is 4 fsc of the NTSC system, and when the output video signal is the PAL system, P is used.
Encoder clock E with 4 fsc frequency in AL system
NCK is output.

The encoder clock ENCK output from the oscillation circuit 51 is supplied to the chroma asynchronous circuit 49 and the chroma encoder 50. Also, the chroma asynchronous circuit 4
A read-side clock RCK is supplied to 9. Also,
The chroma encoder 50 is supplied with a blanking signal PBLK as well as a V-axis inversion control signal PALT for controlling V-axis inversion in color modulation when the output video signal is of the PAL system. The blanking signal PBLK is supplied as a switching control signal for separating and outputting the burst signal and the modulated chroma signal as described later.

In the chroma encoder 50, the encoder clock ENCK is used, and the color difference data RY, B-
Color modulation processing is performed by arranging Y,-(RY), and-(BY) as shown in FIG. In addition, R-
V-axis inversion can be performed by reversing the positions of Y and-(RY).

In this example, the read side clock RC
K is selected as 4 fsc (17.734 MHz) of the PAL system. In this case, when the output video signal is the PAL system, all the circuits can be operated in synchronization. However, when the output video signal is the NTSC system, 4fsc of the NTSC system is 14.318 MHz.
Therefore, the chroma encoder 50 and the signal processing circuit in the preceding stage are operated asynchronously.

The problem at this time is that when 8-bit data changes the clock, each of the data can become indefinite. When indefiniteness occurs, it appears as noise on the screen and makes it unsightly. Therefore, in this example, by providing the chroma asynchronous circuit 49 between the chroma encoder 50 and the signal processing circuit in the preceding stage,
Prevents the generation of indefinite data.

FIG. 21 shows the chroma asynchronous circuit 49. In the figure, the red color difference data RADR output from the changeover switch 47R is the D flip-flop 491R.
It is supplied to the data terminal D of 1,491R2. The blue color difference data RADB output from the changeover switch 47B is supplied to the data terminal D of the D flip-flops 491B1 and 491B2.

The read clock RCK is supplied to the clock terminal of the D flip-flop 492. The output data of the inverted output terminal Q bar of the D flip-flop 492 is supplied to the enable terminal EN bar of the D flip-flops 491R1 and 491B1 and the data terminal D of the D flip-flop 492. Also,
The output data of the non-inverted output terminal Q of the D flip-flop 492 is supplied to the enable terminal EN bar of the D flip-flops 491R2 and 491B2 and the data terminal D of the D flip-flop 494. D flip-flops 491R1, 491R2, 491B1, 491
The read side clock RCK is supplied to the clock terminal of B2, and the read side clock RCK is supplied to the inverter 493 of the clock terminal of the D flip-flop 494.
Is inverted and supplied.

In addition, the D flip-flops 491R1 and 4
The output data from the non-inverting output terminal Q of the 91R2, 491B1 and 491B2 are the D flip-flops 495R1 and 495R1, respectively.
The output data of the non-inverting output terminal Q of the D flip-flop 494 is supplied to the data terminal D of the 495R2, 495B1, and 495B2.
Is supplied to the data terminal D. D flip-flop 49
The encoder clock ENCK is supplied to the clock terminals of 5R1, 495R2, 495B1, 495B2, and 496.

D flip-flops 495R1 and 49
The output data from the non-inverted output terminal Q of 5R2 is supplied to the fixed terminals on the L and H sides of the changeover switch 497R, respectively. Also, D flip-flops 495B1 and 495B2
The output data of the non-judgment output terminal Q are supplied to fixed terminals on the L side and the H side of the changeover switch 497B, respectively.
A select pulse SPb is supplied as a switching control signal from the non-inverting output terminal Q of the D flip-flop 496 to each of the changeover switches 497R and 497B. That is,
The changeover switches 497R and 497B are operated by selecting pulse S
When Pb is low level “L”, it is connected to the L side,
When it is at the high level “H”, it is connected to the H side.

The output data of the changeover switches 497R and 497B are the D flip-flops 498R and 498B, respectively.
Is supplied to the data terminal D. The encoder clock ENCK is supplied to the clock terminals of these D flip-flops 498R and 498B. The output data from the non-inverted output terminals Q of the D flip-flops 498R and 498B are output as red color difference data AADR and blue color difference data AADB, which are synchronized with the encoder clock ENCK.

The operation of the chroma asynchronous circuit 49 will be briefly described below with reference to the timing chart of FIG.

When the output video signal is of the NTSC system, the read side clock RCK (17.
Color difference data RA sent at a rate of 734 MHz)
DR (shown in B in the same figure) is directly used as the encoder clock E
When sampling is performed at NCK (14.318 MHz), the data change point and the clock rising point match at a certain timing. In this case, since the setup time or hold time of the flip-flop is not sufficient, the output data becomes indefinite.

In the chroma asynchronous circuit 49 of FIG. 21, the red difference data RAD is generated by the asynchronous encoder clock ENCK.
17.734MHz because R is always latched once
D-type flip-flops 491R1 and 491R2 form parallel data Da and Db (shown in FIGS. 22D and 22E) of two systems at half the rate from the red color difference data RADR of that rate. FIG. 22C shows the output data Dq of the inverting output terminal Q bar of the D flip-flop 492.

Two systems of parallel data Da and Db formed by the D flip-flops 491R1 and 49R2 are supplied to the D flip-flops 495R1 and 495R2, respectively, and latched by the encoder clock ENCK (shown in FIG. 22G). Then, the D flip-flop 495R1,
Two parallel data D latched by 495R2
c and Dd (shown in FIGS. 22H and 22I) are changeover switches 47R
It is returned to 1 system.

Here, after the D flip-flop 494 forms the select pulse SPa (shown in FIG. 22F) that matches the sequence of the parallel data Da and Db of the two systems, the D flip-flop 496 outputs the encoder clock E.
A select pulse SPb (illustrated in FIG. 22J) that is normalized by NCK and is supplied to the changeover switch 497R is formed.

In this case, even if the select pulse SPb or the parallel data Dc, Dd is indefinite as described above, the changeover switch 497R needs to select the data accurately latched by the D flip-flops 495R1, 495R2. There is. Therefore, as in this example, it is desirable to form the select pulse SPa so that the pulse change point has the largest margin with respect to the change points of the parallel data Da and Db. FIG. 23 is an enlarged view showing the timing relationship between the parallel data Da and Db and the select pulse SPa. fs is the sample rate of the red color difference data RADR.

After being converted into one-system data by the changeover switch 497R, it is latched by the D flip-flop 498R to obtain the red color difference data AADR (shown in FIG. 22K) synchronized with the encoder clock ENCK. Figure 2
In 2H and I, the data Dc and Dd are indefinite (illustrated by a mark X), but the finally obtained red difference data AAD
The indefinite part does not occur in R.

Here, when the encoder clock ENCK has the timing shown in FIG. 22L, the parallel data D
c and Dd are as shown in M and N of FIG. Consider a case where the select pulse SPb is originally at the high level "H" due to a timing error but at the low level "L" (hatched in FIG. 22O). In this case, the red difference data AADR (shown in FIG. 22P) is missing data for one cycle, but no indefinite portion is generated, so that the generation of noise can be avoided. Even in such an operation, there is no problem because the band of the chroma signal is about 1 MHz, which is sufficiently lower than 14.318 MHz.

In the above description, the encoder clock ENC
The case of obtaining the red color difference data AADR synchronized with K has been described, but the detailed description is omitted, but the operation of obtaining the blue color difference data AADB is also the same. When the output video signal is of the PAL system, the encoder clock ENCK is PAL.
The color difference data A synchronized with the encoder clock ENCK is also obtained from the chroma asynchronous circuit 49.
ADR and AADB are obtained.

Returning to FIG. 3, the modulated chroma signal Cm and the burst signal Sb output from the chroma encoder 50.
Are supplied to fixed terminals on the b side of the changeover switches 46R and 46B, respectively. A read mode control signal RMODC is supplied to the changeover switches 46R and 46B from a system controller (not shown). The change-over switches 46R and 46B are connected to the a side when the color difference signals RY and BY are output to the output terminals 55R and 55B, which will be described later, while the modulation chroma signal Cm and the burst signal Sb.
When outputting in the form of, it is connected to the b side.

The output data of the changeover switches 46R and 46B are converted from the two's complement display to the normal binary display by the conversion circuits 53R and 53B, respectively, and then the D / A converter 5 is used.
Output terminal 55 after being converted into an analog signal by 4R and 54B
The chroma signals Cout1 and Cout2 are derived to R and 55B. In this case, when the changeover switches 46R and 46B are connected to the side a, the chroma signals Cout1 and Cout2 become color difference signals RY and BY, respectively. On the other hand, the changeover switch 46
When R and 46B are connected to the b side, chroma signal Cout
1 and Cout2 become the modulated chroma signal Cm and the burst signal Sb, respectively.

Reference numeral 56 is a clock select circuit. The select circuit 56 is supplied with the encoder clock ENCK from the oscillator circuit 51 and the read clock R.
CK is supplied. The read mode control signal RMODC is supplied to the select circuit 56 as a switching control signal,
The select circuit 56 outputs the read clock RCK when outputting to the output terminals 55R and 55B in the form of color difference signals RY and BY, while the modulation chroma signal Cm,
When outputting in the form of the burst signal Sb, the encoder clock ENCK is output. And the select circuit 5
The clock output from 6 is the D / A converter 54R,
54B is supplied as a sampling clock.

As described above, the modulated chroma signal Cm and the burst signal Sb can be separately output to the output terminals 55R and 55B as the chroma signals Cout1 and Cout2, respectively, which allows color gain control and hue on the output side. Easy to control. It is possible to digitally control the gain and the hue by the chroma encoder 50 from the outside, but there are problems that the number of terminals for that purpose is increased and the circuit configuration becomes complicated. It is also possible to control the gain and the hue with an analog circuit for the modulated chroma signal added with the burst signal, but there is a problem that the circuit configuration becomes complicated.

The chroma signal Cou is output to the output terminals 55R and 55B.
Modulated chroma signal Cm and burst signal S as t1 and Cout2
When b is output, a modulated chroma signal with a burst, that is, a carrier color signal can be obtained by adding these with a mix amplifier 57. In this case, the gain can be controlled by controlling the synthesis ratio of the mix amplifier 57, and the hue can be changed by inserting a phase shifter (not shown) into either the burst signal Sb or the modulation chroma signal Cm. You can control.

The carrier chrominance signal output from the mix amplifier 57 is a bandpass filter 5 whose center frequency is the color subcarrier frequency of the NTSC system and the PAL system, respectively.
8N, 58P through the n side of the changeover switch 59 and p
Side fixed terminal. The system identification signal Rn / p is supplied to the changeover switch 59 as a changeover control signal. The changeover switch 59 is connected to the n side when the output video signal is in the NTSC system, and is connected to the p side when the output video signal is in the PAL system. Therefore, the changeover switch 59 obtains the carrier color signal of the system designated by the system identification signal Rn / p. The carrier color signal output from the changeover switch 59 is added by the adder 60 to the low-pass filter 61.
Is added to the luminance signal Yout whose band is limited by
A video signal SV of C system or PAL system is obtained.

In general, as described above, the bandpass filters 58N and 58N are set in accordance with the output video signal system.
It is necessary to switch between P and P, but since the up-convert processing by the above-mentioned up-conversion circuits 42R1, 42R2, 42B1 and 42B2 can make the filter characteristic on the output side a wide range (broad) characteristic, both the NTSC method and the PAL method are available. It is also possible to commonly use one band pass filter.

Next, the structure of a control signal generation system for forming various control signals used in the above-mentioned signal processing system will be described with reference to the drawings.

FIG. 24 shows a write-side clock generation circuit. In the figure, the composite sync signal WCSYNC separated by the sync separation circuit (not shown) from the luminance signal Y supplied to the input terminal 1 (see FIG. 1) is supplied to the half H killer circuit 65 to remove the equivalent pulse. The generated reference horizontal synchronizing signal REFHD is formed. The synchronization signal REFHD output from the half H killer circuit 65 is supplied to the phase difference detection circuits 66 and 67.

Further, 68 is a voltage controlled oscillator, and an oscillation signal (clock WCK) output from this oscillator 68.
Is supplied as a count clock to the horizontal counter 69 and the vertical counter 70. The internal horizontal synchronizing signal INTHD output from the horizontal counter 69 is supplied to the phase difference detecting circuit 66, and a pulse of one clock width synchronized with the internal horizontal synchronizing signal INTHD is output from the horizontal counter 69 to the vertical counter 70 as an enable signal. Supplied as.

Reference numeral 71 is an external vertical reset circuit, and the vertical synchronizing signal WVSYNC separated from the luminance signal Y by the sync separating circuit is supplied to the reset circuit 71. In the reset circuit 71, a reset pulse having a one-clock width synchronized with the vertical synchronizing signal WVSYNC is formed and supplied to the fixed terminal on the b side of the changeover switch 72. Also,
Reference numeral 73 denotes a vertical synchronizing signal generating circuit.
RF switching pulse R from rotary head type VTR
FSWP is supplied. In the generating circuit 73, pulse RFS
A vertical synchronizing pulse VD having a one-clock width synchronized with WP is formed and supplied to the fixed terminal on the side a of the changeover switch 72.

When the input video signal (luminance signal Y and chroma signal C supplied to the input terminals 1 and 7 (see FIG. 1)) of the VTR is in the VTR JOG mode (slow mode, cue / review mode), the changeover switch 72 is operated. A JOG mode identification signal SJOG indicating whether or not the reproduction signal is a switching control signal. The changeover switch 72 is connected to the a side when the input video signal is a reproduction signal in the JOG mode, and is connected to the b side otherwise.

The pulse output from the changeover switch 72 is supplied to the reset terminal of the vertical counter 70. As a result, the vertical counter 70 outputs the vertical synchronization signal WVSYNC.
Alternatively, the counting operation is performed in synchronization with the RF switching pulse RFSWP, and the internal vertical synchronization signal INTVD
Is formed. The vertical synchronizing signal WVSYNC separated from the reproduction signal in the VTR JOG mode is disturbed, but in the present example, the vertical synchronizing pulse VD formed based on the RF switching pulse RFSWP which is stably obtained in the JOG mode. Since the vertical counter 70 is reset by, the vertical counter 70 can be stably reset even if the input video signal is a reproduction signal in the VTR JOG mode.

Reference numeral 74 denotes an external horizontal reset circuit. The reset circuit 74 is supplied with a gate pulse having a width of one horizontal period in synchronization with the internal vertical synchronizing signal INTVD from the vertical counter 70. Further, the reset circuit 74 receives the reference horizontal synchronizing signal REFH from the half H killer circuit 65.
A pulse having a width of 1 clock is supplied in synchronization with D. Then, the 1-clock-width pulse gated by the gate pulse in the reset circuit 74 is supplied as a reset pulse to the horizontal counter 69 via the adder 63 and the side b of the changeover switch 64.

The internal horizontal synchronizing signal INTHD output from the horizontal counter 69 is reset, and a fixed number of clocks WCK output from the oscillator 68 (1128 when the input video signal is the NTSC system,
The internal reset pulse INTRP obtained by counting only the number of 1152 in the PAL system) is supplied to the horizontal counter 69 via the adder 63 and the b side of the changeover switch 64. As a result, the horizontal counter 70
Then, the counting operation is performed in synchronization with the internal vertical synchronizing signal INTVD and in synchronization with the internal reset pulse INTRP to form the internal horizontal synchronizing signal INTHD.

Reference numeral 62 is a JOG horizontal reset circuit. The reset circuit 62 includes a half H killer circuit 65.
Further, a pulse having a width of 1 clock is supplied in synchronization with the reference horizontal synchronization signal REFHD, and the internal reset pulse I
NTRP is supplied. The reset circuit 62 is supplied with an envelope detection signal ENVDET described later. The reset circuit 62 outputs an envelope detection signal E, which will be described later.
The pulse supplied from the half H killer circuit 65 is extracted during the period when NVDET is at the low level “L” and the field memory 19 is in the write state, and the reset terminal of the horizontal counter 69 is passed through the a side of the changeover switch 64. Is supplied to. Also, the envelope detection signal ENVDET
Is at the high level "H", the reset circuit 62
The internal reset pulse INTRP is further output and supplied to the reset terminal of the horizontal counter 69 via the a side of the changeover switch 64.

The changeover switch 64 is supplied with the JOG mode identification signal SJOG as a changeover control signal. When the input video signal is a reproduction signal in the JOG mode, it is connected to the a side, and when it is not, it is connected to the b side. It As a result, when the input video signal is a reproduction signal in the VTR JOG mode, when the envelope detection signal ENVDET is at the low level “L” and the field memory 19 is in the writing state, the half H killer circuit 65 is provided to the horizontal counter 69. The output pulse is supplied as a reset pulse, and the horizontal H counter 69 is forcibly reset in synchronization with the external horizontal synchronizing signal (reference synchronizing signal REFHD).

The synchronizing signals INTHD and INTVD output from the counters 69 and 70 are supplied to the comparison inhibiting circuit 75. In the comparison prohibiting circuit 75, the synchronizing signals INTHD, IN
The comparison prohibited section is set based on TVD. Regarding the horizontal direction, it is set in the comparison prohibited section except for the 1/4 horizontal period before and after the falling timing of the synchronizing signal INTHD. Further, in the vertical direction, a predetermined period before and after the vertical synchronization signal is set as a comparison prohibited section. From the comparison prohibition circuit 75, the comparison prohibition signal C of high level "H" is generated in the comparison prohibition section.
MPIB is output (see FIGS. 25C and 26C). Note that FIG. 25B shows an internal horizontal synchronization signal INTHD,
26A shows the composite synchronizing signal WCSYNC, FIG. 26B shows the vertical synchronizing signal WVSYNC, and FIG. 26D shows the reset pulse output from the external horizontal reset circuit 74.
Comparison prohibition signal CMPI output from comparison prohibition circuit 75
B is supplied to the phase difference detection circuits 66 and 67.

The phase difference detection circuit 66 detects the phase difference between the reference horizontal synchronizing signal REFHD and the internal horizontal synchronizing signal INTHD. In this case, when the synchronization signal INTHD is delayed with respect to the synchronization signal REFHD, the synchronization signal RE
A high-level “H” signal P is output from the fall of FHD to the fall of the sync signal INTHD,
Conversely, when the sync signal INTHD is ahead of the sync signal REFHD, the signal N of high level "H" is output from the falling time of the sync signal INTHD to the falling time of the sync signal REFHD.

The signals P and N output from the phase difference detection circuit 66 are supplied to the phase comparison circuit 76. The phase comparison circuit 76 outputs a signal PHER that is lower than the reference level during the period in which the signal P is supplied and is higher than the reference level during the period in which the signal N is supplied. Here, the reference synchronization signal REFHD is shown in FIG.
, The signals P and N are output from the phase difference detection circuit 66 as shown in D and E of the same figure, and the signal PHER is obtained from the phase comparison circuit 76 as shown in F of the same figure. The signal PHER output from the phase comparator 76 is supplied as a phase error signal to the adder 78 via the low-pass filter 77 composed of an inverting amplifier.

The phase difference detecting circuit 67 detects the phase difference between the reference horizontal synchronizing signal REFHD and the comparison prohibiting signal CMPIB. From the phase difference detection circuit 67, the synchronization signal REF is output from the falling point of the comparison inhibit signal CMPIB.
A signal SPER that is higher than the reference level until the trailing edge of HD and that is lower than the reference level from the trailing edge of the sync signal REFHD to the leading edge of the comparison inhibit signal CMPIB is obtained. Here, when the reference synchronization signal REFHD is as shown in FIG. 25A, the signal SPER is obtained from the phase difference detection circuit 67 as shown in FIG. The signal SPER output from the phase difference detection circuit 67 is added as a speed error signal via a low pass filter 79 composed of an inverting amplifier to an adder 78.
Is supplied to.

In the adder 78, the low pass filters 77, 7
The phase error signal and the speed error signal output from 9 are added, and the added signal is sent to the oscillator 68 as a control signal VC.
Supplied as OIN. FIG. 27 shows the oscillation characteristic of the oscillator 68, and the oscillation frequency increases as the control signal VCOIN increases. Here, the reference horizontal synchronization signal R
When the internal horizontal synchronizing signal INTHD is delayed with respect to EFHD, the level of the control signal VCOIN is increased and the oscillation frequency of the oscillator 68 is increased to increase the internal horizontal synchronizing signal IN.
The THD phase is controlled so as to advance. On the other hand, with respect to the reference horizontal synchronization signal REFHD, the internal horizontal synchronization signal INTH
When D advances, the level of the control signal VCOIN decreases, the oscillation frequency of the oscillator 68 decreases, and the phase of the internal horizontal synchronizing signal INTHD is delayed.

As a result, the internal horizontal synchronizing signal INTHD
The AFC operation is performed so that the phase lock of the reference horizontal synchronization signal REFHD with the reference horizontal synchronization signal REFHD. In the phase control operation described above, the speed error signal SPER is used to roughly control the oscillation frequency of the oscillator 68 so that the phase is easily locked, while the phase error signal PHER is used to phase lock the oscillation frequency of the oscillator 68. Used for fine control.

As described above, the phase difference detection circuit 6
The comparison prohibition signal CMPIB is supplied to 6 and 67, the phase difference detection operation is not performed in the comparison prohibition section, and the output side is in the high impedance state. This is for stabilizing the AFC operation even when the input video signal is a VTR reproduction signal or the like and the horizontal sync signal is disturbed at the time of dropout or head switching.

However, since the oscillator 68 is in the free-run state in the vertical comparison prohibition section, if the phase of the internal horizontal synchronizing signal INTHD is extremely deviated from the reference horizontal synchronizing signal REFHD after the start of comparison, It takes time for the AFC operation to stabilize, and the effect appears at the top of the screen. Therefore, in this example, the horizontal horizontal counter 69 is provided by the external horizontal reset circuit 74 to the reset pulse synchronized with the reference horizontal synchronization signal REFHD on the line immediately before the start of comparison.
To the reference horizontal synchronizing signal REFH (see FIG. 26D).
By synchronizing the internal horizontal synchronizing signal INTHD with D, the AFC operation is stabilized.

As described above, since the horizontal counter 69 is reset by the reset pulse INTRP, the internal horizontal synchronizing signal INTHD with respect to the reference horizontal synchronizing signal REFHD.
With the phase locked, the horizontal frequency fh and the oscillator 6
The frequency f of the write-side clock WCK output from 8
The relationship with wck is fwck = 1128fh when the input video signal is the NTSC system and fwck = 1152fh when the input video signal is the PAL system.
The write-side clock WCK is inverted by the inverter 80, and the write clock WM is written to the field memory 19.
Supplied as CK.

Horizontal frequency fh and write side clock WC
The reason for setting the relationship of the frequency fwck of K as described above is as follows. In this example, the frequency of the read-side clock RCK is set to 4 fsc of the PAL system during system conversion.
It is assumed that Therefore, when the frequency of the read clock RCK is frck, frck = 1135fh is set when the output video signal is the PAL system, and frck = 1128fh is set when the output video signal is the NTSC system. . At this time, the effective video signal period on the read side in the NTSC system and the PAL system is as shown in FIGS. 28A and 28B.

As described above, the field memory 19 has a maximum capacity of 960 samples in the horizontal direction. Memory 19
The more the data of the video signal written in, the better, but in this example, as described above, the video data VDA
In addition to TA, ID data (ODD / EVEN, SUBNS
EQ) is also written (see FIG. 6), and the video data is multiplexed data of luminance data and chrominance point sequential data (see FIGS. 4H and 4M). Therefore, in the NTSC system, the effective video signal period is 4 Frck = 1128fh is set so that it becomes a multiple of 936 clocks.

However, when the input video signal is of the PAL system, setting fwck = 1135fh causes inconvenience. That is, when fwck = 1135fh is set, the effective video signal period becomes about 924 clocks, and when this is converted into the NTSC system, 12 samples (936-9).
The data for 24) will be insufficient. If this shortage is to be supplemented by, for example, extending the blanking period, the blanking portion may be visible on the screen.
Therefore, in this example, the number of samples of the effective video signal period written in the memory 19 is 936 in both the NTSC system and the PAL system. Therefore, fwck = 1152fh is set as described above so that the effective video signal period is 936 clocks when the input video signal is of the PAL system. 29A and 29B show the effective video signal periods on the read side in the NTSC system and the PAL system, respectively.

As described above, frck = 1128f
By setting as h, fh = frck / 1128 = 15.
It becomes 722 KHz, which is slightly deviated from the original horizontal frequency of 15.734 KHz of the NTSC system, but it is about -12 Hz, and there is no problem at all considering that there is a sufficient margin in the synchronizing circuit such as the receiver.

Next, the configuration of the write side and read side control circuits of the field memory 19 will be described with reference to FIGS. 30 and 31.

In FIG. 30, reference numeral 81 is a write address control circuit, and 82 is a write timing generation circuit. The address control circuit 81 and the timing generation circuit 82 have synchronization signals INTHD and INT output from counters 69 and 70 (see FIG. 24), respectively.
A system identification signal Wn / indicating whether the input video signal is the NTSC system or the PAL system while VD is supplied.
p is supplied.

Then, the address control circuit 81 outputs a horizontal clear signal HCL0 and a vertical clear signal VCL0 for writing control of the field memory 19 according to the system of the input video signal, and the field memory 19 is output.
(As shown in FIG. 1) (see FIG. 8). Under the control of the address control circuit 81, the increment circuit 83 outputs one increment signal for each line, and the increment circuit 84 outputs two increment signals for each line. The increment signals output from the increment circuits 83 and 84 are supplied to the field memory 19 as the write control increment signal INC0 via the a side and the b side of the changeover switch 85, respectively.

Further, the address control circuit 81 outputs horizontal clear signals THCR1, THCR2, vertical clear signals TVCR1, TVCR2 and increment signals TINC1, TINC2 for read control during non-conversion, according to the system of the input video signal. (See FIGS. 9 and 10). In this case, the increment signal TINC
Only one of 1 and TINC2 is output in each line.

Further, in the timing generation circuit 82, the number is reset by the internal horizontal synchronizing signal INTHD and the number (11 in the NTSC system) according to the system of the input video signal is reset.
28 clocks, 1152 clocks in PAL system) WC
K is counted and the internal reset pulse INTRP is formed. The internal reset pulse INTRP is supplied to the horizontal counter 69 via the adder 63 as described above (see FIG. 24).

Further, the timing generation circuit 82 outputs the sampling clock ADCLK and the clamp pulse YCL.
P, select signals SELR and SELB, switching control signals SW1 and SW2, and ID data ODD / EVEN,
SUBNSEQ is output and supplied to the corresponding location on the write side. Also, the timing generation circuit 82
From the blanking signal TRBLK and burst gate pulse TRBGP used on the read side during non-conversion.
Is output.

Reference numeral 90 denotes a conversion / non-conversion discriminating circuit, which is supplied with the system discriminating signal Wn / p of the input video signal and the system discriminating signal Rn / p of the output video signal. The determination circuit 90 outputs a conversion instruction signal CONV indicating whether or not to convert the system, and the conversion instruction signal CONV is supplied to the changeover switches 44R and 44B as a changeover control signal (see FIG. 2).

Reference numeral 91 denotes a mode discriminating circuit which determines whether the input video signal is a VTR reproduction signal and the VTR is in the JOG mode (slow mode, cue / review mode). A JOG mode identification signal SJOG that indicates and a still mode identification signal SSTL that indicates whether or not to use the still mode are supplied. Discrimination circuit 9
1 outputs a mode identification signal SMOD capable of individually identifying the JOG mode and the still mode described above.

The conversion instruction signal CONV output from the conversion / non-conversion determination circuit 90 and the mode identification signal SMOD output from the mode determination circuit 91 are the synchronous select circuit 9
2 is supplied. From the sync select circuit 92, for example, at the time of conversion and at the time of non-conversion, it is at the high level “H” in the JOG mode or the still mode (hereinafter referred to as “at the time of conversion”), and is not at the time of conversion. When neither the JOG mode nor the still mode (hereinafter referred to as "non-conversion, etc."), the sync select signal S which becomes the low level "L"
SEL is output.

Further, the conversion instruction signal CONV output from the conversion / non-conversion determination circuit 90 and the mode determination circuit 91.
The output mode identification signal SMOD is supplied to the mode change detection circuit 93. The detection circuit 93 outputs a mode change detection pulse PCHM in synchronization with the internal vertical synchronization signal INTVD when the normal state is entered and the JOG mode or the still mode is entered at the time of non-conversion.

A write enable control circuit 94 is supplied with the mode identification signal SMOD output from the mode discrimination circuit 91 and the input video signal is a VTR reproduction signal. The envelope detection signal ENVDET of the reproduction RF signal is supplied. The envelope detection signal ENVDET has a high level "H" in the noise portion and has a low level "L" in the signal portion. A write enable signal WE is output from the control circuit 94 and supplied to the field memory 19.

In this case, from the control circuit 94, the input video signal is not the reproduction signal in the VTR JOG mode,
Further, when not in the still mode, that is, in the normal operation, the write enable signal WE is continuously set to the low level "L". As a result, the write data WDATA is continuously written in the memory 19. The input video signal is a VTR reproduction signal and the VTR is a JOG.
The write enable signal WE in the mode and in the still mode will be described later.

The write enable signal WE output from the write enable control circuit 94 is supplied to the rising edge detection circuit 95. When the rising edge of the write enable signal WE is detected, the detection circuit 95 outputs an edge detection pulse PRED having a pulse width of one horizontal period in synchronization with the internal horizontal synchronization signal INTHD, and this edge detection pulse PRED is It is supplied to the changeover switch 85 as a changeover control signal. Changeover switch 8
5 is connected to the b side during the pulse width period of the edge detection pulse PRED, and is connected to the a side during the other periods.

During the above-described normal operation, the write enable signal WE continuously becomes low level "L",
The rising edge is not detected by the edge detection circuit 95, and the changeover switch 85 remains connected to the a side. As a result, in the normal operation, the address in the vertical direction is incremented by one line for each line and writing is performed.

In FIG. 31, reference numeral 100 denotes an oscillator circuit, and the oscillator circuit 100 has a 4fsc (1
Crystal oscillator 1 having an oscillation frequency of 7.734 MHz)
01 is connected. PA output from the oscillator circuit 100
A clock RCLK having a frequency of 4 fsc in the L system is supplied to a fixed terminal on the H side of the changeover switch 102. The read-side clock WCK is supplied to the fixed terminal on the L side of the changeover switch 102. A synchronous select signal SSEL output from the synchronous select circuit 92 (see FIG. 30) is supplied to the changeover switch 102 as a changeover control signal,
It is connected to the H side when the select signal SSEL is at a high level “H” during conversion or the like, and is connected to the L side when the select signal SSEL is at a low level “L” during non-conversion.

The clock output from the changeover switch 102 is the read side clock RCK. Therefore,
The clock RCLK having a frequency of 4 fsc in the PAL system is used as the read side clock RCK at the time of conversion, and the write side clock WCK is used as the read side clock RCK at the time of non-conversion. This read-side clock RCK is used as it is in the field memory 19 (see FIG.
(See reference) is supplied as a read clock RMCK.

The read side clock RCK output from the changeover switch 102 is supplied to the horizontal counter 103 and the vertical counter 104 as a count clock. The mode change detection pulse PCHM output from the mode change detection circuit 93 (see FIG. 30) is supplied to the counters 103 and 104 as a reset pulse via the adders 105 and 106, respectively. The horizontal synchronizing signal RHD output from the horizontal counter 103 is supplied to the read timing generation circuit 107 and the read address control circuit 108. Further, the horizontal counter 103 supplies a pulse of one clock width synchronized with the horizontal synchronizing signal RHD to the vertical counter 104 as an enable signal. Vertical sync signal V output from the vertical counter 104
The HD is supplied to the timing generation circuit 107 and the address control circuit 108.

The system identification signal Rn / p of the output video signal is supplied to the timing generation circuit 107 and the address control circuit 108. The timing generating circuit 107 is reset by the horizontal synchronizing signal RHD output from the horizontal counter 103, and the reading side clock R
An internal horizontal reset pulse HRP obtained by counting a fixed number of CKs (1128 when the input video signal is the NTSC system and 1135 when the input video signal is the PAL system) is supplied to the horizontal counter 10 via the adder 105.
3 is supplied.

From the timing generation circuit 107,
Vertical sync signal RVD output from the vertical counter 104
The horizontal synchronizing signal RHD is reset by a fixed number (525 when the input video signal is the NTSC system).
The internal vertical reset pulse VRP, which is obtained by counting the number of PALs, which is 625 in the PAL system), is supplied to the horizontal counter 104 via the adder 106.

Further, 109 is an ID latch circuit, and the read data RDATA1 from the field memory 19 is supplied to this ID latch circuit 109. In the ID latch circuit 109, the ID data SUBNSEQ indicating whether the line is an odd line or an even line is latched from the read data RDATA1, and the ID data SUBN
The SEQ is supplied to the timing generation circuit 107.

From the timing generation circuit 107, a blanking signal CRBL used on the read side at the time of conversion or the like.
K, burst gate pulse CRBGP, composite sync signal C
RCSYNC is output, and each switch 10
It is supplied to the fixed terminals on the H side of 9, 110, and 111. Blanking signal TRBLK and burst gate pulse TRBGP output from write timing generation circuit 82 (see FIG. 30) are supplied to fixed terminals on the L side of changeover switches 109 and 110, respectively, and changeover switch 111 is supplied.
To the fixed terminal on the H side of the
YNC is supplied.

A synchronous select signal SSEL output from the synchronous select circuit 92 (see FIG. 30) is supplied to the changeover switches 109, 110 and 111 as a changeover control signal, and the select signal SSEL is at a high level "H" at the time of conversion. Is connected to the H side, and when the select signal SSEL is at the low level “L” during non-conversion or the like, it is connected to the L side. The blanking signal RBLK, the burst gate pulse RBGP, and the composite synchronizing signal RCSYNC output from the changeover switches 109, 110, and 111 are supplied to the corresponding locations on the read side (see FIG. 3).

From the timing generation circuit 107,
Latch pulse YLT0, YLT1, RLT0, RLT
1, BLT0, BLT1, the switching control signal SW3, and the V-axis inversion control signal PALT are output and supplied to corresponding portions on the read side (see FIG. 3). Further, the timing generation circuit 107 outputs a field identification signal Ro / e indicating whether the read side is in an odd field or an even field.

Further, the address control circuit 108 is supplied with a line thinning control signal LDIM and a line double read control signal LINC output from a coefficient control ROM described later. Then, from the address control circuit 108, the synchronizing signals RHD, RVD and the control signals LDIM,
Horizontal clear signals CHCR1, CHCR2 and vertical clear signal CVCR used at the time of conversion based on LINC
1, CVCR2, increment signals CINC1, CI
NC2 is output (see FIGS. 9 and 10).

These horizontal clear signals CHCR1 and CHC
R2, vertical clear signals CVCR1 and CVCR2, and increment signals CINC1 and CINC2 are changeover switch 1
12 is supplied to the fixed terminal on the H side. To the fixed terminal on the L side of the changeover switch 112, the horizontal clear signals THCR1 and THCR used by the write address control circuit 81 (see FIG. 30) for non-conversion are output.
2. Vertical clear signals TVCR1 and TVCR2 and increment signals TINC1 and TINC2 are supplied.

A synchronous select signal S output from the synchronous select circuit 92 (see FIG. 30) is applied to the changeover switch 112.
SEL is supplied as a switching control signal and is connected to the H side when the select signal SSEL is at a high level “H” during conversion, and L when the select signal SSEL is at a low level “L” during non-conversion. Connected to the side. Horizontal clear signals HCLR1 and H output from the changeover switch 112
The CLR2, the vertical clear signals VCLR1 and VCLR2, and the increment signals INC1 and INC2 are supplied to the field memory 19 (see FIG. 1). However, since the horizontal clear signals HCLR1 and HCLR2 have the same timing, they are supplied to the memory 19 as the common signal HCLR. Similarly, since the increment signals INC1 and INC2 have the same timing, the memory 1 is used as the common signal INC.
9 is supplied.

As described above, when the input video signal is NTSC
When the output video signal is the PAL system and the conversion is made from 525 lines to 625 lines, one line is read every 5 lines, and the input video signal is the PAL system and the output video signal is NTSC. Method 6
When converting from 25 lines to 525 lines, thinning is performed at a ratio of 1 line to 6 lines.

From the address control circuit 108,
When the output video signal is in the PAL system, it indicates which line of the 6-line cycle of the output line,
When the output video signal is of the NTSC system, a 3-bit line address signal LAD indicating which line of the output line is in the 5-line cycle is output.

Next, referring to FIG. 32, the coefficient ROM 28
A circuit for generating coefficient control data CFD1, CFD2, etc. supplied to Y1, 28Y2 (see FIG. 2) will be described. In the figure, reference numeral 120 is a coefficient control ROM in which coefficient control data CFD1 and CFD2 are stored in advance. In the ROM 120, the 3-bit line address LAD output from the read address control circuit 108 (see FIG. 31), the field identification signal Ro / e output from the read timing generation circuit 107 (see FIG. 31), the conversion / non-conversion. Conversion discrimination circuit 90
(Shown in FIG. 30) output conversion instruction signal CON
V, a system identification signal Rn / p indicating whether the output video signal is the NTSC system or the PAL system is supplied.

The read data RDATA1 and RDATAD2 output from the field memory 19 are supplied to the ID latch circuit 121. In the ID latch circuit 121, an ID indicating whether the read line is an odd field line or an even field line at the time of writing based on the read data RDATA1 and RDATA2.
The data ODD / EVEN is latched.

Data Wo / e1 (ID data ODD / EVEN latched from read data RDATA1) and data Wo / e2 output from the ID latch circuit 121.
(ID data ODD / EVEN latched from the read data RDATA2) is supplied to the exclusive OR circuit (hereinafter referred to as “EX-OR circuit”) 122. The EX-OR circuit 122 outputs a high level “H” signal when the read line changes from an odd field line to an even field line or from an even field line to an odd field line. This signal is a start line detection of field inversion. It is supplied to the ROM 120 as the signal OSTR.

The data Wo / e1 output from the ID latch circuit 121 is supplied to the EX-OR circuit 123.
The EX-OR circuit 123 has a field identification signal Ro /
e is also supplied. From the EX-OR circuit 123, a field inversion determination signal FCOM that becomes a high level “H” when the field on the read side does not match the field at the time of writing the read line and field inversion occurs.
P is output, and the discrimination signal FCOMP is stored in the ROM 120.
Is supplied to.

The field inversion determination signal FCOMP output from the EX-OR circuit 123 is supplied to the AND circuit 124 together with the field identification signal Ro / e. Then, the AND circuit 124 outputs an inversion state identification signal OE / EO which indicates whether the field inversion is inverted from the odd field to the even field or from the even field to the odd field, and the identification signal OE / EO is output. It is supplied to the ROM 120.

From the ROM 120, whether the system is converted as described above based on various signals supplied, whether the system of the output video signal is the NTSC system or the PAL system, and the field inversion. Coefficient ROMs 28Y1 and 28Y2 depending on whether or not the occurrence has occurred and which field has changed from field to field by field inversion.
Control data CFD1, CFD supplied to
2 is output, and the line thinning control signal LDIM and line double read control signal LINC supplied to the read address control circuit 108 (see FIG. 31) are output.

Next, the still mode will be described. In the still mode, a high level “H” signal is supplied to the mode discrimination circuit 91 as the still mode identification signal SSTL. Therefore, the mode identification signal SMOD output from the mode determination circuit 91 indicates the still mode, and the write enable signal WE output from the write enable control circuit 94 becomes a high level “H” signal.

Therefore, the field memory 19 (see FIG.
Since the writing to the read data RDATA1, RD is not performed, the data in the memory 19 does not change.
The same data is repeatedly output as ATA2 for each field. Therefore, a still image output video signal can be obtained.

As described above, in this example, the oscillation circuit 1 is used as the read side clock RCK in the still mode.
A clock RCLK having a frequency of 4 fsc in the PAL system from 00 (see FIG. 31) is used. Since this clock RCLK is used from the beginning during conversion of the system, it is not necessary to replace the sync signal, but during non-conversion the replacement of the sync signal is required. Therefore, when entering the still mode from the normal operation state, the vertical sync signal is not disturbed because it is not necessary to transfer the sync signal at the time of conversion, but the vertical sync signal is disturbed because it is necessary to replace the sync signal at the time of non-conversion. This causes a so-called V rattling on the screen.

In this example, when the still mode is entered from the normal operation state, the mode change detection circuit 93 (see FIG.
0)), the internal vertical synchronization signal INT on the write side when changing from the normal operation state to the still mode during non-conversion
A mode change detection pulse PCHM is output in synchronization with VD, and the horizontal counter 103 and the vertical counter 104 (see FIG. 31) on the read side are reset by this. Therefore, even when the still mode is entered from the normal operation state, the vertical sync signal is not disturbed, and it is possible to prevent V rattling. It should be noted that similar processing is performed when the JOG mode (slow mode, cue / review mode) described later is entered from the normal operation state.

Next, the case where the input video signal is the reproduction signal of the VTR and the VTR is in the cue (fast forward reproduction) mode or the review (rewind reproduction) mode will be described. In the cue / review mode, a high level “H” signal is supplied to the mode discrimination circuit 91 as the JOG mode identification signal SJOG. Therefore, the mode identification signal SMOD output from the mode determination circuit 91 is JOG.
It shows the mode.

In the write enable control circuit 94, the write enable signal WE which becomes high level "H" in the noise portion and low level "L" in the signal portion is output based on the envelope detection signal ENVDET of the reproduction RF signal. . FIG. 33D shows the write enable signal WE in the queue mode (6 × speed). Note that FIG. 33A shows an RF switching pulse RFSWP, and FIG. 33B shows a reproduced RF signal. Further, FIG. 6C shows an envelope detection signal ENVDET which has a high level “H” in the noise portion and a low level “L” in the signal portion. This allows the field memory 19 (shown in FIG. 1)
Only the signal portion will be written in.

By the way, generally, in the cue / review mode of the VTR, the position of the noise bar is fixed at the same position in the odd field and the even field, and the odd double speed is adopted in order to apparently reduce the number of noise bars to half. FIG. 34A shows the relationship between the tape pattern in the cue mode (4 × speed) and the head trace.
A1, B1, ... Respectively correspond to one track, a broken line a indicates a head trace during normal reproduction, and a solid line b indicates a head trace in cue mode. In addition, FIG.
The relationship between the switching pulse RFSWP and the reproduction RF signal is shown, and FIG. C shows the display screen.

On the other hand, FIG. 35A shows the relationship between the cue mode (3 × speed) tape pattern and the head trace, and the square portions A0, B0, A1, B1, ... Correspond to one track. The broken line a indicates the head trace during normal reproduction, and the solid line b indicates the cue mode head trace. Further, FIG. 9B shows the relationship between the RF switching pulse RFSWP and the reproduction RF signal, and FIG.
Indicates a display screen.

Although not described in detail, it is well known that the tapes are recorded on the tape so that the azimuths of the adjacent inclined recording tracks are different from each other. Signal reproduction is alternately performed from the inclined recording tracks by the first and second magnetic heads having azimuths corresponding to the recording azimuths. The recording azimuths of the portions A0, A1, ... And B0, B1 ,.

As described above, in this example, the field memory 1 is controlled by controlling the write enable signal WE.
9 (shown in FIG. 1) only the signal part is written,
In the VTR, the cue / review mode is set to an odd multiple speed, and the position of the noise bar is made different between the odd field and the even field, so that it is possible to configure one screen without noise bars with two fields.

The envelope detection signal ENVDET supplied to the write enable control circuit 94 is the reproduction R
It can be obtained by comparing the F signal with a predetermined threshold value, but it can also be formed by a microcomputer (not shown) based on the RF switching pulse RFSWP so that the write timing is fixed. Since the writing timing is constant, a calm screen can be obtained.

In this case, the microcomputer detects from the envelope detection signal ENVD which becomes a low level "L" at a preset timing according to the speed of the cue / review mode.
ET is output. FIG. 36C shows cue mode (6x speed)
In this case, the envelope detection signal ENVDET output from the microcomputer is shown. A in the figure is an RF switching pulse RFSWP, and B in the figure is a reproduction RF signal.

For example, the preset timing is a set value when the head width and the tape track width are the same and the tracking is optimum. Therefore, when a tape having a different track width with respect to the head width or a tape having a deviated tracking is reproduced, the set value becomes unsuitable and the S / N may be deteriorated or the noise bar may not be removed.
In such a case, the time of T1, T2, T3 in FIG. 36C may be adjusted by the microcomputer.

By the way, in the queue / review mode,
It is known that the number of lines in one field increases or decreases depending on the head trace position on the tape. That is, the number of lines is increased in the cue mode, the number of lines is decreased in the review mode, and becomes more remarkable as the double speed number is higher. As described above, since the number of lines decreases in the cue mode, if the synchronization signal corresponding to the regular number of lines is added after the writing and reading of the field memory 19 (shown in FIG. 1) as it is, it will occur at the end of the field. Not enough data.

FIG. 37A shows the state of write data on the field memory 19 in the queue mode.
There is a shortage of data for n lines (the hatched portion) with respect to the data for the normal line number. n varies depending on the speed number. FIG. 37B shows the output video signal after the synchronization signal is added, and becomes a noise in the lack of data.
Therefore, for example, on the television monitor side, there is a possibility that vertical synchronization signals may occur and vertical shake may occur.

In this example, as described above, the rising edge of the write enable signal WE is detected by the rising edge detection circuit 95 (see FIG. 30) and, for example, an edge of one horizontal period width is synchronized with the internal horizontal synchronizing signal INTHD. The detection pulse PRED is supplied to the changeover switch 85. Therefore, two increment signals output from the increment circuit 84 for only one line after the rising edge of the write enable signal WE is detected are supplied to the field memory 19 as the increment signal INC0 via the changeover switch 85.

Therefore, in this example, the write vertical address is incremented by 2 each time the write state (write enable signal WE is at the low level "L") is changed to the inhibit state (usually 1), The last data in the field is sequentially shifted to the rear, and the data comes to the noise part of the output video signal (see FIG. 37B). As a result, it is possible to prevent the above-described vertical shaking from occurring.

The operation of preventing vertical shaking in the cue mode described above will be further described with reference to FIG. For example, the address written in the h + 1 line next to the h line is increased by 2 in the vertical direction and written in the h + 2 line. By repeating such a process, the write address in the vertical direction on the memory 19 is shifted backward by the number of switching points (switching points from the write state to the prohibited state) in one field. It should be noted that the line (h + 1, i + 1, j + 1) in which the data is not updated is generated by increasing the two vertical addresses at the switching point, but since the tape running actually varies, the same line is used in each field. It does not appear as noise on the screen.

Although the number of lines in one field increases in the review mode as described above, in the present example, the rising edge detection circuit 95 (see FIG. 30) also outputs the edge detection pulse PRED in the review mode. As in the queue mode, vertical address control is performed. In the review mode, it is not necessary to perform such address control.Furthermore, contrary to the queue mode, the increase of the vertical address is eliminated every time the write state is changed to the prohibited state, and the image is vertically extended. It may be reduced.

Further, in the cue / review mode, the AFC operation is disturbed at the noise bar portion, so that the portion other than the noise bar is also affected. Even if it is written in the field memory 19 as it is, a skew will occur when it is reproduced.

Therefore, in the present example, the comparison prohibiting circuit 75
(See FIG. 24) is supplied with the envelope detection signal ENVDET, and the comparison inhibition circuit 75 outputs the comparison inhibition signal CMPIB of high level from the comparison inhibition circuit 75 during the period when the envelope detection signal ENVDET is at the high level “H”, that is, in the noise bar portion. Then, the phase difference detection circuits 66 and 67 are set in the comparison prohibited state.

On the other hand, the envelope detection signal ENVDET
Is at a low level "L", that is, in a portion other than the noise bar, the phase difference detection circuits 66 and 67 perform the comparison operation, and the JOG horizontal reset circuit 62 (see FIG. 2).
The horizontal counter 69 is forcibly reset by the reset pulse output from (see 4). As a result, the error signal is stabilized without being affected by the noise bar in the noise bar portion, and the horizontal counter 69 is controlled by the external horizontal synchronization signal (reference horizontal synchronization signal RE) in the signal portion.
Since it is forcibly synchronized with (FHD), data can be stably written in the field memory 19.

Also in the vertical direction, in the JOG mode, the vertical counter 70 is reset by the vertical sync signal generated by the RF switching pulse RFSWP in the vertical sync signal generating circuit 73 (see FIG. 24). This allows
It is possible to stabilize the writing position in the vertical direction.

33E shows a reset pulse to the horizontal counter 69 in the cue mode, FIG. 33F shows a reset pulse to the vertical counter 70, and FIG. 33G shows a comparison inhibit pulse CMPIB in the vertical direction. in this case,
Although not described above, in the portion where the reset pulse is supplied to the vertical counter 70, the comparison inhibit pulse CMPIB is set to the high level “H” and the write enable signal WE is set to the low level “L” to detect the phase difference even in the writing state. Circuit 6
In Nos. 6 and 67, the comparison is prohibited.

FIG. 39D shows a horizontal comparison prohibition signal C when the comparison section is in the vertical direction (the comparison prohibition signal CMPIB of FIG. 33G is at the low level “L”).
The state of MPIB is shown. It should be noted that FIG. A shows a reference horizontal synchronizing signal REFHD, and FIG. B shows an internal horizontal synchronizing signal INT.
HD and C in the same figure show the reset pulse to the horizontal counter 69. Further, FIG. 40D shows the state of the comparison prohibition signal CMPIB in the horizontal direction when it is in the comparison prohibition section (the comparison prohibition signal CMPIB of FIG. 33G is at the high level “H”) in the vertical direction. It should be noted that FIG. A shows a reference horizontal synchronizing signal REFHD, and FIG.
NTHD, C in the figure shows a reset pulse to the horizontal counter 69.

By the way, FIG. 41 shows a recording track pattern in the LP mode (double mode) of the PAL system in a VTR, for example. In this case, the so-called H
There is no arranging, and there is a shift of 0.5H between every other recording tracks that have the same recording azimuth. Therefore, in the cue / review mode, a discontinuity occurs in the horizontal synchronizing signal of the reproduction signal, and when the AFC operation is performed, an image flows horizontally on the display screen as shown in FIG. 42A, but the AFC operation is performed. If not, the display screen is as shown in FIG.

In this example, as described above, the horizontal counter 69 is forcibly reset by the external horizontal synchronizing signal (reference horizontal synchronizing signal REFHD) in the portion where there is a signal, so that the normal position of the field memory 19 is set to the normal position of each line. The video data can be stably written, and it is possible to prevent image distortion from occurring on the display screen even if the horizontal synchronizing signal of the reproduction signal becomes discontinuous. That is, even if there is a 0.5H shift as shown in FIGS. 43A and 43B, the horizontal counter 69 is reset in synchronization with the horizontal synchronization signal REFHD as described above, so that the write data WDATA of both lines is reset as shown in FIG. Both can be written in the regular position of the memory 19.

Next, the case where the input video signal is a reproduction signal in the slow mode of the VTR will be described. In this case, the slow mode of the VTR is the intermittent feed method. In this example, a write pulse having a pulse width of one field period is supplied to the write enable control circuit 94 (see FIG. 30) as the envelope detection signal ENVDET after the servo is stabilized after the tape running is stopped (illustrated in FIG. 45C). ). Therefore, the field memory 1
The write data WDATA for one field is written in 9 when the tape is stopped, and
Since data is asynchronously read from the device and an output video signal is obtained, it is possible to prevent the occurrence of image shake and noise that occur in the slow mode of the conventional intermittent feed system.

FIG. 45A shows the ON signal CAPON of the capstan motor in the 1/5 speed slow mode.
At the low level "L" portion, the capstan motor (not shown) of the VTR is turned on to control the running of the tape. Further, FIG. 9B shows an RF switching pulse RF
SWP and D in the figure show the write enable signal WE.

Further, in this example, as described above, the clamp pulse YCLP is supplied to the clamp circuit 3 (see FIG. 1) from the write timing generation circuit 82 (see FIG. 30) to perform the pedestal clamp. When the signal is the reproduction signal in the VTR JOG mode, the clamp pulse YCLP is generated only in the reproduction RF signal where the S / N ratio is good. In order to generate the clamp pulse YCLP in this way, the envelope detection signal ENVDET of the reproduction RF signal is supplied to the timing generation circuit 82, which is not shown in FIG. 30, and the clamp pulse YCLP is generated only in the low level "L" portion. To be done. Accordingly, in the clamp circuit 3, the clamp operation is not performed in the noise bar portion, so that the clamp voltage can be prevented from being disturbed.

However, the envelope detection signal ENVDE
When the high level “H” period of T becomes too long,
The clamp circuit 3 cannot hold the clamp voltage. For example, in the 1/10 times slow mode, the low level “L” period of the envelope signal ENVDET is 1
Since the period of the high level “H” is 19 fields with respect to the fields, the image becomes distorted when the clamp cannot be completed and time passes. Therefore, in this example, a sync tip clamp is also used together with the pedestal clamp (not shown), and the sync tip clamp works when the pedestal clamp is not performed by the clamp pulse YCLP. In this case, the sync tip clamp voltage is set to a value obtained by subtracting the sync level from the pedestal clamp voltage.

The above embodiment is based on the NTSC system and PAL.
Although it is possible to convert the system between the systems, the present invention is generally applicable to the system conversion between the 525/60 system and the 625/50 system, and further, the number of lines and the number of fields are different. Of course, it can be similarly applied to conversion between methods.

[0222]

According to the present invention, a memory having a storage capacity for one field is provided.
The memory capacity is small, and the cost can be reduced. In addition, the video data of the first and second lines that are continuous from the memory are read in parallel and coefficient calculation processing is performed to obtain the desired interpolated line, and when field inversion is detected, read as necessary. Interlace interpolation is performed by shifting the line by one line and shifting the double-reading or thinning-out line. Therefore, even if field inversion occurs, it is possible to reduce the occurrence of figure distortion due to double-reading or thinning-out of the line. it can.

Also, by adding field identification data for identifying a field at the time of writing to each line of the video data and detecting field inversion on a line-by-line basis using the field identification data, graphic distortion due to field inversion can be prevented. It is possible to immediately perform the read line shift processing or the like to reduce the load.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration (1/3) of an embodiment of a television system converter according to the present invention.

FIG. 2 is a block diagram showing a configuration (2/3) of an embodiment of a television system conversion apparatus according to the present invention.

FIG. 3 is a block diagram showing a configuration (3/3) of an embodiment of the television system conversion apparatus according to the present invention.

FIG. 4 is a diagram for explaining signal processing on the writing side of the memory.

FIG. 5 is a range written in a memory (NTSC system, P
It is a figure for explaining (AL system).

FIG. 6 is a diagram showing a configuration of write data WDATA for each line.

FIG. 7 is a block diagram showing a configuration of a field memory.

FIG. 8 is a diagram for explaining a write operation of the field memory.

FIG. 9 is a diagram for explaining a read operation of the field memory.

FIG. 10 is a diagram for explaining a read operation of the field memory.

FIG. 11 is a diagram for explaining line offset subsampling.

FIG. 12 is a diagram for explaining reproduction of high frequency components by line offset subsampling.

FIG. 13 is a diagram for explaining line interpolation and interlace interpolation.

FIG. 14 is a diagram for explaining line interpolation and interlace interpolation.

FIG. 15 is a block diagram showing a configuration of a luminance system (reading side).

FIG. 16 is a diagram showing characteristics of a high-pass filter and a low-pass filter arranged in a luminance system (reading side).

FIG. 17 is a diagram showing characteristics of a low-pass filter configured in the luminance system (reading side).

FIG. 18 is a diagram showing characteristics of a low-pass filter configured in a luminance system (reading side).

FIG. 19 is a diagram for explaining signal reproduction by line interpolation and subsampling.

FIG. 20 is a diagram for explaining the color modulation operation of the chroma encoder.

FIG. 21 is a block diagram showing a configuration of a chroma asynchronous circuit.

FIG. 22 is a diagram for explaining the operation of the chroma asynchronous circuit.

FIG. 23 is a diagram for explaining the timing of select pulses.

FIG. 24 is a block diagram showing a configuration of a write-side clock generation circuit.

FIG. 25 is a diagram for explaining phase comparison timing.

FIG. 26 is a diagram for explaining phase comparison timing.

FIG. 27 is a diagram showing oscillation characteristics of a voltage controlled oscillator.

FIG. 28 is a diagram for explaining an effective video signal period on the reading side.

FIG. 29 is a diagram for explaining an effective video signal period on the writing side.

FIG. 30 is a block diagram showing a configuration of a write-side / read-side control circuit.

FIG. 31 is a block diagram showing a configuration of a write-side / read-side control circuit.

FIG. 32 is a block diagram showing a configuration of a coefficient control data generation circuit.

FIG. 33 is a diagram for explaining write control and the like in the queue mode.

FIG. 34 is a diagram showing a relationship between a tape pattern and a head trace in a cue mode (4 × speed).

FIG. 35 is a diagram showing a relationship between a tape pattern and a head trace in a cue mode (3 × speed).

FIG. 36 is a diagram for explaining formation of an envelope detection signal by the microcomputer in the cue / review mode.

FIG. 37 is a diagram showing a state of write data on a memory in a queue mode.

FIG. 38 is a diagram for explaining a vertical shaking prevention operation in the cue mode.

FIG. 39 is a diagram for explaining a comparison prohibition signal in the horizontal direction (comparison section in the vertical direction).

FIG. 40 is a diagram for explaining a comparison prohibition signal in the horizontal direction (comparison prohibition section in the vertical direction).

FIG. 41 is a diagram showing a recording track pattern in the PAL system LP mode.

FIG. 42 is a diagram showing a display screen in the queue / review mode in the case where H lines are not arranged.

FIG. 43 is a diagram showing a shift of a horizontal synchronizing signal of a reproduced signal in the cue / review mode.

FIG. 44 is a diagram showing a writing state of the memory when there is a shift in the horizontal synchronizing signal in the cue / review mode.

FIG. 45 is a diagram showing a write enable signal and the like in the 1/5 times slow mode of the intermittent feeding method.

FIG. 46 is a diagram for explaining line number conversion.

FIG. 47 is a diagram for explaining field number conversion.

[Fig. 48] Fig. 48 is a diagram for describing conversion of the number of lines in a field and in a frame.

[Explanation of symbols]

1, 7 Input terminals 3, 13R, 13B Clamp circuit 4, 15 A / D converter 6, 17, 18 Multiplexer 8 Chroma decoder 14R, 14B Connection switch 19 Field memory 21Y1, 21Y2, 41R1, 41R2, 41B1, 41
B2 latch circuits 22Y1, 22Y2 high pass filters 23, 44R, 44B, 46R, 46B, 47R, 47
B changeover switches 24, 29, 43R, 43B Adders 25Y1, 25Y2, delay circuits 26Y1, 26Y2 Subtractors 28Y1, 28Y2 Coefficient ROM 36, 54R, 54B D / A converter 37, 55R, 55B Output terminals 42R1, 42R2, 42B1, 42B2 Up-conversion circuit 48R, 48B Burst level circuit 49 Chroma asynchronous circuit 50 Chroma encoder 62 JOG horizontal reset circuit 65 Half H killer circuit 66, 67 Phase difference detection circuit 68 Voltage controlled oscillator 69 Write side horizontal counter 70 Read side horizontal counter 71 External Vertical Reset Circuit 73 Vertical Sync Signal Generation Circuit 74 External Horizontal Reset Circuit 75 Comparison Disable Circuit 76 Phase Comparison Circuit 77, 79 Low Pass Filter (Inverting Amplifier) 81 Write Address Control Circuit 82 Write Tie Ming generation circuit 83, 84 increment circuit 90 conversion / non-conversion determination circuit 91 mode determination circuit 92 sync selection circuit 93 mode change detection circuit 94 write enable control circuit 95 rising edge detection circuit 103 read side horizontal counter 104 read side vertical counter 107 read timing generation circuit 108 read address control circuits 109 and 121 ID latch circuit 120 coefficient control ROM

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-3-89788 (JP, A) JP-A-59-133777 (JP, A) JP-A-1-194781 (JP, A) JP-A-4- 299687 (JP, A) JP-A-7-15699 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N ^7/ 00-7/088

Claims (2)

(57) [Claims] 1. A memory having a storage capacity for one field, a memory write control means for sequentially writing video data constituting an input video signal of the first system to the memory, and first and second memory units continuous from the memory. a memory read control means for reading in parallel video data of the second line, Intare using video data of the first and second lines are read by the memory read control means
Arithmetic processing means for performing video interpolation to obtain video data of each line forming an output video signal of a second method different from the first method, and the first and the first and second read by the memory read control means. A field inversion detection means for detecting occurrence of field inversion in which a field at the time of writing the video data of the second line is different from a field at the time of reading, and the memory read control means has the field at the time of writing by the field inversion means. Strange
Even field when reading with several fields
When field inversion is de is detected, shifting twice readings or thinning of lines with one line shift line out read, the field at the time of writing in the field inversion means even
An odd field when reading from several fields
Read twice when a field reversal is detected.
Alternatively, the television conversion device is characterized by shifting the thinning line . 2. Field identification data for identifying a field at the time of writing is added to each line of video data forming the input video signal written in the memory, and the field inversion detection means uses the field identification data. 2. The television system conversion apparatus according to claim 1, wherein the field inversion is detected line by line.