JP3112787B2 - Scanning line converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal scanning line conversion circuit used in a television signal transmitting and receiving apparatus or a converter between different signal systems.

[0002]

2. Description of the Related Art There is a letter box system as a broadcasting system which requires a scanning line conversion process. The letterbox system is one of the systems proposed for the next-generation television system (EDTV), and is compatible with the current NTSC color television system. The letterbox method will be described with reference to FIG. On the transmitting side, the aspect ratio is 1 as the image source
Using a 6: 9 image signal, 480 effective scanning lines (240 lines per field) in 525 lines in one frame are compressed by 3/4 times in the vertical direction to 360 lines (180 lines per field) Auxiliary signals such as high-frequency signals in the horizontal or vertical direction are multiplexed inconspicuously on the upper and lower panels. When this is received by the current television receiver, an image as shown in FIG. 8A is obtained. on the other hand,
When received by the EDTV receiver, an image having an aspect ratio of 16: 9 is displayed as shown in FIG. In an EDTV receiver, 360 lines per frame (180 lines per field)
The image composed of the scanning lines of the (1)
480 lines per frame (240 per field
Book) must be converted to an image consisting of scan lines.

A scanning line conversion process in this case will be described with reference to FIG. FIG. 9 shows a configuration example in the case of an NTSC decoder. A digitally converted television signal is input to a terminal 91 and supplied to a YC separation circuit 92.
The YC separation circuit 92 separates a luminance signal and a chrominance signal from the television signal,
4, supplied to the color demodulation circuit 93. In the color demodulation circuit 93, the color difference signals (RY, B
−Y) are demodulated, and each is stored in the positioning memory 9.
5,96. Positioning memory 94, 9
In 5, 96, the scanning lines of each signal are rearranged from 180 lines to 240 lines per field, and supplied to the vertical filters 97, 98, 99, respectively. The vertical filters 97, 98, and 99 remove distortion and aliasing components caused by rearrangement of scanning lines by low-pass filtering in the vertical direction, and output signals after scanning line conversion.

[0004]

In the above conventional example, three scanning line conversion means are required independently for the luminance signal and two color difference signals, and the positioning memory used for the scanning line conversion is also three. A system is required. Normally, a 2-Mbit image field memory is used as the positioning memory. However, since there are three systems, a 6-Mbit memory is required, which makes it difficult to reduce the cost and hinders the spread of the receiver. In order to solve this problem, a method of performing the positioning process with the composite signal as it is and reducing the memory amount by changing the positioning memory, which used to be three systems in the past, to one system can be considered. There has been a problem that the principle of the NTSC signal of inverting every line is broken and color demodulation cannot be performed. Further, there is a problem that the YC separation between lines cannot be used for the same reason.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to solve the above-mentioned problem when the positioning process is performed with a composite signal, and to reduce the amount of memory.

[0006]

According to a first aspect of the present invention, there is provided a television signal scanning line conversion circuit, wherein one line is provided within n -1 (n is a natural number greater than 1 ) line periods. Means for rearranging the scanning lines of the television signal by inserting the invalid scanning lines at a rate of the period, and a television signal connected to the means for rearranging the scanning lines and having the invalid scanning lines after the rearranging of the scanning lines inserted therein YC separation means for separating a luminance signal and a chrominance signal from the nk line and the nk line so that the phase of a color subcarrier generated on the receiving side and a color burst into which an invalid scanning line after scanning line rearrangement are inserted are the same. n
When k + 1 lines (k is a natural number), the phases are the same,
In other lines, a selection unit for alternately inverting the phase of the color subcarrier for each line and a color signal separated from the YC separation unit are supplied and connected to the selection unit. Means for demodulating the chrominance signal from the chrominance signal using the subcarrier, and a luminance signal separated from the YC separation means,
And a vertical filter unit for removing aliasing components generated at the time of scanning line conversion, to which a color difference signal is supplied from the demodulation unit. This is achieved by a scanning line conversion circuit characterized in that demodulation and vertical filter processing are performed.

[0007] According to the second invention, in the scanning line conversion circuit of a television signal comprising the above-described configuration, disable
A timing signal for inserting a scanning line is applied for one line period.
Using the delayed timing signal ,
The first to perform the inter-line operation avoiding the inserted invalid scanning line
And a switching means for separating the luminance signal and the chrominance signal using the inter-line operation.

According to a third aspect of the invention, in the television signal scanning line conversion circuit having the first configuration, a one- line delay memory means for performing an inter-line operation, and an invalid scanning line inserted by rearranging the scanning lines. the one-line delay memory hand
Second switching means for preventing writing to the stage ;
Input of one-line delay memory means and one line delayed the
Further comprising means for the inter-line operation with the output from the one-line delay memory means, achieved by scanning line conversion circuit, characterized in that so as to separate the luminance signal and the color signal using between said line operation Is done.

[0009]

According to the first aspect of the invention, the means for rearranging the scanning lines is a television which inserts invalid scanning lines at a rate of one line period in n -1 (n is a natural number greater than 1 ) line periods. Rearrange the scanning lines of the John signal,
The luminance signal and the chrominance signal are separated from the television signal into which the invalid scanning line after the scanning line rearrangement is inserted, and the selection unit inserts the color subcarrier generated on the receiving side and the invalid scanning line after the rearranging the scanning line. In order to make the phase of the color burst the same, when the nk line and the nk + 1 line (k is a natural number), the phase is the same, and in the other lines, the phase of the color subcarrier is alternately inverted for each line, The demodulation means is
The color difference signal is demodulated from the color signal using the color subcarrier, and the vertical filter removes the aliasing component generated at the time of the scan line conversion.

According to the second invention, the first switching means
However, the timing signal for inserting the invalid scanning line
Using the timing signal delayed for the scan period,
There <br/> rows inserted between avoiding invalid scanning line lines calculated in beauty replacement, luminance signal and a color signal of separated by inter-line operation
It is .

According to the third invention, the second switching means
, One invalid scanning line inserted by rearranging the scanning lines
Switch not to write to delay memory means, line
Means for performing an inter-operation is connected to an input of a one-line delay memory
Output from one line delay memory means delayed by one line
Performs interline operation between the luminance signal and the color signal are separated by the inter-line operation.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to FIG. The scanning line converter according to the present embodiment includes a positioning memory 2 having a terminal 1, a YC separation circuit 3 to which an output from the positioning memory 2 is input,
A color demodulation circuit 4 to which a color signal from the C separation circuit is input;
Vertical filters 5 to 7 to which a luminance signal from the YC separation circuit 3 and a color difference signal from the color demodulation circuit 4 are respectively input; a phase inversion circuit 9 to which a signal from a terminal 8 is input; An output from the circuit 9 is input, and a selector 10 for selectively supplying one of the outputs to the color demodulation circuit, and timing signals T1 and T2 for controlling the positioning memory 2 and the selector 10, respectively, are supplied to terminals 11 and 1.
And a timing signal generation circuit 13 for generating and outputting the timing signal based on a signal input through the input terminal 2.

A terminal 1 receives a digitally converted television signal and supplies it to a positioning memory 2. In the positioning memory 2, 180 effective scanning lines are written per field, and at the time of reading, reading is stopped at a rate of one out of three according to the signal T1 supplied from the timing generation circuit 13, and invalid scanning lines are inserted. Thus, the scanning lines are rearranged from 180 lines to 240 lines per field. Here, the timing signal T1 is a signal which becomes high only during one line period of the four line periods. When this signal is high, the reading of the positioning memory 2 stops.

In this case, as shown in the left side of FIG. 2, the effective scanning lines a1 to a6 are b1, b2, b4, b
5, b6, and b8, and
The invalid scanning line of b7 is inserted. FIG. 3 shows the phase relationship between the color subcarriers at this time. 3. In FIG. 3, .largecircle. Indicates an effective scanning line, and .circle-solid. Indicates an invalid scanning line, and a symbol indicating the phase of the color subcarrier is shown beside it. Before scanning line rearrangement (left: 180 lines), the phase is inverted for each scanning line according to the NTSC standard, but after scanning line rearrangement (right: 240 lines).
In the invalid scanning line, the above relationship is broken.

In the next YC separation circuit 3, the luminance signal and the chrominance signal are separated from the television signal by a method such as frequency separation. Cannot be used), and supplied to the vertical filter 5 and the color demodulation circuit 4, respectively.

On the other hand, the color subcarrier reproduced on the receiver side is input to the terminal 8, and the color subcarrier and a signal obtained by inverting the color subcarrier are supplied to the selector 10. Selector 1
At 0, the color subcarrier is selected according to the signal T2 supplied from the timing generation circuit 13 and supplied to the color demodulation circuit 4 so that the phase of the color subcarrier is the same as the color burst phase after the scanning line rearrangement. Here, the timing signal T2 is
This signal is inverted every four lines, so that the phases of the color subcarriers at the 4kth line and the 4k + 1th line (k is a natural number) are the same, and the other lines can be alternately inverted every line. Eventually, it becomes possible to make the phase of the color subcarrier supplied to the color demodulation circuit the same as the color burst phase after scanning line rearrangement.

In the color demodulation circuit 4, the color difference signals (RY, BY) are demodulated from the balanced modulated color signals, and supplied to the vertical filters 6, 7, respectively. Vertical filter 5,
6, 7 multiplies the invalid scanning line inserted in the positioning memory by 0 so that the image remains unaffected, and removes distortion and aliasing components caused by rearranging the scanning line by vertical low-pass filtering. Then, the signal after the scanning line conversion is output. The vertical filter processing in this case has a configuration using different filter coefficients for each line, as shown on the right side of FIG.

In this embodiment, the phase of the color subcarrier is matched with the color burst phase after the scanning line is rearranged.
The color signal after scanning line rearrangement may be adjusted to the color subcarrier phase, or both may be changed so that the color burst and the color subcarrier have the same phase in all the scanning lines.

Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 4, the same components as those in the first embodiment described above are denoted by the same reference numerals.

The difference in configuration from the first embodiment is that the YC separation circuit 3 in the first embodiment includes two one-line delay memories 41 and 42, subtractors 43 and 44, a selector 45, and a horizontal high-pass. The point is that the filter is replaced with a filter 46 and a subtractor 47, and that the timing generation circuit 13 outputs a timing signal T3 for controlling the selector 45.

The output from the positioning memory 2 is supplied to the first one-line delay memory 41, and the output from the first one-line delay memory 41 is supplied to the second one-line delay memory 42. You. The output from the positioning memory 2 and the one-line delay memory 41
The output from the positioning memory 2 and the output from the one-line delay memory 42 are supplied to the subtractor 44. The selector 45 includes subtractors 43 and 4
4 are provided. Horizontal high-pass filter 46
Is supplied with a selector output.
Supplied to Further, the outputs from the positioning memory 2 and the horizontal high-pass filter 46 are supplied to the subtracter 47, and the output is supplied to the vertical filter 5.

A terminal 1 receives a digitally converted television signal and supplies it to a positioning memory 2. In the positioning memory 2, 180 effective scanning lines are written per field, and at the time of reading, reading is stopped at a rate of one out of three according to the signal T1 supplied from the timing generation circuit 13, and invalid scanning lines are inserted. Thus, the scanning lines are rearranged from 180 lines to 240 lines per field.

The signals after the scanning line rearrangement are subtracted by subtracters 43 and 4.
4 and 47 and 1-line delay units 41 and 42
, And are supplied to the subtracters 43 and 44, respectively. Subtractors 43 and 4
At 4, a difference signal between one line and a difference signal between two lines are obtained and supplied to the selector 45.

In the selector 45, the timing generation circuit 1
According to the signal T3 supplied from No. 3, an inter-line difference signal in which a difference between valid scanning lines is obtained while avoiding invalid scanning lines is selected (because a receiver inserts invalid scanning lines). The choice is easy). Here, the timing signal T3 is a signal obtained by delaying T1 by one line period. For example, when the effective scanning line of b2 in FIG. 2 appears in ha of FIG. 4, the output (b2-b1) of the subtractor 43 is selected because the effective scanning line of b1 appears in hb. When the effective scanning line b4 appears in ha, the invalid scanning line b appears in hb.
3 selects the output (b4-b2) of the subtractor 44 because the effective scanning line b2 appears in hc.

In the next horizontal high-pass filter 46, a color signal band is extracted from the difference signal between lines and supplied to the subtracter 47 and the color demodulation circuit 4. The subtracter 47 subtracts the color signal from the signal after the scanning line rearrangement, and supplies the luminance signal to the vertical filter 5.

On the other hand, the color subcarrier reproduced on the receiver side is input to the terminal 8, and the color subcarrier and a signal obtained by inverting the color subcarrier are supplied to the selector 10.

The selector 10 selects the color subcarrier in accordance with the signal T2 supplied from the timing generation circuit 13 and supplies the same to the color demodulation circuit 4 so that the phase of the color subcarrier is the same as the color burst phase after the scanning line rearrangement. You.

In the color demodulation circuit 4, color difference signals (RY, BY) are demodulated from the balanced modulated color signals, and supplied to the vertical filters 6, 7, respectively. Vertical filter 5,
In steps 6 and 7, distortion and aliasing components caused by rearrangement of scanning lines are removed by low-pass filtering in the vertical direction, and a signal after scanning line conversion is output. In this embodiment, the inter-frame YC separation is not used. However, the inter-line YC separation and the inter-frame YC separation in the present embodiment can be used together.

Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 5, the same components as those in the first and second embodiments described above are denoted by the same reference numerals.

This embodiment is different from the second embodiment in that two one-line delay memories are used, but is constituted by using only one one-line delay memory. That is, the configuration of the present embodiment is different from the second embodiment in that the one-line delay memory 4
2, except for the subtractor 44 and the selector 45. However, the timing signal T1 is input to the one-line delay memory 41 as write control.

A digitally converted television signal is input to a terminal 1 and supplied to a positioning memory 2. In the positioning memory 2, 180 effective scanning lines are written per field, and at the time of reading, reading is stopped at a rate of one out of three according to the signal T1 supplied from the timing generation circuit 13, and invalid scanning lines are inserted. Thus, the scanning lines are rearranged from 180 lines to 240 lines per field.

The signals after the scanning lines are rearranged are subtracted by subtracters 43 and 4.
7 and 1 line delay memory 41. In the one-line memory 41, the writing of the invalid scanning lines is stopped according to the signal T1 supplied from the timing generation circuit 13, and only the valid scanning lines are written. For example, the fifth
When the invalid scanning line b3 in FIG. 2 appears at hd in the figure, b3 is not written to the one-line memory 41, and the previous effective scanning line b2 is read and output at he. Next, in the period after one line, the effective scanning line b4 appearing in hd is written into the one-line memory 41, and the effective scanning line b2 two lines earlier is read out and output to he. As described above, since the invalid scanning line inserted by the scanning line rearrangement is not output to the output of the one-line memory 41,
The effective scanning line appearing at hd in FIG. 5 is always calculated by the previous effective scanning line and the subtractor 43. To stop writing to the line memory, a T1 signal may be input to a write enable terminal of the line memory, and writing to the memory may be controlled by the T1 signal.

The line-to-line difference signal obtained by the subtractor 43 is supplied to a horizontal high-pass filter 46, where a color signal band is extracted from the line-to-line difference signal and supplied to a subtractor 47 and a color demodulation circuit 4. The subtractor 47 subtracts the chrominance signal from the signal after the scanning line rearrangement, and outputs the luminance signal to the vertical filter 5.
Supplied to

On the other hand, the color subcarrier reproduced at the receiver side is input to the terminal 8, and the color subcarrier and a signal obtained by inverting the color subcarrier are supplied to the selector 10. Selector 1
At 0, the color subcarrier is selected according to the signal T2 supplied from the timing generation circuit 13 and supplied to the color demodulation circuit 4 so that the phase of the color subcarrier is the same as the color burst phase after the scanning line rearrangement.

In the color demodulation circuit 4, the color difference signals (RY, BY) are demodulated from the balanced modulated color signals, and supplied to the vertical filters 6, 7, respectively. Vertical filter 5,
In steps 6 and 7, distortion and aliasing components caused by rearrangement of scanning lines are removed by low-pass filtering in the vertical direction, and a signal after scanning line conversion is output. In this embodiment, the inter-frame YC separation is not used. However, the inter-line YC separation and the inter-frame YC separation in the present embodiment can be used together.

Finally, an example of the timing generation circuit 13 will be described with reference to FIGS. In FIG. 6, the timing generation circuit includes a 2-bit counter 62, a T-type flip-flop 64, a D-type flip-flop 65, and AN.
It is composed of a D gate 63 and an OR gate 61.
From the horizontal reference pulse (H-pulse) and the vertical reference pulse (V-pulse) supplied to the memory 12, a memory control signal (T1), a color subcarrier phase control signal (T2), and an inter-line operation switching control signal (T3) Occurs.

The horizontal reference pulse is a 2-bit counter 62
And the D-type flip-flop 65 is supplied to the clock input, while the vertical reference pulse is supplied to the OR gate 61 and the clear input of the T-type flip-flop 64. The output of the OR gate 61 is supplied to the clear input of the 2-bit counter 62, and the 2-bit outputs Q _A and Q _B of the 2-bit counter 62 are input to the AND gate 63. AND
The output of the gate 63 is output as it is as the timing signal T1, and is also supplied to the clock input of the T-type flip-flop 64, the D input of the D-type flip-flop 65, and the OR gate 61, respectively. Output Q _A T-type flip-flop 64 is output as a timing signal T2, the output Q of the D-type flip-flop 65 is output as a timing signal T3.

FIG. 7 shows a timing chart of the T1, T2, and T3 signals. The memory control signal (T1) is a signal that becomes high only for one line period of the four line periods, and is used for stopping reading of the positioning memory, stopping writing to the one line memory, and the like. The color subcarrier phase control signal (T2) is a signal that is inverted every four lines.
It is used to adjust the phase of the color subcarrier to the color burst phase of the signal after the scanning line is rearranged. The inter-line operation switching control signal (T3) is a signal obtained by delaying T1 by one line period, and is used to select either the one-line difference signal or the two-line difference signal in the second embodiment. .

[0039]

According to the first aspect of the present invention, n -1 (where n is less than 1)
Ri larger in response to the composite signal in which the color subcarrier phase changes by disabling the scan line consists of inserting the scan line rearrangement processing at a rate of one line period within a natural number) line period, the color used for color demodulation The phase of the sub-carrier was corrected, and it became possible to correctly color-demodulate the signal after the scanning line rearrangement.

According to the second invention, n (n is a natural number)
Invalid scanning lines are inserted at a rate of one line period within the in period.
A first switching unit for performing a line-to-line operation while avoiding invalid scanning lines for a composite signal in which invalid scanning lines have been inserted by the scanning line rearranging process. YC separation was enabled.

According to the third invention, n (n is a natural number)
Invalid scanning lines are inserted at a rate of one line period within the in period.
To the composite signal invalid scanning line is inserted by the scanning line reordering process consisting in, the second switching means for writing only effective scanning lines to avoid invalid scanning line to 1-line delay memories YC separation like YC separation between the effective scanning lines is enabled.

As a result, the positioning process can be performed with the composite signal as it is, and the positioning memory which has conventionally been three systems can be changed to one system, and the memory amount can be reduced from, for example, 6 Mbits to 2 Mbits. This can contribute to the spread of the receiver.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of scan line conversion.

FIG. 3 is an explanatory diagram of scanning line rearrangement.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating an example of a timing generation circuit.

FIG. 7 is a timing chart of the timing generation circuit.

FIG. 8 is an explanatory diagram of a letter box format.

FIG. 9 is a block diagram showing a conventional example.

[Explanation of symbols]

 1, 8, 11, 12 terminals 2 positioning memory 3 YC separation circuit 4 color demodulation circuit 5-7 vertical filter 9 inversion circuit 10, 45 selector 13 timing signal generation circuit 41, 42 1 line memory 43, 44, 47 subtractor 46 Horizontal high-pass filter

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H04N 11/00-11/24 H04N 7/01

Claims (3)

(57) [Claims] In a television signal scanning line conversion circuit, a television signal is scanned by inserting invalid scanning lines at a rate of one line period in n -1 (n is a natural number greater than 1 ) line periods. Means for rearranging lines, YC separating means connected to the means for rearranging scanning lines, for separating a luminance signal and a chrominance signal from a television signal into which the invalid scanning lines after rearranging scanning lines have been inserted, In the case of the nk line and the nk + 1 line (k is a natural number), the phase is the same so that the color subcarrier generated in the above and the color burst into which the invalid scanning line after the scanning line rearrangement is inserted are the same. For other lines, color sub-conveyance alternates line by line
Selecting means for inverting the phase of a wave, and means for receiving a color signal separated from the YC separating means and connected to the selecting means for demodulating a color difference signal from a color signal using the color subcarrier. A vertical filter unit for removing aliasing components generated during scanning line conversion, to which a luminance signal separated from the YC separation unit is supplied, and a color difference signal is supplied from the demodulation unit. A scanning line conversion circuit wherein YC separation, color demodulation, and vertical filter processing are performed after rearranging the scanning lines into which the scanning lines have been inserted. 2. The television signal scanning line conversion circuit according to claim 1, wherein a timing signal for inserting an invalid scanning line is inserted by rearranging the scanning lines using a timing signal delayed by one line period. A first switching means for performing an inter-line operation while avoiding the invalid scanning line, wherein a luminance signal and a chrominance signal are separated using the inter-line operation. . 3. The television signal scanning line conversion circuit according to claim 1, wherein the one-line delay memory means for performing an inter-line operation, and the invalid scanning line inserted by rearranging the scanning lines. Second switching means for preventing writing into the delay memory means; and means for performing an inter-line operation using an input of the one-line delay memory means and an output from the one-line delay memory means delayed by one line. And a luminance signal and a chrominance signal are separated by using the inter-line operation.