JPH05268004A - Multiplier circuit - Google Patents

Multiplier circuit

Info

Publication number
JPH05268004A
JPH05268004A JP31587591A JP31587591A JPH05268004A JP H05268004 A JPH05268004 A JP H05268004A JP 31587591 A JP31587591 A JP 31587591A JP 31587591 A JP31587591 A JP 31587591A JP H05268004 A JPH05268004 A JP H05268004A
Authority
JP
Japan
Prior art keywords
input
circuit
clock signal
transmission line
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP31587591A
Other languages
Japanese (ja)
Inventor
Mamoru Kikuchi
衛 菊池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31587591A priority Critical patent/JPH05268004A/en
Publication of JPH05268004A publication Critical patent/JPH05268004A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a stable multiplied clock signal with less delay fluctuation by forming the multiplier circuit through the input of a delayed clock signal to one input of EX-OR circuit and using a transmission line as a delay means. CONSTITUTION:A double frequency clock signal whose duty is 50% is outputted at an output terminal from an EX-OR circuit 1 having an input (a) connecting directly to an input terminal and an input (b) connecting to the input terminal via a transmission line 2 depending on the EX-OR logic when a difference of the delay time between the inputs (a) and (b) is 1/4 of a period of the clock signal inputted to the input terminal. Since a multiple factor is a fixed value being 1/4 of the period of the clock signal to be inputted, the delay by the transmission line 2 is attained, and since no adjustment is required, the entire circuit is formed on a semiconductor substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、逓倍回路に関し、特に
半導体集積回路に適した逓倍回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier circuit, and more particularly to a multiplier circuit suitable for semiconductor integrated circuits.

【0002】[0002]

【従来の技術】従来の逓倍回路は図4に示すように入力
端子に入力されたクロック信号の基本波成分のみ出力す
る低域フィルタ3と低域フィルタ3の出力信号を全波整
流して出力する全波整流回路4と、全波整流された信号
を入力し、基準電源5を有するコンパレータ6で構成さ
れている。
2. Description of the Related Art A conventional multiplier circuit, as shown in FIG. 4, outputs a low-pass filter 3 which outputs only a fundamental wave component of a clock signal input to an input terminal and an output signal of the low-pass filter 3 after full-wave rectification. And a full-wave rectifier circuit 4 and a comparator 6 that receives a full-wave rectified signal and has a reference power supply 5.

【0003】図5は動作について説明した図で各部の波
形を示している。入力端子に入力されたクロック信号
は、波形dに示すように矩形波で入力される。クロック
信号は、低域フィルタ3により高調波成分が除去され、
波形eに示すように基本波成分のみが低域フィルタ3の
出力に出力される。低域フィルタ3の出力は、全波整流
回路4に入力され、負電位側の振幅の波形を正電位側に
折り返えす全波整流が行なわれ、全波整流された信号
は、波形fに示すように波形のピークの数が入力端子に
入力されたクロック信号の2倍となってコンパレータ6
の正相入力に入力されている。コンパレータ6の逆相入
力には、電圧VTHを有する基準電源5が接続され、波形
fに示すように電圧VTHをしきい値としてHレベル,L
レベル判定がされ、その結果、波形gに示す波形がコン
パレータ6の出力に出力される。出力された信号は入力
端子に入力されたクロック信号を2逓倍した周期とな
り、デューティ調整は、電圧VTHの値を変えることによ
り行なえる。
FIG. 5 is a diagram for explaining the operation and shows the waveform of each part. The clock signal input to the input terminal is input as a rectangular wave as shown by the waveform d. The low-pass filter 3 removes harmonic components from the clock signal,
As shown by the waveform e, only the fundamental wave component is output to the output of the low pass filter 3. The output of the low-pass filter 3 is input to the full-wave rectification circuit 4, and full-wave rectification is performed to return the waveform of the amplitude on the negative potential side to the positive potential side. As shown in the figure, the number of peaks in the waveform becomes twice the number of clock signals input to the input terminal, and the comparator 6
Input to the positive phase input of. A reference power supply 5 having a voltage V TH is connected to the negative phase input of the comparator 6, and as shown in a waveform f, the voltage V TH is used as a threshold to set an H level and an L level.
The level is determined, and as a result, the waveform shown in the waveform g is output to the output of the comparator 6. The output signal has a cycle in which the clock signal input to the input terminal is doubled, and the duty can be adjusted by changing the value of the voltage V TH .

【0004】[0004]

【発明が解決しようとする課題】この従来の逓倍回路で
は、回路構成が複雑なうえ、最適波形を得るためにはコ
ンパレータの基準電源の調整を必要とする問題があっ
た。
This conventional multiplication circuit has a problem that the circuit configuration is complicated and that the reference power source of the comparator needs to be adjusted in order to obtain the optimum waveform.

【0005】[0005]

【課題を解決するための手段】本発明によれば、入力端
子に接続され入力クロックの1/4周期の遅延を有する
半導体基板上に形成される伝送線路と、その出力に接続
される第1の入力および前記入力端子に接続される第2
の入力を有する半導体基板上に形成された排他的論理和
回路とを備えた逓倍回路を得る。
According to the present invention, a transmission line formed on a semiconductor substrate connected to an input terminal and having a delay of 1/4 cycle of an input clock, and a first transmission line connected to the output thereof. Input and second connected to the input terminal
And an exclusive-OR circuit formed on a semiconductor substrate having an input of 1.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0007】図1は本発明の第一の実施例を示す図であ
る。入力端子に入力されるクロック信号は、EX−OR
回路1の入力aに入力され、他方の入力bには、半導体
集積回路基板上にマイクロストリップラインで構成した
伝送線路2を通過することにより、入力aより遅延時間
τ遅れて入力される。EX−OR回路1の入力aの信号
に対して入力bの信号の遅延時間τを入力端子に入力さ
れるクロック信号の周期Tの1/4の時間にすることに
より、EX−OR論理が行なわれた出力波形は、図2の
波形Cに示すように2逓倍されたデューティ50%のク
ロック信号が得られる。一般にマイクロストリップライ
ンの伝送線路2の遅延時間τは以下の式にて求められ
る。
FIG. 1 is a diagram showing a first embodiment of the present invention. The clock signal input to the input terminal is EX-OR
The signal is input to the input a of the circuit 1 and input to the other input b with a delay time τ delayed from the input a by passing through the transmission line 2 formed of a microstrip line on the semiconductor integrated circuit substrate. The EX-OR logic is performed by setting the delay time τ of the signal of the input b to the signal of the input a of the EX-OR circuit 1 to be 1/4 of the period T of the clock signal input to the input terminal. The output waveform thus obtained is a clock signal having a duty of 50% which is doubled as shown by the waveform C in FIG. Generally, the delay time τ of the transmission line 2 of the microstrip line is obtained by the following formula.

【0008】 [0008]

【0009】上式のεffは次式にて求まる。Ε ff in the above equation is obtained by the following equation.

【0010】 [0010]

【0011】次に図3を用いて本発明の第二の実施例に
ついて説明する。
Next, a second embodiment of the present invention will be described with reference to FIG.

【0012】この第二の実施例は2n逓倍回路の例を示
したものであり、第一の実施例で説明した逓倍回路を逓
倍回路11〜1nまで縦続接続することにより、2n逓
倍回路が実現したものである。このときの逓倍回路11
〜1nの各伝送線路の遅延時間τ11〜τ1nは次の通りに
決定される。
The second embodiment shows an example of a 2n multiplier circuit, and a 2n multiplier circuit is realized by connecting the multiplier circuits described in the first embodiment to the multiplier circuits 11 to 1n in cascade. It was done. Multiplier circuit 11 at this time
Delay times τ 11 to τ 1n of each transmission line of ˜1n are determined as follows.

【0013】入力端子に入力されるクロック信号の周期
をTとすれば、逓倍回路12に入力されるクロック信号
の周期はT/2となり、以下T/4,T/8,…,T/
n−1,T/nとなる。伝送線路2による遅延は、各逓
倍回路に入力されるクロック信号の周期の1/4に設定
することにより、各逓倍回路11〜1nの伝送線路の遅
延時間τ11〜τ1nは以下の通りとなる。
Assuming that the cycle of the clock signal input to the input terminal is T, the cycle of the clock signal input to the multiplication circuit 12 is T / 2, and the following T / 4, T / 8, ..., T /
n-1, T / n. The delay due to the transmission line 2 is set to ¼ of the cycle of the clock signal input to each multiplication circuit, so that the delay time τ 11 to τ 1n of the transmission line of each multiplication circuit 11 to 1n is as follows. Become.

【0014】 τ11=T×1/4=T/4 τ12=T/2×1/4=T/8 ・・・ τ1(n-1)=T/n−1×1/4=T/4(n−1) τ1n=T/n×1/4=T/4nΤ 11 = T × 1/4 = T / 4 τ 12 = T / 2 × 1/4 = T / 8 ... τ 1 (n-1) = T / n-1 × 1/4 = T / 4 (n-1) τ 1n = T / n × 1/4 = T / 4n

【発明の効果】以上説明したように、本発明の逓倍回路
は、能動素子EX−OR回路のみであり、遅延は伝送線
路で行なうことにより簡易な回路構成が可能である。ま
た入力するクロック信号の周期により遅延時間τは決ま
ることからτは固定値で良いため伝送線路の長さ調整は
不要となり、半導体基板上に伝送線路を含めた全回路を
構成することが可能となる。さらに伝送線路で遅延を行
なうため、遅延回路で見られる温度変動の影響等が小さ
く、安定した遅延が得られるという利点も有している。
As described above, the multiplication circuit of the present invention is only the active element EX-OR circuit, and the delay is performed by the transmission line, so that a simple circuit configuration is possible. Also, since the delay time τ is determined by the cycle of the input clock signal, τ can be a fixed value, so the length of the transmission line does not need to be adjusted, and the entire circuit including the transmission line can be configured on the semiconductor substrate. Become. Further, since the transmission line delays, there is an advantage that the influence of temperature fluctuations seen in the delay circuit is small and a stable delay can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施例を示すブロック図FIG. 1 is a block diagram showing a first embodiment of the present invention.

【図2】図1の逓倍回路の各部の波形図FIG. 2 is a waveform diagram of each part of the multiplication circuit of FIG.

【図3】本発明の第二の実施例を示すブロック図FIG. 3 is a block diagram showing a second embodiment of the present invention.

【図4】従来の逓倍回路のブロック図FIG. 4 is a block diagram of a conventional multiplication circuit.

【図5】図4の逓倍回路の各部の波形図5 is a waveform diagram of each part of the multiplication circuit of FIG.

【符号の説明】[Explanation of symbols]

1 EX−OR回路 2 伝送線路 3 低域フィルタ 4 全波整流回路 5 基準電源 6 コンパレータ 11〜1n 逓倍回路 DESCRIPTION OF SYMBOLS 1 EX-OR circuit 2 Transmission line 3 Low-pass filter 4 Full-wave rectifier circuit 5 Reference power supply 6 Comparator 11-1n multiplication circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力端子に接続され入力クロックの1/
4周期の遅延を有する半導体基板上に形成される伝送線
路と、その出力に接続される第1の入力および前記入力
端子に接続される第2の入力を有する前記半導体基板上
に形成された排他的論理和回路とを備えたことを特徴と
する逓倍回路。
1. An input clock connected to an input terminal of 1 /
A transmission line formed on a semiconductor substrate having a delay of 4 cycles, and an exclusion formed on the semiconductor substrate having a first input connected to its output and a second input connected to the input terminal. And a logical sum circuit.
JP31587591A 1991-11-29 1991-11-29 Multiplier circuit Withdrawn JPH05268004A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31587591A JPH05268004A (en) 1991-11-29 1991-11-29 Multiplier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31587591A JPH05268004A (en) 1991-11-29 1991-11-29 Multiplier circuit

Publications (1)

Publication Number Publication Date
JPH05268004A true JPH05268004A (en) 1993-10-15

Family

ID=18070651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31587591A Withdrawn JPH05268004A (en) 1991-11-29 1991-11-29 Multiplier circuit

Country Status (1)

Country Link
JP (1) JPH05268004A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1117636A (en) * 1997-06-20 1999-01-22 Nec Corp Multiplexer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1117636A (en) * 1997-06-20 1999-01-22 Nec Corp Multiplexer

Similar Documents

Publication Publication Date Title
US6198317B1 (en) Frequency multiplication circuit
US5901054A (en) Pulse-width-modulation control circuit
US5929714A (en) PLL timing generator
JPH04232519A (en) Self-adjusting clock generator
US4669099A (en) Digital frequency multiplier
TW202029640A (en) Frequency doubling apparatus and method thereof
TW200427224A (en) Clock multiplier
CN101436857A (en) Clock pulse generators and clock pulse generation methods thereof
JP3641782B2 (en) Clock multiplier circuit
CN210157160U (en) Digital clock frequency multiplication circuit system
JPH05268004A (en) Multiplier circuit
US5010561A (en) Circuit for multiplying the frequency in one series of input pulses
JPH08168239A (en) Control circuit for zero-volt switch pulse width modulation type switching regulator
JP2008028830A (en) Phase-comparison signal processing circuit
JP3783072B2 (en) Reference pulse generator
JPH0645895A (en) Signal width control circuit
JPH04354407A (en) Frequency discriminator
JP2004194483A (en) Controller for dc-dc converter
JP3062506B1 (en) Impedance measuring device
SU752670A1 (en) Cascade-type frequency multiplyer
JPH0658943B2 (en) Substrate voltage generation circuit
CN106160666B (en) Design pierce circuit and its control method
KR0118634Y1 (en) Frequency multiflier
JPH0281513A (en) Frequency multiplier circuit
JP2776328B2 (en) PLL circuit

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990204