JPH05268004A - Multiplier circuit - Google Patents

Abstract

PURPOSE:To obtain a stable multiplied clock signal with less delay fluctuation by forming the multiplier circuit through the input of a delayed clock signal to one input of EX-OR circuit and using a transmission line as a delay means. CONSTITUTION:A double frequency clock signal whose duty is 50% is outputted at an output terminal from an EX-OR circuit 1 having an input (a) connecting directly to an input terminal and an input (b) connecting to the input terminal via a transmission line 2 depending on the EX-OR logic when a difference of the delay time between the inputs (a) and (b) is 1/4 of a period of the clock signal inputted to the input terminal. Since a multiple factor is a fixed value being 1/4 of the period of the clock signal to be inputted, the delay by the transmission line 2 is attained, and since no adjustment is required, the entire circuit is formed on a semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier circuit, and more particularly to a multiplier circuit suitable for semiconductor integrated circuits.

[0002]

2. Description of the Related Art A conventional multiplier circuit, as shown in FIG. 4, outputs a low-pass filter 3 which outputs only a fundamental wave component of a clock signal input to an input terminal and an output signal of the low-pass filter 3 after full-wave rectification. And a full-wave rectifier circuit 4 and a comparator 6 that receives a full-wave rectified signal and has a reference power supply 5.

FIG. 5 is a diagram for explaining the operation and shows the waveform of each part. The clock signal input to the input terminal is input as a rectangular wave as shown by the waveform d. The low-pass filter 3 removes harmonic components from the clock signal,
As shown by the waveform e, only the fundamental wave component is output to the output of the low pass filter 3. The output of the low-pass filter 3 is input to the full-wave rectification circuit 4, and full-wave rectification is performed to return the waveform of the amplitude on the negative potential side to the positive potential side. As shown in the figure, the number of peaks in the waveform becomes twice the number of clock signals input to the input terminal, and the comparator 6
Input to the positive phase input of. A reference power supply 5 having a voltage V _TH is connected to the negative phase input of the comparator 6, and as shown in a waveform f, the voltage V _TH is used as a threshold to set an H level and an L level.
The level is determined, and as a result, the waveform shown in the waveform g is output to the output of the comparator 6. The output signal has a cycle in which the clock signal input to the input terminal is doubled, and the duty can be adjusted by changing the value of the voltage V _TH .

[0004]

This conventional multiplication circuit has a problem that the circuit configuration is complicated and that the reference power source of the comparator needs to be adjusted in order to obtain the optimum waveform.

[0005]

According to the present invention, a transmission line formed on a semiconductor substrate connected to an input terminal and having a delay of 1/4 cycle of an input clock, and a first transmission line connected to the output thereof. Input and second connected to the input terminal
And an exclusive-OR circuit formed on a semiconductor substrate having an input of 1.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of the present invention. The clock signal input to the input terminal is EX-OR
The signal is input to the input a of the circuit 1 and input to the other input b with a delay time τ delayed from the input a by passing through the transmission line 2 formed of a microstrip line on the semiconductor integrated circuit substrate. The EX-OR logic is performed by setting the delay time τ of the signal of the input b to the signal of the input a of the EX-OR circuit 1 to be 1/4 of the period T of the clock signal input to the input terminal. The output waveform thus obtained is a clock signal having a duty of 50% which is doubled as shown by the waveform C in FIG. Generally, the delay time τ of the transmission line 2 of the microstrip line is obtained by the following formula.

[0008]

Ε _ff in the above equation is obtained by the following equation.

[0010]

Next, a second embodiment of the present invention will be described with reference to FIG.

The second embodiment shows an example of a 2n multiplier circuit, and a 2n multiplier circuit is realized by connecting the multiplier circuits described in the first embodiment to the multiplier circuits 11 to 1n in cascade. It was done. Multiplier circuit 11 at this time
Delay times τ _{11 to} τ _1n of each transmission line of ˜1n are determined as follows.

Assuming that the cycle of the clock signal input to the input terminal is T, the cycle of the clock signal input to the multiplication circuit 12 is T / 2, and the following T / 4, T / 8, ..., T /
n-1, T / n. The delay due to the transmission line 2 is set to ¼ of the cycle of the clock signal input to each multiplication circuit, so that the delay time τ _{11 to} τ _1n of the transmission line of each multiplication circuit _{11 to 1n} is as follows. Become.

Τ ₁₁ = T × 1/4 = T / 4 τ ₁₂ = T / 2 × 1/4 = T / 8 ... τ _{1 (n-1)} = T / n-1 × 1/4 = T / 4 (n-1) τ _1n = T / n × 1/4 = T / 4n

As described above, the multiplication circuit of the present invention is only the active element EX-OR circuit, and the delay is performed by the transmission line, so that a simple circuit configuration is possible. Also, since the delay time τ is determined by the cycle of the input clock signal, τ can be a fixed value, so the length of the transmission line does not need to be adjusted, and the entire circuit including the transmission line can be configured on the semiconductor substrate. Become. Further, since the transmission line delays, there is an advantage that the influence of temperature fluctuations seen in the delay circuit is small and a stable delay can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram of each part of the multiplication circuit of FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional multiplication circuit.

5 is a waveform diagram of each part of the multiplication circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 EX-OR circuit 2 Transmission line 3 Low-pass filter 4 Full-wave rectifier circuit 5 Reference power supply 6 Comparator 11-1n multiplication circuit

Claims (1)

[Claims] 1. An input clock connected to an input terminal of 1 /
A transmission line formed on a semiconductor substrate having a delay of 4 cycles, and an exclusion formed on the semiconductor substrate having a first input connected to its output and a second input connected to the input terminal. And a logical sum circuit.