JPH05267680A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the sectional area of a gate formed on a channel region, reduce the resistance of the gate, and increase the reading speed of stored data, by making a sidewall gate formed on the side part of a gate of a select transistor function as a floating gate. CONSTITUTION:A P-type well 2 formed on an N-type silicon substrate 1 is isolated every specified element forming regions by a field oxide film 3. In a channel region between a drain diffusion layer 11 and a source diffusion layer 12, a floating gate 7a which is slenderly formed by interposing a tunnel oxide film 6 is formed in a region in the vicinity of the drain diffusion layer 11. In the channel region, a common gate 10a is formed in the source side region via a gate oxide film 9, so as to stretch as far as the upper region of the floating gate 7a while interposing an insulating film 8. The drain diffusion layer 11 and the source diffusion layer 12 are commonly used by both transistors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EEPROM (Electr
The present invention relates to a non-volatile semiconductor memory device such as a physically erasable / programmable read only memory.

[0002]

2. Description of the Related Art Conventionally, in an EEPROM, a gate is formed in which a floating gate which is electrically insulated by sandwiching a tunnel oxide film is formed on the surface of a semiconductor substrate, and a control gate is formed on the floating gate via an insulating film. A transistor having a structure is applied as a memory transistor. That is, for example, in an N-channel type transistor, writing is performed by injecting hot electrons generated near the drain into the floating gate through a tunnel oxide film. And
Information is erased by pulling out the electrons accumulated in the floating gate from the source side. Since the threshold voltage of the transistor is different between the state where electrons are stored in the floating gate and the state where no electrons are stored,
Apply a sense voltage with an intermediate value to the control gate,
At this time, reading of information is achieved by checking whether the transistor is held in the conductive state or the cutoff state.

In an EEPROM using a memory transistor having such a floating gate, a select transistor is provided for each memory transistor of each cell so that writing, erasing and reading of information can be performed independently for each cell. There are a full-future type and a flash type in which information writing and reading is performed for each cell and erasing is performed collectively for all cells.

However, the full-future type is
Since the select transistor is provided for each individual cell, the cell area becomes large and high integration is difficult. For this reason, recently, flash-type devices have been actively developed. A typical structure of the memory transistor in the flash type EEPROM is the stack gate structure shown in FIG. That is, the P-type well 62 is formed in the N-type silicon substrate 61, and the tunnel oxide film 63, the floating gate 64, the insulating film 65, and the control gate 66 are formed on the P-type well 62.
Are sequentially stacked. P on both sides of the tunnel oxide film 63
The N ⁺ type source diffusion layer 67 and the N ⁺
A type drain diffusion layer 68 is formed. Further, around the drain diffusion layer 68, a P ⁺ -type diffusion layer 69 for concentrating an electric field at the boundary between the drain diffusion layer 68 and the P-type well 63 to enhance the generation efficiency of hot electrons.
Are formed. Further, around the source diffusion layer 67, an N ⁻ -type diffusion layer 70 is formed for slowing the change of the impurity concentration at the boundary portion to form a high breakdown voltage structure.

With this configuration, when a positive high voltage is applied to the control gate G and the drain D and the source S is grounded, hot electrons are generated near the drain diffusion layer 68. The hot electrons pass through the tunnel oxide film 63 and reach the floating gate 6
4 is injected. In this way the writing of information is achieved.

At the time of erasing information, the gate G is grounded,
A positive erase voltage is applied to the source S. As a result, the charges in the floating gate 64 are FN tunneled and extracted to the source diffusion layer 67, thereby erasing information. The threshold value of the transistor changes into two types depending on the presence or absence of electrons in the floating gate 64. At the time of reading information, a sense voltage having an intermediate voltage value between the two kinds of threshold values is applied to the gate G. At this time, it is possible to know whether the information is in the written state or the erased state by monitoring whether or not the source and the drain are electrically connected, and thereby the reading of the information is achieved.

In the EEPROM, the memory transistors as described above are arranged in a matrix, and the sources S of the transistors are commonly connected. At the time of erasing data, all the word lines connected to the gate G are grounded, and a positive voltage is applied to the commonly connected sources S, so that the erasing of information on all cells is performed at once. Done. In such a flash type EEPROM having a stack gate structure, one cell includes one transistor.
Since it is an individual, it is advantageous for integration.

However, all cells (or P
In order to erase the stored information in all cells in the mold well 62 at a time, it is necessary to set the overall erase time to a long time in accordance with the cell that requires the longest time to erase the signal charge. Therefore, in the cell in which the signal charge is erased relatively quickly, the signal charge is excessively extracted, and the positive charge is accumulated in the floating gate of the memory transistor of this cell, which causes an excessive erase. When such over-erasure occurs, the threshold value of the transistor varies among cells, and the read operation may become unstable. For example, in a memory transistor of a cell in which over-erase has occurred, even if it is in a non-selected state, a channel is formed due to the positive charge accumulated in the floating gate, and a current flows between the source and the drain. Then, the reading of the stored information from the target cell becomes uncertain.

As a flash type EEPROM that solves such a problem, SISO is shown in a simplified form in FIG.
It is proposed that a transistor having a gate of S (SIdewall Select-gate On the Source side) structure is applied to a memory transistor. In FIG. 8, portions corresponding to the respective portions shown in FIG. 7 described above are designated by the same reference numerals. In this structure, the SWS (side wall layer) formed in a self-aligned manner on the side wall portion of the gate including the floating gate 64 on the source diffusion layer 67 side.
The spacer) is used as the select gate 71 for cell selection. When the information is read, the selection gate 7
A positive voltage is applied to 1 to form a channel in the P-type well 62 directly below the select gate 71.

According to this structure, the read cell can be surely selected by applying the voltage to the select gate 71.
Even if there is some variation in the threshold value due to overerasure, reading of information from non-selected cells can be prevented,
The reliability of the read operation can be secured. Moreover, since the transistor formation region does not become excessively large, high integration can be favorably performed.

[0011]

However, in the memory device to which the transistor having the SISOS structure as described above is applied, it is necessary to apply a voltage to the select gate 71 having a relatively small cross-sectional area. There is a problem that the electric resistance is high, and as a result, the speeding up of the read operation is hindered. To avoid this problem, the selection gate 71
Increasing the cross-sectional area of causes an increase in the substrate area,
This is against the demand for high integration and is unacceptable.

Therefore, an object of the present invention is to solve the above-mentioned technical problems and to provide a non-volatile semiconductor memory device which can favorably perform a read operation and which is advantageous for high integration.

[0013]

A conceptual structure of a nonvolatile semiconductor memory device of the present invention for achieving the above object is shown in FIG. That is, the nonvolatile semiconductor memory device of the present invention includes a memory transistor MTr for performing nonvolatile storage by injecting / releasing charges to the floating gate through the tunnel insulating film 51, and a select transistor ST for selecting the memory transistor MTr.
and a memory transistor MTr formed by sandwiching a channel region in the semiconductor substrate 50.
And a first impurity diffusion region 53 and a second impurity diffusion region 54 which also serve as drains and sources of the select transistor STr, a gate 55 of the select transistor STr formed on the channel region of the semiconductor substrate 50, and The side wall gate 52, which is provided in an electrically insulated state on the drain side of the gate 55 and acts as the floating gate, and the side wall gate 52.
And a control gate 57 of the memory transistor MTr, which is disposed in the vicinity of the memory cell via an insulating film 56.

[0014]

According to the above configuration, the select transistor S
The gate 55 of Tr is formed over a relatively wide region of the channel region, and the side wall gate 52 formed on the side portion thereof functions as a floating gate. That is, since the sidewall gate 52 having a small cross-sectional area is used only for accumulating charges without applying a voltage, no problem occurs even if the sidewall gate 52 having a small cross-sectional area has a high resistance value. Absent. On the other hand, since the gate 55 to which the voltage for selecting the memory transistor MTr is applied has a relatively large cross-sectional area, it can have a sufficiently small resistance value, which enables a high-speed read operation. Can be achieved.

[0015]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. 2 is a plan view of a memory cell of an EEPROM which is an embodiment of the nonvolatile semiconductor memory device of the present invention, and FIG. 3 is a sectional view taken along the section line AA of FIG. The P-type well 2 formed on the N-type silicon substrate 1 is separated by the field oxide film 3 for each predetermined element formation region. An N ⁺ type drain diffusion layer 11 and an N ⁺ type source diffusion layer 12 are formed in the separated element formation region.

In the channel region between the drain diffusion layer 11 and the source diffusion layer 12, in the region near the drain diffusion layer 11, an elongated floating gate 7a with a tunnel oxide film 6 interposed is formed. .. Further, in the above-mentioned channel region, a common gate 10a is formed in the region on the source side via the gate oxide film 9, and the common gate 10a is above the floating gate gate 7a with the insulating film 8 interposed. Is formed so as to extend to the region.

In FIGS. 2 and 3, 14 is a metal wiring electrically connected to the drain diffusion layer 11 and the source diffusion layer 12, 16 is a metal wiring electrically connected to the common gate 10, and 13, Reference numeral 15 is an interlayer insulating film. In this embodiment, one memory cell has a memory transistor and a select transistor in one transistor region. That is, the drain diffusion layer 11 and the source diffusion layer 12 are also used as the drain and the source of both transistors. Further, the gate of the memory transistor is composed of the tunnel oxide film 6, the floating gate 7a, the insulating film 8 and the common gate 10a described above, and one end of the common gate 10a on the drain side serves as a control gate. Further, the gate of the select transistor is composed of the source-side end of the above-described gate oxide film 9 and common gate 10a.
That is, the floating gate 7a described above is composed of a sidewall gate formed on the side of the gate of the select transistor STr.

FIG. 4 shows a part of the EEPROM of this embodiment.
It is an electric circuit diagram which shows an equivalent circuit. One memory cell
Is the memory transistor MTr and select transistor described above.
It is composed of a register STr and each memory cell is a matrix.
It is arranged like a stripe. Both transistors MTr, STr
The common gate 10a of the
_n, W_{n + 1}, W_{n + 2}Connected to the memory transistor M
The drain (drain diffusion layer 11) of Tr is a bit line
B_m, B_{m + 1}Connected to the select transistor STr
Source (source diffusion layer 12) is the source line S_m, S
_{m + 1}It is connected to the. Word line W_n, W_{n + 1}, W
_{n + 2}Is selected by the X decoder 20 and the source line S
_m, S_{m + 1}Are selected by the Y decoder 21.

Data writing to the memory cell (n, m) is performed as follows. That is, the write voltage V _P is applied to the bit line B _m , the word line W _{n is set} to the H level, and the source line S _m is grounded. The memory cell (n, m + 1) commonly connected to the word line W _n together with the memory cell (n, m) is opened or grounded by opening the bit line B _{m + 1} and the source line S _{m + 1} . Writing is prohibited. In the other memory cells (n + 1, m) and (n + 1, m + 1), by setting the word line W _{n + 1} to the ground or the L level, the select transistor STr is turned off and writing can be prohibited.

In the selected memory cell (n, m), hot electrons are injected into the floating gate 7a as follows. That is, when the write voltage V _P is applied to the drain diffusion layer 11, the source diffusion layer 12 is grounded, and the common gate 10a becomes H level, a channel is formed from the source diffusion layer 12 toward the drain diffusion layer 11. It By appropriately setting the write voltage V _P , this channel is crossed over the lower portion of the select transistor STr (that is, immediately below the gate oxide film 9 on the right side of the common gate 10a in FIG. 3) and the drain diffusion layer 11 is formed.
Extend to a position that does not reach. Then, the electric field is concentrated immediately below the floating gate 7a, and a large number of hot electrons are generated. A part of the hot electrons flows into the drain diffusion layer 11, but a part of the hot electrons is accelerated by the electric field of the common gate 10a, penetrates the tunnel oxide film 6, and is injected into the floating gate 7a. In this way, writing of data is achieved. In this written state, the threshold value for making the memory transistor MTr conductive has a high value.

Erasing the data in the memory cell (n, m)
This is done as follows. That is, the word line W _n
Is set to the L level, and the erase voltage V _E is applied to the bit line B _m and the source line S _m . The memory cell (n, m + 1) commonly connected to the word line W _n together with the memory cell (n, m) has a bit line B _{m +.
1} and the source line S _{m + 1} are grounded or open, and erasing is prohibited. In addition, other memory cells (n
+ 1, m) and (n + 1, m + 1) are word lines W
Erase can be prohibited by setting _{n + 1} to the H level. When the common gate 10a of the memory cell (n, m) is set to the L level and the erase voltage V _E is applied to the drain diffusion layer 11, the electrons accumulated in the floating gate 7a pass through the tunnel oxide film 6. Drain diffusion layer 11
, And thereby erase of the stored data is achieved. In this erased state, the threshold value for making the memory transistor MTr conductive has a low value.

The data stored in the memory cell (n, m) is read out as follows. That is, the source line S _m is grounded and the sense voltage V _{SENSE is} applied to the word line W _n.
It applies a applies a voltage Vcc via a resistor to the bit line B _m, the bit line B _m, for detecting the presence or absence of the potential drop. That is, the memory cell (n, m)
If data is written in the memory transistor M,
Since Tr is turned off, no voltage drop occurs,
That is, the data “1” is read. On the other hand, when the data is written in the memory cell (n, m), the memory transistor MTr is turned on, so that the voltage drop occurs, that is, the data “0” is read.
The sense voltage V _SENSE is a voltage having an intermediate value between the threshold values of the memory transistor MTr in the written state and the erased state.

As described above, in this embodiment, the side wall gate formed on the side of the gate of the select transistor STr is used as the floating gate 7a, and the common gate 10a extends over a relatively wide region on the channel region. The formed source-side portion having a large cross-sectional area is used as the gate of the select transistor STr.
Therefore, the gate of the select transistor STr can have a sufficiently small resistance, so that the select transistor STr can be driven well. As a result, the read operation can be performed at high speed.

On the other hand, since the sidewall gate is used for the floating gate 7a, this floating gate 7a
However, no external voltage is applied to the floating gate 7a, and the floating gate 7a is used only for accumulating charges. Therefore, even if floating gate 7a having a small cross-sectional area has a large resistance value, this does not adversely affect each operation of writing, erasing and reading.

Moreover, since the two transistors of the memory transistor MTr and the select transistor are formed in one transistor formation region, the area of the memory cell does not increase excessively, and high integration can be favorably achieved. It can be carried out. Hereinafter, a method of manufacturing the EEPROM of this embodiment will be described with reference to FIGS.
The manufacturing method can be variously modified, and the memory device of the present invention is not limited to the one manufactured by this method.

First, as shown in FIG. 5A, a P-type well 2 is formed on an N-type silicon substrate 1, an oxide film 4 is then formed on the surface, and a field oxide film 3 for element isolation is further formed. Can be selectively grown. Then, as shown in FIG. 5B, the oxide film 5 is formed by CVD (Chemical Vapor Deposit).
ion deposition) and then anisotropically etching to selectively remove the oxide film 5 in the region where the memory transistor and the select transistor are to be formed.

From this state, in order to smooth the surface of the substrate, the surface of the substrate is re-oxidized, and then the oxide film is removed by wet etching. Then, in the element formation region,
After forming the tunnel oxide film 6, a conductive polysilicon film 7 is deposited. This state is shown in FIG. 5 (c). Next, as shown in FIG. 5D, etching back is performed until the polysilicon film 7 on the oxide film 5 is completely removed. As a result, a sidewall of polysilicon is formed on the end surface of the window portion of the oxide film 5. The sidewall on the left is
It becomes the floating gate 7a of the memory transistor MTr described above. The gate length of the floating gate 7a can be controlled by a dimension smaller than the design rule by changing the thickness of the oxide film 5 and the etching conditions.

Next, FIG. 6 (e) will be referred to. In this step, the floating gate 7a, which is the left sidewall shown in FIG. 5D, and a part of the oxide film 5 are masked with a photoresist, and the right sidewall and the rest of the oxide film 5 are etched. To remove. Then, after removing the photoresist, the floating gate 7 is thermally oxidized.
An insulating film (silicon oxide film) 8 is formed on the surface of a. Further, the oxide film in the select transistor region is removed by wet etching, then the gate oxide film 9 is formed, and then the polysilicon film 10 is formed.

Next, as shown in FIG. 6 (f), the transistor region is masked with a photoresist, and the remaining polysilicon film 10 and oxide film 5 are removed by anisotropic etching. As a result, the common gate 10a which is also used as the control gate of the memory transistor and the gate of the select transistor is formed. After removing the oxide film 9 in the drain and source regions, N type impurities such as phosphorus and arsenic are ion-implanted to form the drain diffusion layer 11 and the source diffusion layer 12.

Further, as shown in FIG. 6 (g), thermal oxidation is performed again to form an oxide film on the surface. And phosphorus glass (P
After depositing an interlayer insulating film 13 such as SG), contact holes are formed in the drain and source regions, and Al--S
Deposit a metal such as i. This metal film is patterned by photoetching to form metal wirings electrically connected to the drain diffusion layer 11 and the source diffusion layer 12.

Then, as shown in FIG. 6H, after depositing the interlayer insulating film 15, a contact hole is formed in the gate region and a metal layer is deposited. By patterning this metal layer, the metal wiring 16 connected to the common gate 10a is formed. In this way, FIG. 2 and FIG.
The EEPROM shown in FIG. The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the N-channel type EEPROM has been described as an example, but the present invention is a P-channel type EEPROM.
Of course, it can also be applied to.

Further, as explained in the conventional example shown in FIG. 6, in the memory cell shown in FIG. 2 as well, in order to increase the generation efficiency of hot electrons between the drain diffusion layer 11 and the P-type well 2. A P ⁺ type diffusion layer may be provided. Further, an N ⁻ diffusion layer may be provided between the source diffusion layer 12 and the P-type well 2 in order to improve the breakdown voltage. further,
In the above-mentioned embodiment, the control gate of the memory transistor and the gate of the select transistor are constituted by one common gate 10a, but these gates are constituted by two gates which are mutually insulated as in the constitution of FIG. It may be configured.

Besides, various design changes can be made within the scope of the present invention.

[0034]

As described above, according to the nonvolatile semiconductor memory device of the present invention, since the sidewall gate provided on the side of the gate of the select transistor is made to function as the floating gate, it is formed on the channel region. The gate of the selected select transistor may have a sufficiently large cross-sectional area. Therefore, since the gate of the select transistor can have a sufficiently low resistance value, the stored information can be read at high speed.

Moreover, in one transistor formation region,
Since the two transistors of the memory transistor and the select transistor are formed, they can be formed in a small area, which is advantageous for high integration.

[Brief description of drawings]

FIG. 1 is a simplified cross-sectional view showing a basic configuration of a nonvolatile memory device of the present invention.

FIG. 2 is a plan view showing a cell structure of an EEPROM which is an embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a sectional view taken along the section line AA of FIG.

FIG. 4 is an electric circuit diagram showing an equivalent circuit of a part of the memory device of the above embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing process of the memory device of the above embodiment in the order of processes.

FIG. 6 is a cross-sectional view showing the manufacturing process of the memory device of the above embodiment in process order.

FIG. 7 is a sectional view showing a cell structure of a flash type EEPROM having a stack gate structure which has been conventionally used.

FIG. 8 is a conventional flash type E having a SISSOS structure.
It is sectional drawing which shows the cell structure of EPROM.

[Explanation of symbols]

 1 N-type silicon substrate 2 P-type well 6 Tunnel oxide film 7a Floating gate 8 Insulating film 9 Gate oxide film 10a Common gate 11 Drain diffusion layer (first impurity diffusion region) 12 Source diffusion layer (second impurity diffusion region) 50 Semiconductor Substrate 51 Tunnel Insulation Film 52 Floating Gate 53 First Impurity Diffusion Region 54 Second Impurity Diffusion Region 55 Select Transistor Gate 56 Insulation Film 57 Memory Transistor Control Gate MTr Memory Transistor STr Select Transistor

Claims (1)

[Claims] 1. A non-volatile semiconductor memory device comprising a memory transistor for performing non-volatile storage by injecting / releasing charges to / from a floating gate through a tunnel insulating film, and a select transistor for selecting the memory transistor. A first impurity diffusion region and a second impurity diffusion region which are formed on the substrate with a channel region sandwiched therebetween and also serve as drains and sources of the memory transistor and the select transistor; and the above-mentioned semiconductor device formed on the channel region of the semiconductor substrate. The gate of the select transistor, the side wall gate that is provided on the drain side of the gate in an electrically insulated state, and acts as the floating gate, and the side wall gate that is disposed near the side wall gate via an insulating film. Memory transistor control game And a non-volatile semiconductor memory device.