JPH05267672A - Semiconductor device - Google Patents

Abstract

PURPOSE:To remarkably improve resistance to noise at a low cost, in a power IC wherein a vertical type power element (MOSFET, IGBT, etc.) and its control circuit are constituted in a chip. CONSTITUTION:An insulating layer 14 is buried in a P-well 13 in which a junction (J1) for blocking a main circuit voltage is formed by using an SIMOX method and a short path 15 is formed at the same time. A control. circuit is formed only on the insulating layer 14. Thereby the control circuit is hardly affected by the displacement current due to dv/dt, especially in the case of sharp dv/dt at the time of turning OFF of a power element which turns a main current ON and OFF, so that malfunction is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in many applications such as semiconductor devices suitable for low-side switches, in particular, solenoid driving of automobiles and various automatic machines, driving of DC motors, driving of various displays, driving of DC motors. The present invention relates to a power IC.

[0002]

2. Description of the Related Art First, a low-side, single power output power IC will be described. A method of realizing this power IC with the simplest structure will be described. In FIG. 7, an n-channel vertical MOS FET is used as a power element, and a MOS F
The control circuit of the MOS FET is formed in a large P well formed by the same P diffusion as the P well of the ET. FIG. 7A is a plan view of a chip, 1 is a chip, 2 is a vertical MOS FET part, 3 is a control circuit part,
4 is a bonding pad and 10 is a vertical MOS FET
Is the source of. 7B is an enlarged view of part A of FIG. 7A, 5 is an n ⁺ region, 6 is the source of the MOS FET of the control circuit, 7 is its gate, 8 is its drain, 9 is an n region, 10 is the source of the MOS FET, 11 is the same gate, 12 is the same drain, 13 is a P well, and 18 is N
Well, 19 is a source / drain diffusion layer, 20 is nn
⁺ Silicon substrate, 21 is a gate oxide film, and 22 is a polysilicon gate. This structure is the simplest structure and can provide a low-side switch having a large capacity power element.

[0003]

The conventional semiconductor device as described above has a fatal defect that the dv / dt resistance is extremely small. That is, for example, an output MOS FET
Is switched from the ON state to the OFF state, a dv / dt accompanying the turn-off of the output MOS FET is applied to the junction J _{1 formed} by the P well, and the excursion current due to this dv / dt (see an arrow in FIG. 7B). Shows the latch-up of the PNPN four-layer structure directly under the drain of the n-channel MOS FET part of the control circuit, or the P-channel MOS.
There is a problem that it flows into the drain of the FET and drives a device in the subsequent stage to cause a malfunction.

The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a semiconductor device capable of preventing a control circuit of a power IC from malfunctioning due to a deviation current due to dv / dt. To aim.

[0005]

In a semiconductor device according to the present invention, an insulating layer is intermittently and planarly formed in a well to form a short circuit path in the vertical direction, and the insulating layer is formed. The control circuit is formed only on the top.

In addition, a high-concentration impurity is diffused above the short-circuit path and connected to a low-potential power source, or a high-impurity concentration layer of the opposite conductivity type which is not grounded is formed around the short-circuit path where the high-concentration impurity is diffused. It is also preferable to

[0007]

In the present invention, the excursion current generated when the power element is turned off is blocked by the insulating layer and passes through the short circuit path. Further, if the short circuit is connected to the low potential power source, the excursion current is likely to be emitted to the outside.

[0008]

1 (a), 1 (b) to 4 (a), 4 (b) show a manufacturing process of an embodiment of a semiconductor device of the present invention. In these figures, the same reference numerals as those in FIG.
Reference numeral 14 is an insulator layer formed by the SIMOX (Separated by Inplanted Oxigen) method, 15 is a short circuit path formed in the insulation layer 14, 16 is a low resistance short circuit path, and 17 is an n-type impurity diffusion layer. The steps will be described below.

First, as shown in FIG. 1A, the P well 13 is formed by a process of forming an ordinary power MOS FET using the nn ⁺ silicon substrate 20, and a portion constituting the control circuit and the power MOS FET. Is formed in the part of. In this case, the control circuit portion is, as shown in the enlarged view of FIG.
The part is formed corresponding to each segment.

Next, as shown in FIGS. 2 (a) and 2 (b),
O 2 ⁻ is implanted into the control circuit portion at a predetermined depth by a SIMOX method using an ion implanter (not shown) to form the insulator layer 14. At this time, a short-circuit path 15 is formed by providing an island-shaped region where injection is not performed in order to form a peripheral portion of the control portion and a bypass passage for the dv / dt deviation current.

Next, the crystallinity of the silicon mosaiced by the oxygen ion implantation is restored by scanning and annealing the region into which the oxygen ions are implanted with a YAG laser or the like. After that, a P-type impurity such as boron is diffused at a high concentration so as to correspond to the short circuit 15, and a low resistance short circuit 16 is formed as shown in FIG. Further, when it is necessary to further enhance the effect of this short-circuit path, FIG.
It is effective to form the diffusion layer 17 of n-type impurities such as phosphorus so as to surround the boron diffusion layer as shown in FIG.

Next, by a commonly used method, for the power MOS FET portion, the n-well corresponding to the source 10 is formed in the silicon layer on the buried insulator layer 14 for the n-type layer control circuit portion. 18, a source / drain diffusion layer 19 and the like are formed, and a gate oxide film 21, a polysilicon gate 22 and the like are further formed. Then, after passing through other necessary processes, electrode wiring is performed using a metal layer. In this metal wiring, the low resistance short circuit 16 on the short circuit 15 described above is connected to the ground potential or the source potential of the MOS FET. FIG. 4 shows a partially enlarged view of an embodiment of the present invention thus obtained.

Next, the operation of the present invention will be described with reference to FIGS.
Will be explained. The waveform of the power MOS FET at the time of turn-off is as shown in FIG. 5 (a), and when the charge of the gate capacitance in the on state is discharged, the MOS FET rapidly shifts to the off state. , The source / drain current I _DS becomes zero, and the source / drain voltage V _DS rises at a high dv / dt of several thousand v / μs from the voltage of several V in the ON state to the power supply voltage (during resistive load). .. Due to this change in V _DS, the junction J ₁ is rapidly charged (this charging current is referred to as excursion current), and the excursion current flows, but the excursion current is buried in FIG. 5B. Blocked by the insulating layer 14 and flowing laterally in the P-well 13 forming the junction J ₁ , it flows through the short circuit path 14 to the power supply. Therefore, the control circuit MOS FET
And no other useful place.

If the short circuit 14 is not provided at all, a voltage of displacement current × R is generated in the P layer immediately below the insulating layer 14 due to the junction J ₁ and the sheet resistance R of the P well 13 of the insulating layer 14. To do. The sheet resistance of the insulator layer 14 is generally 100.
When it is Ω or more, and when the junction capacitance is about 1000 PF / cm ² or more, it may reach several tens of v in the central portion, and this voltage may cause a charging current of the embedded insulator layer 14 to flow. This charging current may cause the control circuit to erroneously make a difference. However, by providing the short-circuit path 15, it is possible to easily make the potential increase in the P well 13 due to this deviation current to several V or less, and the above-mentioned malfunction occurs. Can be completely prevented.

Further, if the resistance of the short-circuit path 15 is high, a deviation current may enter the control circuit, which also causes a malfunction of the control circuit. In order to prevent this, as shown in FIG. 6, the low resistance short circuit path 16 is provided with an n-type impurity diffusion layer 17 of an opposite conductivity type (in this embodiment, an n-type semiconductor layer opposite to a p-type semiconductor). It is desirable to have a structure surrounded by, so that the deviation current can be more reliably prevented from entering the control circuit portion. In this case, it is preferable that the n-type impurity diffusion layer 17 is not short-circuited with the electrode with respect to the low resistance short circuit path 16.

[0016]

As described above, the present invention forms an insulating layer in the well intermittently and in a plane to form a short circuit path in the vertical direction, and controls only on this insulating layer. Since the circuit is formed, the excursion current generated at the time of turning off the power element is blocked by the insulating layer and passes through the short circuit, and dv / dt at the time of turning off the power element, Dv / due to external noise
It is possible to prevent the displacement current of the junction due to dt or the like from flowing into the control circuit, and it is possible to prevent the malfunction of the control circuit unit.

In addition, a high-concentration impurity is diffused in the upper part of the short-circuit portion to connect with a low-potential power source, or a high-impurity concentration layer of opposite conductivity type which is not grounded is formed around the short-circuit path in which the high-concentration impurity is diffused. By allowing the current to flow, the influence of the excursion current can be more effectively reduced, and the potential generated by the excursion current can be reduced, so that malfunction of the control circuit can be prevented more effectively.

[Brief description of drawings]

FIG. 1 is a structural diagram of a semiconductor device of the present invention before O ⁻ implantation.

FIG. 2 is a configuration diagram at the time of forming an insulator layer of the semiconductor device of the present invention.

FIG. 3 is a structural diagram of a semiconductor device of the present invention when a short circuit is formed.

FIG. 4 is a structural diagram of an embodiment of a semiconductor device of the present invention.

FIG. 5 is a diagram illustrating an effect on dv / dt deviation current.

FIG. 6 is a structural diagram of another embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional semiconductor device.

[Explanation of symbols]

1 Semiconductor Chip 2 Vertical MOS FET Section 3 Control Circuit Section 4 Wire Bonding Pad 5 n ⁺ Region 6 Source of MOS FET of Control Circuit 7 Gate of MOS FET of Control Circuit 8 Drain of MOS FET of Control Circuit 9 n Region 10 Vertical MOS FET source 11 Vertical MOS FET gate 12 Vertical MOS FET drain 13 P-well 14 Insulator layer 15 Short circuit 16 Low resistance short 17 N-type impurity diffusion 18 N-well

Claims (4)

[Claims] 1. A control circuit for controlling and driving the power element in a well on a semiconductor substrate in which a power element of a vertical type is formed to flow a current from one main surface of the semiconductor substrate to the other main surface. In a semiconductor device provided with the structure, an insulating layer is intermittently and planarly formed in the well to form a short circuit path in a vertical direction, and a control circuit is formed only on the insulating layer. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the insulator layer is formed by a SIMOX method. 3. The semiconductor device according to claim 1, wherein a high-concentration impurity is diffused in the upper part of the short circuit and is connected to a low potential power source. 4. The semiconductor device according to claim 3, wherein a high-impurity concentration layer of the opposite conductivity type that is not grounded is formed around a short circuit path in which high-concentration impurities are diffused.