JP4531276B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device for driving a power device such as an inverter, and particularly to a technique for improving the malfunction tolerance.
[0002]
[Prior art]
FIG. 6 is a schematic configuration diagram for explaining the configuration of a conventional power device and power device driving apparatus. In this figure, Q1 and Q2 are N-channel insulated gate bipolar transistors which are power switching devices, and switch high voltage HV which is a main power source. A load is connected to the node N30, and D1 and D2 are free-wheeling diodes for protecting the N-channel insulated gate bipolar transistors Q1 and Q2 from the back electromotive voltage caused by the load connected to the node N30.
[0003]
Reference numeral 100 denotes a power device driving apparatus for driving the power switching devices Q1 and Q2, which operates in accordance with a high voltage side control input HIN for controlling the high voltage side power switching device Q1 and a low voltage side control input LIN for controlling the low voltage side power switching device Q2. . The power device driving apparatus 100 further includes a high voltage side driving unit 101 that drives the high voltage side power switching device Q1, a low voltage side driving unit 102 that drives the low voltage side power switching device Q2, and a control input processing unit 103.
[0004]
Here, for example, when the power switching devices Q1 and Q2 are simultaneously turned on, the through current flows through Q1 and Q2, and the current does not flow through the load, which is not preferable. The control input processing unit 103 performs processing on the control inputs HIN and LIN, such as preventing such a state from being caused by the control inputs HIN and LIN.
[0005]
HO is a high-voltage side drive signal output by the high-voltage side drive unit 101, and is connected to the control terminal of the power switching device Q1. Similarly, LO is a low-voltage side drive signal output by the low-voltage side drive unit 102, and is connected to the control terminal of the power switching device Q2.
[0006]
VCC is a low-voltage side fixed supply voltage serving as a power source for the low-voltage side drive unit 102, and is supplied from a low-voltage side fixed supply power source (not shown). VS is a high-voltage side floating offset voltage that becomes a reference potential of the high-voltage side drive unit 101. VB is a high voltage side floating supply absolute voltage serving as a power source for the high voltage side driving unit 101 and is supplied by a high voltage side floating power source (not shown). GND is a ground potential, and COM is a common ground. As shown in FIG. 6, the common ground COM and the high-voltage side floating offset voltage VS are connected to the emitter terminals of N-channel insulated gate bipolar transistors Q1 and Q2, respectively.
[0007]
Further, between the high-voltage side floating supply absolute voltage VB and the high-voltage side floating offset voltage VS, and between the common ground COM and the low-voltage side fixed supply voltage VCC, the power supply voltage supplied to the high-voltage side drive unit 101 and the low-voltage side drive unit 102 Are connected to capacitors C1 and C2 in order to follow the potential fluctuation accompanying the operation of the power device.
[0008]
With the above configuration, the main power source is switched by the power device based on the control inputs HIN and LIN.
[0009]
By the way, the high-voltage side drive unit 101 operates in a state where it is floating in potential with respect to the ground potential of the circuit, and therefore has a configuration including a level shift circuit for transmitting a drive signal to the high-voltage side circuit.
[0010]
FIG. 7 is a circuit diagram of the main part of the high-voltage side driving unit in the conventional power device driving apparatus. In this figure, the elements indicated by the symbols VB, HO, VS, and GND are the high-voltage side floating supply absolute voltage VB, the high-voltage side drive signal output HO, the high-voltage side floating offset voltage VS, This corresponds to the potential GND. Reference numeral 11 denotes a high breakdown voltage MOS as a switching element, which plays the role of the level shift circuit described above. Reference numeral 12 denotes a high voltage side drive signal output CMOS which is a switching element that includes a PMOS transistor and an NMOS transistor and outputs a high voltage side drive signal. Reference numeral 13 denotes a level shift resistor for setting the gate potential of the high-voltage side drive signal output CMOS 12, which plays a role corresponding to a pull-up resistor.
[0011]
The high voltage MOS 11 switches the high voltage side drive signal output CMOS 12 in accordance with the high voltage side control input LIN. The high-voltage side drive signal output CMOS 12 switches the voltage between the high-voltage side floating supply absolute voltage VB and the high-voltage side floating offset voltage VS and outputs a drive signal to the high-voltage side drive signal output HO. Drive the element.
[0012]
In the following description, the high voltage side drive signal output CMOS 12 and the level shift resistor 13 are collectively referred to as a high voltage side drive circuit.
[0013]
FIG. 8 is a cross-sectional view of a level shift circuit and a high voltage side drive circuit of a high voltage side drive unit in a conventional power device drive apparatus. In this figure, elements equivalent to those shown in FIGS. 6 and 7 are denoted by the same reference numerals, and detailed description thereof is omitted here. In FIG. 8, 21 is a p substrate, 22 and 23 are n− layers, and 24 is a p + diffusion layer. The p + diffusion layer 24 surrounding the high voltage MOS 11 reaches the p substrate 21. The high breakdown voltage MOS 11 is junction-separated by setting the potential of the p substrate 21 to the lowest potential (GND or COM potential) in the circuit. A p-well 25 is formed below the source electrode 40 and the gate electrode 41 of the high breakdown voltage MOS 11 and reaches the lower portion of the gate electrode 40 through the gate insulating film to form a channel region of the high breakdown voltage MOS 11. Further, a p + region 26 and an n + source region 27 are formed in the p well 25 so as to be in contact with the source electrode 40. An n + drain region 28 is formed so as to be in contact with the drain electrode 42 of the high voltage MOS 11.
[0014]
The drain terminal of the high voltage MOS 11 is connected to the gate terminals of the PMOS transistor and NMOS transistor of the high voltage side drive signal output CMOS 12, and the source terminal of the PMOS transistor and the high voltage side floating supply absolute voltage VB via the level shift resistor 13. Connected to.
[0015]
On the other hand, in the n− layer 23 where the high-voltage side drive signal output CMOS 12 is formed, an n + region 29 and a p + source region 30 are formed so as to be in contact with the source electrode 43 of the PMOS transistor, and are in contact with the drain electrode 45. A p + drain region 31 is formed. Reference numeral 44 denotes a PMOS gate electrode. The NMOS transistor of the high-voltage side drive signal output CMOS 12 is formed in the p-well 32. The n + drain region 32 is in contact with the NMOS drain electrode 46, and the n + source region 34 and p + 35 are in contact with the source electrode 48. Each is formed.
[0016]
Reference numeral 36 denotes an aluminum wiring. In general, the high-voltage side drive circuit composed of the high-voltage side drive signal output CMOS 12 and the level shift resistor 13 is shielded by surrounding it with aluminum wiring of the substrate potential as a high-voltage island. FIG. 9 is a plan view showing the layout of the aluminum wiring 36 provided on the high voltage island in the conventional power device driving apparatus. As shown in this figure, the aluminum wiring 36 is laid out so as to surround the high-voltage island, and is further in contact with the ground potential GND.
[0017]
In FIG. 8, the p + region 38 in the p well 25 is for reducing the contact resistance between the aluminum wiring 36 and the p well 25, and 39 is a field plate.
[0018]
With the above configuration, the level shift circuit and the high-voltage side drive circuit shown in FIG. 7 are formed.
[0019]
[Problems to be solved by the invention]
In the power device and the power device driving apparatus shown in FIG. 6, the high-voltage side floating offset voltage VS is common ground COM during the regeneration period, that is, the period when the freewheel diode D1 is turned on by the back electromotive voltage from the load connected to the node N30. May be at a lower potential. The negative fluctuation of the high voltage side floating offset voltage VS is transmitted to the high voltage side floating supply absolute voltage VB via the capacitor C1, and the potential of the high voltage side floating supply absolute voltage VB also varies negatively.
[0020]
When the high-voltage side floating supply absolute voltage VB varies negatively, in FIG. 8, the negative variation is transmitted to the n− layers 22 and 23 and is normally reverse-biased. The parasitic diode between the layer 22 (body / drain diode) and the parasitic diode between the p-well 25 and the n-layer 23 in the high-voltage side drive signal output CMOS 12 are turned on. In the following description, the parasitic diode between the p-well 25 and the n− layer 23 in the high-voltage side drive signal output CMOS 12 is referred to as a CMOS parasitic diode for convenience.
[0021]
The current from the body / drain diode of the high breakdown voltage MOS flows into the high voltage side floating supply absolute voltage VB through the level shift resistor 13. At that time, the output signal of the high voltage MOS 11, that is, the drive signal received by the high voltage side drive signal output CMOS 12 is kept at “H” level, and the high voltage side drive signal output HO of the high voltage side drive signal output CMOS 12 is “L”. It is a level.
[0022]
Thereafter, when the negative fluctuation of the high-voltage side floating offset voltage VS disappears, the potential of the high-voltage side floating supply absolute voltage VB also rises, and a reverse bias is applied to the body / drain diode again, and a level shift occurs from the high-voltage side floating supply absolute voltage VB. The reverse recovery current of the body / drain diode flows through the resistor. When the gate potential of the high-voltage drive signal output CMOS 12 becomes lower than the logical threshold due to a voltage drop generated in the level shift resistor by the reverse recovery current, the high-voltage drive signal output HO is switched to the “H” level.
[0023]
That is, both the power switching devices Q1 and Q2 shown in FIG. 6 are turned on, which is an undesirable state in which a through current flows through the power switching devices Q1 and Q2 and no current flows through the load.
[0024]
On the other hand, when the CMOS parasitic diode is turned on, a current flows into the n− layer 23. The high-voltage side drive signal output CMOS 12 has a parasitic thyristor due to the pnpn structure of the p + region 30, the n− layer 23, the p well 32, and the n + region 34, and flows from the CMOS parasitic diode into the n− layer 23. The supplied current acts as a trigger current for latching up the high-voltage side drive signal output CMOS 12. When this latch-up occurs, an excessive current flows through the high-voltage side drive signal output CMOS 12, and in some cases, a circuit or a component is damaged.
[0025]
By the way, in the power device driving apparatus shown in FIG. 6, a high-voltage diode is further connected such that the anode is at the low-voltage side fixed supply voltage VCC and the cathode is at the high-voltage side floating supply absolute voltage VB, and the capacitor C1 has a large capacity. Is used, the capacitor C1 is charged through the high voltage diode when the low voltage side power switching device Q2 is turned on, and the high voltage side floating power source that supplies the high voltage side floating supply absolute voltage VB can be made unnecessary. In general, this diode is called a bootstrap diode.
[0026]
FIG. 10 is a cross-sectional view of a high voltage diode used in a bootstrap diode of a conventional power device driving apparatus. In this figure, the n− layer 53 on the p-type substrate 21 is separated from the high voltage island and the high voltage MOS 22 by the p + diffusion layer 24. Reference numeral 50 denotes an anode electrode, and the anode of the high voltage diode is formed by the p well 54 and the p + region 55 inside thereof. Reference numeral 52 denotes a cathode electrode, and the n− layer 53 and the n + region 56 form a cathode of a high voltage diode.
[0027]
However, when this high-voltage diode is mounted as a bootstrap diode in a power device driving device, the anode potential of the high-voltage diode is the low-voltage side fixed supply voltage VCC, so that it is turned on even by a slight negative fluctuation of the high-voltage side floating offset voltage VS. A current is injected into the high pressure island. Therefore, compared to the case where an independent power source is used for the high-voltage side floating supply absolute voltage VB, the latch-up resistance of the high-voltage side drive signal output CMOS 12 is reduced, and as a result, the high-voltage side floating offset voltage VS of the power device driving device is There arises a problem that the malfunction tolerance against the fluctuation is lowered.
[0028]
The present invention has been made to solve the above-described problems, and a first object of the present invention is to prevent malfunction due to negative fluctuation of the high-voltage side floating offset voltage VS in a semiconductor device that drives a power device. It is to provide a high semiconductor device. A second object of the present invention is to provide a semiconductor device having a high tolerance for malfunction against negative fluctuation of the high-voltage-side floating offset voltage VS in a semiconductor device equipped with a bootstrap diode and driving a power device.
[0029]
[Means for Solving the Problems]
  The semiconductor device according to claim 1 includes a first switching element, a driving circuit that has a first resistor for setting a gate potential thereof, and outputs a driving signal to an external power converter, and a second switching element And a control signal is output to the first switching element of the drive circuit, and the drive circuit and a level shift circuit separated from the drive circuit are provided, and by electron beam irradiation and annealing,At least a p-type well and an n-type layer constituting the body / drain diode of the second switching element, and a p-type well and an n-type layer constituting the junction isolation, respectively.The lifetime is suppressed.
[0030]
  3. A semiconductor device according to claim 2, comprising a first switching element and a first resistor for setting a gate potential thereof, a driving circuit for outputting a driving signal to an external power converter, and a second switching element. A level shift circuit that outputs a control signal to the first switching element of the drive circuit and is separated from the drive circuit;Connected on the diffusion layer to perform the junction separation,And a shield wiring surrounding the drive circuit, wherein the shield wiring is divided into a plurality of parts.
[0031]
  The semiconductor device according to claim 3, having a first switching element and a first resistor for setting a gate potential thereof, a drive circuit for outputting a drive signal to an external power converter, and a second switching element And a level shift circuit that outputs a control signal to the first switching element of the drive circuit and is separated from the drive circuit, and includes a p of a parasitic diode formed by a pn junction in the junction separation Only some of the multiple wires that connect on the areaGround potentialIt is characterized by being directly connected to.
[0032]
  5. The semiconductor device according to claim 4, comprising a first switching element and a first circuit for setting a gate potential thereof, a driving circuit for outputting a driving signal to an external power converter, and a second switching element. For outputting a control signal to the first switching element of the drive circuit, for supplying a power supply for the drive circuit, and a level shift circuit joined and separated from the drive circuitBootstrapA diode, andBootstrapThe anode concentration is suppressed by not having a p + diffusion layer in the p-well which is the anode of the diode,BootstrapThe current flowing through the diode is suppressed.
[0033]
  6. The semiconductor device according to claim 5, comprising a first switching element and a first circuit for setting a gate potential thereof, a driving circuit for outputting a driving signal to an external power converter, and a second switching element. For outputting a control signal to the first switching element of the drive circuit, for supplying a power supply for the drive circuit, and a level shift circuit joined and separated from the drive circuitBootstrapA diode, andBootstrapIn series with the diodeSecondThese resistors are inserted.
[0034]
  7. The semiconductor device according to claim 6, comprising a first switching element and a first resistor for setting a gate potential thereof, a driving circuit for outputting a driving signal to an external power converter, and a second switching element. A level shift circuit that outputs a control signal to the first switching element of the drive circuit and is separated from the drive circuit, and a bootstrap diode for supplying power to the drive circuit The lifetime of the p-type well and the n-type layer constituting the bootstrap diode is suppressed by electron beam irradiation and annealing.
  A semiconductor device according to a seventh aspect is the semiconductor device according to any one of the first to fourth and sixth aspects, wherein the semiconductor device is further in series with a parasitic diode formed by a pn junction in the junction isolation. A second resistor is inserted.
  The semiconductor device according to claim 8 is the semiconductor device according to claim 5, further comprising a third resistor inserted in series with a parasitic diode formed by a pn junction in the junction isolation. And
  Claim 9The semiconductor device described inClaims 2 to 8The semiconductor device according to any one of the above, and further by electron beam irradiation and annealing,At least a p-type well and an n-type layer constituting the body / drain diode of the second switching element, and a p-type well and an n-type layer constituting the junction isolation, respectively.The lifetime is suppressed.
[0035]
  Claim 10The semiconductor device described inClaims 3 to 9A semiconductor device according to any one of the above,Connected on the diffusion layer to perform the junction separation,A shield wiring surrounding the drive circuit is provided, and the shield wiring is divided into a plurality of parts.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
<Embodiment 1>
As described above, in the semiconductor device shown in FIG. 8, that is, the power device driving device, when negative fluctuation of the high-voltage side floating offset voltage VS occurs, the p-well 25 in the high-breakdown-voltage MOS 11 that should normally be reverse-biased. And the n-layer 22 are turned on. The negative fluctuation of the high-voltage side floating offset voltage VS disappears, and the reverse recovery current when the forward bias is applied to the body / drain diode again causes a voltage drop in the level shift resistor. If the gate potential of the high-voltage drive signal output CMOS 12 becomes lower than the logical threshold due to this voltage drop, the high-voltage drive signal output HO is switched to the “H” level, resulting in malfunction. That is, the reverse recovery current of the body / drain diode causes a malfunction of the device.
[0038]
Therefore, it is possible to suppress the magnitude of the reverse recovery current of the body / drain diode, and to further reduce the time during which the reverse recovery current flows (reverse recovery time), the negative of the high-voltage side floating offset voltage VS of the power device driving device. This is effective to improve the malfunction tolerance against fluctuation.
[0039]
The magnitude of the reverse recovery current and the reverse recovery time strongly depend on the amount of carriers accumulated in the device and the lifetime. That is, by suppressing the amount of carriers accumulated in the body / drain diode and shortening the lifetime, it is possible to improve the malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage VS of the power device driving apparatus. .
[0040]
The semiconductor device according to the first embodiment of the present invention is a power device driving device in which the lifetime of carriers is suppressed by further annealing after irradiation with an electron beam.
[0041]
That is, in the present embodiment, the control of the lifetime of the semiconductor device uses electron beam irradiation. By using an electron beam, the process of controlling the lifetime can be performed after the wafer process, so there is no risk of contamination of the production facility. In addition, the lifetime can be easily controlled by the dose, so trimming is easy. There is an advantage of being. However, annealing (for example, 340 ° C., 60 minutes) is also performed because devices constituting the semiconductor device do not function only by electron beam irradiation.
[0042]
FIG. 1 is a diagram for comparing the current-voltage characteristics of the body / drain diode of the semiconductor device according to the first embodiment and the body / drain diode of the conventional semiconductor device at the time of forward bias. In this figure, 1a is the current-voltage characteristic of the body / drain diode of the semiconductor device after electron beam irradiation and annealing according to the first embodiment, and 1b is the current-voltage characteristic of the body / drain diode of the conventional semiconductor device. It is. As shown in this figure, the body / drain diode of the semiconductor device according to the present embodiment has a shorter lifetime than the conventional one, so that the amount of carriers accumulated in the diode can be suppressed. As a result, the forward current is reduced. Therefore, it is expected that the reverse recovery current is suppressed in the body / drain diode of the semiconductor device according to the present embodiment.
[0043]
FIG. 2 is a diagram for comparing the reverse recovery current characteristics of the body / drain diode of the semiconductor device according to the first embodiment and the body / drain diode of the conventional semiconductor device. In this figure, 2a is the reverse recovery current characteristic of the body / drain diode of the semiconductor device after electron beam irradiation and annealing according to the first embodiment, and 2b is the reverse recovery current characteristic of the body / drain diode of the conventional semiconductor device. It is. As shown in this figure, the body / drain diode of the semiconductor device according to the present embodiment has a forward current suppressed as shown in FIG. 1 as compared with the conventional one. The magnitude (peak value) of the recovery current is small. In addition, it can be seen that the reverse recovery time is shortened because the lifetime is suppressed.
[0044]
As described above, since the body / drain diode of the semiconductor device according to the present embodiment has a small reverse recovery current and a short reverse recovery time, the malfunction caused by the above-described reverse recovery current of the body / drain diode is prevented. Can be suppressed.
[0045]
By the way, not only the body / drain diode, but also the parasitic diode (CMOS) between the p-well 25 and the n− layer 23 in the high-voltage side drive signal output CMOS 12 in FIG. This is also effective for parasitic diodes).
[0046]
As described above, due to the negative fluctuation of the high-voltage side floating offset voltage VS, the current flowing into the n− layer 23 by turning on the CMOS parasitic diode is a trigger current for latching up the high-voltage side drive signal output CMOS 12. I will work. That is, suppressing the forward current of the parasitic diode is effective as a countermeasure for the latch-up problem of the high-voltage side drive signal output CMOS 12 due to the negative fluctuation of the high-voltage side floating offset voltage VS.
[0047]
Further, it is needless to mention that the forward current of the CMOS parasitic diode can be suppressed similarly to FIG. 1 by electron beam irradiation and annealing. That is, the electron beam irradiation and annealing also have the effect of improving the latch-up resistance caused by the forward current of the CMOS parasitic diode accompanying the negative fluctuation of the high-voltage side floating offset voltage VS.
[0048]
Therefore, the semiconductor device according to the present embodiment is also a semiconductor device having a high latch-up resistance caused by the forward current of the CMOS parasitic diode accompanying the negative fluctuation of the high-voltage side floating offset voltage VS.
[0049]
As described above, according to the semiconductor device according to the first embodiment, it is possible to solve the malfunction of the semiconductor device and the latch-up problem caused by the negative fluctuation of the high-voltage side floating offset voltage VS. In other words, it is possible to provide a semiconductor device having a high tolerance for malfunction against negative fluctuation of the high-voltage side floating offset voltage VS.
[0050]
<Embodiment 2>
As described in the first embodiment, by suppressing the forward current value of the parasitic diode (CMOS parasitic diode) between the p-well 25 and the n− layer 23 in the high-voltage side drive signal output CMOS 12 in FIG. The latch-up of the high-voltage side drive signal output CMOS 12 due to the negative fluctuation of the side floating offset voltage VS can be prevented. In the first embodiment, as the means, the lifetime of the CMOS parasitic diode is shortened, and the amount of carriers accumulated in the diode is suppressed.
[0051]
On the other hand, in the second embodiment, by increasing the resistance value of the path through which the forward current of the CMOS parasitic diode flows, the forward current value of the CMOS parasitic diode accompanying negative fluctuation of the high-voltage side floating offset voltage VS is suppressed, and the semiconductor device Improve malfunction tolerance.
[0052]
As described above, the high-voltage side drive circuit composed of the high-voltage side drive signal output CMOS 12 and the level shift resistor 13 is shielded as a high-voltage island by surrounding it with aluminum wiring of the substrate potential. The aluminum wiring is inserted in series between the CMOS parasitic diode and the ground potential GND, as can be seen from FIGS. When a reverse bias is applied to the CMOS parasitic diode due to negative fluctuation of the high-voltage side floating offset voltage VS, the forward current flows from GND to the CMOS parasitic diode via the aluminum wiring.
[0053]
  FIG. 3 is a plan view showing a layout of aluminum wiring provided on the high-pressure island in the semiconductor device according to the second embodiment. In the present embodiment, the aluminum wiring 3 has the same sectional structure as the aluminum wiring 36 shown in FIG. 8, but is divided into a plurality of parts as shown in FIG. That is, each aluminum wiring is not directly contacted with the ground potential GND, but is connected to the GND with p+ AreaThrough. p+ AreaSince the resistance value is larger than that of the aluminum wiring, the resistance value between the GND and the CMOS parasitic diode becomes larger than that of the semiconductor device having the conventional aluminum wiring layout shown in FIG. As a result, the resistance value of the path through which the forward current of the CMOS parasitic diode flows is increased, thereby suppressing the forward current value of the CMOS parasitic diode.
[0054]
Therefore, when the CMOS parasitic diode is turned on due to the negative fluctuation of the high-voltage side floating offset voltage VS of the semiconductor device, the current value flowing into the high-voltage island can be suppressed. In other words, the occurrence of latch-up in the high-voltage side drive signal output CMOS 12 can be suppressed.
[0055]
As described above, according to the semiconductor device according to the second embodiment, the latch-up of the semiconductor device caused by the negative fluctuation of the high-voltage side floating offset voltage VS can be suppressed. In other words, it is possible to provide a semiconductor device having a high tolerance for malfunction against negative fluctuation of the high-voltage side floating offset voltage VS.
[0056]
<Embodiment 3>
Also in the third embodiment, the resistance value of the path through which the forward current of the CMOS parasitic diode flows is increased as means for suppressing the forward current value of the CMOS parasitic diode due to the negative fluctuation of the high-voltage side floating offset voltage VS.
[0057]
FIG. 4 is an enlarged cross-sectional view of the junction isolation part of the high-pressure island in the semiconductor device according to the third embodiment. In this figure, reference numeral 4 denotes a p-well, which has a structure in which the high-pressure island side of the p-well 25 shown in FIG. 8 is separated from the p + diffusion layer 24 and an n-layer 23 is interposed therebetween. Reference numeral 31 denotes a resistor. Since the other elements are the same as those given the same reference numerals as those shown in FIG. 8, detailed description thereof is omitted here.
[0058]
In such a configuration, a CMOS parasitic diode that mainly injects a current into the high-voltage island when the high-voltage side floating offset voltage VS is negatively changed is formed between the p-well 30 and the n− layer 22. The forward current due to the negative fluctuation of the side floating offset voltage VS flows from the GND to the CMOS parasitic diode through the p substrate, the p + diffusion layer, the resistor 31, and the p + region 38. Therefore, the resistance value of the forward current path of the CMOS parasitic diode can be increased by increasing the resistance value of the resistor 31 inserted between the aluminum wiring 36 and the p + diffusion layer. This can suppress the value of the current flowing into the high-voltage island when the CMOS parasitic diode is turned on due to the negative fluctuation of VS. In other words, the occurrence of latch-up in the high-voltage side drive signal output CMOS 12 can be suppressed.
[0059]
As described above, according to the semiconductor device according to the third embodiment, the latch-up of the semiconductor device caused by the negative fluctuation of the high-voltage side floating offset voltage VS can be suppressed. In other words, it is possible to provide a semiconductor device having a high tolerance for malfunction against negative fluctuation of the high-voltage side floating offset voltage VS.
[0060]
<Embodiment 4>
As described above, when a high voltage diode is mounted as a bootstrap diode in the power device driving device, there is a problem that the latch-up resistance of the high voltage side drive signal output CMOS against negative fluctuation of the high voltage side floating offset voltage VS is lowered. It was. This is caused by the current injected from the high voltage diode into the high voltage island when the high voltage side floating offset voltage VS is negatively changed.
[0061]
Therefore, by suppressing the value of the forward current flowing through the bootstrap diode, it is possible to suppress a decrease in the latch-up resistance due to the mounting of the bootstrap diode.
[0062]
FIG. 5 is a cross-sectional view of the high-voltage diode in the semiconductor device according to the fourth embodiment. The conventional high voltage diode shown in FIG. 10 has the same configuration except that the p + region 55 does not exist in the p well 54. That is, there is no p + region in the anode of the high voltage diode that is the bootstrap diode of the semiconductor device according to the present embodiment.
[0063]
Thereby, the injection of carriers into the anode is suppressed, and the value of the forward current flowing through the high voltage diode is suppressed. Therefore, it is possible to suppress the current injected from the bootstrap diode into the high-voltage island when the high-voltage side floating offset voltage VS is negatively changed. As a result, against the negative fluctuation of the high-voltage side floating offset voltage VS accompanying the mounting of the bootstrap diode A reduction in malfunction tolerance can be suppressed.
[0064]
As described above, according to the semiconductor device of the fourth embodiment, it is possible to suppress a decrease in the latch-up resistance of the high-voltage side drive signal output CMOS that accompanies the mounting of the bootstrap diode. That is, it is possible to provide a semiconductor device with a high tolerance for malfunction against negative fluctuations in the high-voltage side floating offset voltage VS in a semiconductor device mounted with a bootstrap diode and driving a power device.
[0065]
Needless to say, the electron beam irradiation and annealing described in the description of Embodiment 1 can suppress the forward current value of the high-voltage diode used for the bootstrap diode. Therefore, by applying electron beam irradiation and annealing to the bootstrap diode, the value of the forward current flowing through the bootstrap diode at the time of negative fluctuation of the high-voltage side floating offset voltage VS can be suppressed. It is clear that the decrease in the latch-up resistance of the high-voltage side drive signal output CMOS due to the mounting of the bootstrap diode can be suppressed.
[0066]
Further, it is clear that the forward current value of the high voltage diode can be suppressed even if a resistor is inserted in series with the high voltage diode, for example, between the power source and the anode of the high voltage diode, in the same way as in the third embodiment. As in the fourth embodiment, it is possible to suppress a decrease in the latch-up resistance of the high-voltage side drive signal output CMOS that accompanies the mounting of the bootstrap diode.
[0067]
【The invention's effect】
  As described above, according to the semiconductor device of claim 1, by electron beam irradiation and annealing,At least a p-type well and an n-type layer constituting the body / drain diode of the second switching element, and a p-type well and an n-type layer constituting the junction isolation, respectively.Since the lifetime is suppressed, the current flowing through the parasitic diode in the semiconductor device that is turned on with negative fluctuation of the high-voltage side floating offset voltage is suppressed, and the amount of carriers accumulated in the parasitic diode is also suppressed. It has been.
[0068]
Therefore, the value of the reverse recovery current of the parasitic diode of the second switching element that flows through the first resistor when the negative fluctuation of the high-voltage side floating offset voltage disappears becomes small, and the reverse recovery time becomes short. Therefore, malfunction of the first switching element caused by a voltage drop generated in the first resistor can be suppressed.
[0069]
Furthermore, the current flowing through the parasitic diode of the first switching element that flows when the high-voltage side floating offset voltage fluctuates negatively can be suppressed, and latch-up of the first switching element caused by the current can be suppressed.
[0070]
Therefore, it is possible to improve the malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage in the semiconductor device.
[0071]
  According to the semiconductor device of claim 2,Connected on the diffusion layer to perform the junction separation,Since the shield wiring that surrounds the drive circuit is divided into a plurality of parts, the resistance value of the current path that flows through the first switching element that is turned on increases as the high-voltage-side floating offset voltage varies negatively.
[0072]
Therefore, the current flowing through the parasitic diode of the first switching element that flows when the high-voltage side floating offset voltage varies negatively can be suppressed, and the latch-up of the first switching element caused by the current can be suppressed.
[0073]
Therefore, it is possible to improve the malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage in the semiconductor device.
[0074]
  According to the semiconductor device of the third aspect, only a part of the plurality of wirings connected to the p region of the parasitic diode formed by the pn junction in the junction isolation is provided.Ground potentialSince the resistance value of the path through which the forward current of the parasitic diode flows is increased, the resistance value of the current path flowing through the first switching element that is turned on with a negative fluctuation of the high-voltage side floating offset voltage is increased. .
[0075]
Therefore, the current flowing through the parasitic diode of the first switching element that flows when the high-voltage side floating offset voltage varies negatively can be suppressed, and the latch-up of the first switching element caused by the current can be suppressed.
[0076]
Therefore, it is possible to improve the malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage in the semiconductor device.
[0077]
  According to the semiconductor device of claim 4, for supplying power to the drive circuitBootstrapThe anode concentration is suppressed by having no p + diffusion layer in the p-well which is the anode of the diode,BootstrapThe current flowing through the diode is suppressed. Therefore, when the high side floating offset voltageBootstrapThe current flowing from the diode into the first switching element can be suppressed. Therefore, it is possible to solve the problem that the latch-up resistance of the semiconductor device is reduced by the current.
[0078]
  Therefore, to supply power for the drive circuitBootstrapIt is possible to improve a malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage in a semiconductor device including a diode.
[0079]
  According to the semiconductor device of claim 5, for supplying power to the drive circuitBootstrapSince the second resistor is inserted in series with the diode, when the high-voltage side floating offset voltage fluctuates negativelyBootstrapThe current flowing from the diode into the first switching element can be suppressed. Therefore, it is possible to solve the problem that the latch-up resistance of the semiconductor device is reduced by the current.
[0080]
  Therefore, to supply power for the drive circuitBootstrapIt is possible to improve a malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage in a semiconductor device including a diode.
[0081]
  According to the semiconductor device of claim 6, since the lifetimes of the p-type well and the n-type layer constituting the bootstrap diode are suppressed by electron beam irradiation and annealing, negative fluctuation of the high-voltage side floating offset voltage Sometimes the current flowing from the bootstrap diode into the first switching element can be suppressed.
  Therefore, it is possible to solve the problem that the latch-up resistance of the semiconductor device is reduced by the current. Accordingly, it is possible to improve a malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage in a semiconductor device including a bootstrap diode for supplying power to the drive circuit.
  According to the semiconductor device of the seventh and eighth aspects, since the resistor is inserted in series with the parasitic diode formed by the pn junction in the junction isolation, the first device that is turned on in accordance with the negative fluctuation of the high-voltage side floating offset voltage. The resistance value of the current path flowing through one switching element increases.
  Therefore, the current flowing through the parasitic diode of the first switching element that flows when the high-voltage side floating offset voltage fluctuates negatively can be suppressed, and the latch-up of the first switching element caused by the current can be suppressed. Therefore, it is possible to improve the malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage in the semiconductor device.
  Claim 9According to the semiconductor device described in (2), the lifetime is suppressed by electron beam irradiation and annealing. By electron beam irradiation and annealing,At least a p-type well and an n-type layer constituting the body / drain diode of the second switching element, and a p-type well and an n-type layer constituting the junction isolation, respectively.Since the lifetime is suppressed, the current flowing through the parasitic diode in the semiconductor device that is turned on with negative fluctuation of the high-voltage side floating offset voltage is suppressed, and the amount of carriers accumulated in the parasitic diode is also suppressed. It has been.
[0082]
Therefore, the value of the reverse recovery current of the parasitic diode of the second switching element that flows through the first resistor when the negative fluctuation of the high-voltage side floating offset voltage disappears becomes small, and the reverse recovery time becomes short. Therefore, malfunction of the first switching element caused by a voltage drop generated in the first resistor can be suppressed.
[0083]
Furthermore, the current flowing through the parasitic diode of the first switching element that flows when the high-voltage side floating offset voltage fluctuates negatively can be suppressed, and latch-up of the first switching element caused by the current can be suppressed.
[0084]
Therefore, it is possible to improve the malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage in the semiconductor device.
[0085]
  Claim 10According to the semiconductor device described inConnected on the diffusion layer to perform the junction separation,Since the shield wiring that surrounds the drive circuit is divided into a plurality of parts, the resistance value of the current path that flows through the first switching element that is turned on increases as the high-voltage side floating offset voltage varies negatively.
[0086]
Therefore, the current flowing through the parasitic diode of the first switching element that flows when the high-voltage side floating offset voltage varies negatively can be suppressed, and the latch-up of the first switching element caused by the current can be suppressed.
[0087]
Therefore, it is possible to improve the malfunction tolerance against negative fluctuation of the high-voltage side floating offset voltage in the semiconductor device.
[Brief description of the drawings]
FIG. 1 is a diagram for comparing current-voltage characteristics of a body / drain diode of a semiconductor device according to a first embodiment and a body / drain diode of a conventional semiconductor device at the time of forward bias.
FIG. 2 is a diagram for comparing reverse recovery current characteristics of the body / drain diode of the semiconductor device according to the first embodiment and the body / drain diode of the conventional semiconductor device;
FIG. 3 is a plan view showing a layout of aluminum wiring provided on a high-pressure island in the semiconductor device according to the second embodiment.
4 is an enlarged cross-sectional view of a junction separation part in a high-pressure island in a semiconductor device according to a third embodiment. FIG.
5 is a cross-sectional view of a high voltage diode in a semiconductor device according to a fourth embodiment. FIG.
FIG. 6 is a schematic configuration diagram for explaining a configuration of a conventional power device and a power device driving apparatus.
FIG. 7 is a circuit diagram of a main part of a high voltage side driving unit in a conventional power device driving apparatus.
FIG. 8 is a cross-sectional view of a level shift circuit and a high voltage side drive circuit of a high voltage side drive unit in a conventional power device drive device.
FIG. 9 is a plan view showing a layout of aluminum wiring provided on a high-pressure island in a conventional power device driving apparatus.
FIG. 10 is a cross-sectional view of a high voltage diode used for a bootstrap diode of a conventional power device driving apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1a Current-voltage characteristic of parasitic diode of semiconductor device according to the present invention subjected to electron beam irradiation and annealing treatment, 1b Current-voltage characteristic of parasitic diode of conventional semiconductor device, 2a Book subjected to electron beam irradiation and annealing treatment Reverse recovery current characteristic of parasitic diode of semiconductor device according to invention, 2b Reverse recovery current characteristic of parasitic diode of conventional semiconductor device, 3,36 aluminum wiring, 4 p well, 5 resistance, 21p substrate, 23, 53 n-layer 24 p + diffusion region, 29, 56 n + region, 29, 51 field plate, 30 p + region, 43 source electrode, 50 anode electrode, 52 cathode electrode, VCC low voltage side fixed supply voltage.

Claims (10)

A drive circuit having a first switching element and a first resistor for setting a gate potential thereof, and outputting a drive signal to an external power converter;
A level shift circuit that has a second switching element, outputs a control signal to the first switching element of the drive circuit, and is separated from the drive circuit,
The lifetime of at least the p-type well and n-type layer constituting the body / drain diode of the second switching element and the p-type well and n-type layer constituting the junction isolation are suppressed by electron beam irradiation and annealing. Being
A semiconductor device. A drive circuit having a first switching element and a first resistor for setting a gate potential thereof, and outputting a drive signal to an external power converter;
A level shift circuit that has a second switching element, outputs a control signal to the first switching element of the drive circuit, and is separated from the drive circuit;
A shield wiring connected to the diffusion layer for performing the junction separation and surrounding the drive circuit;
The shield wiring is divided into a plurality of pieces,
A semiconductor device. A drive circuit having a first switching element and a first resistor for setting a gate potential thereof, and outputting a drive signal to an external power converter;
A level shift circuit that has a second switching element, outputs a control signal to the first switching element of the drive circuit, and is separated from the drive circuit,
Only a part of a plurality of wirings connected to a p region of a parasitic diode formed by a pn junction in the junction isolation is directly connected to a ground potential . A drive circuit having a first switching element and a first resistor for setting a gate potential thereof, and outputting a drive signal to an external power converter;
A level shift circuit that has a second switching element, outputs a control signal to the first switching element of the drive circuit, and is separated from the drive circuit;
A bootstrap diode for supplying power to the drive circuit;
The suppressed anode concentration by no p + diffusion layer in the p-in the well is the anode of the bootstrap diode, the current flowing through the bootstrap diode is suppressed,
A semiconductor device. A drive circuit having a first switching element and a first resistor for setting a gate potential thereof, and outputting a drive signal to an external power converter;
A level shift circuit that has a second switching element, outputs a control signal to the first switching element of the drive circuit, and is separated from the drive circuit;
A bootstrap diode for supplying power to the drive circuit, and a second resistor is inserted in series with the bootstrap diode,
A semiconductor device. A drive circuit having a first switching element and a first resistor for setting a gate potential thereof, and outputting a drive signal to an external power converter;
A level shift circuit that has a second switching element, outputs a control signal to the first switching element of the drive circuit, and is separated from the drive circuit;
A bootstrap diode for supplying power to the drive circuit;
The lifetime of the p-type well and the n-type layer constituting the bootstrap diode is suppressed by electron beam irradiation and annealing.
A semiconductor device. The semiconductor device according to any one of claims 1 to 4 and claim 6, further comprising:
A second resistor is inserted in series with the parasitic diode formed by the pn junction in the junction isolation;
A semiconductor device. 6. The semiconductor device according to claim 5 , further comprising:
A third resistor is inserted in series with the parasitic diode formed by the pn junction in the junction isolation;
A semiconductor device. The semiconductor device according to claim 2, further comprising:
The lifetime of at least the p-type well and n-type layer constituting the body / drain diode of the second switching element and the p-type well and n-type layer constituting the junction isolation are suppressed by electron beam irradiation and annealing. Being
A semiconductor device. The semiconductor device according to any one of claims 3 to 9, further comprising:
A shield wiring connected to the diffusion layer for performing the junction separation and surrounding the drive circuit;
The shield wiring is divided into a plurality of pieces,
A semiconductor device.

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