JPH05267669A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To prevent generation of exfoliation from a source electrode and a drain electrode, while high dielectric strength is obtained by using an insulating film having both low stress properties as a channel protecting film and properties excellent in adhesion. CONSTITUTION:After a gate electrode 2 is formed on a transparent insulating substrate 1, at least the following are formed in order by applying a P-CVD method; a gate insulating film 3, an active semiconductor layer 4, and a channel protecting film composed of two layers, i.e., a low stress channel protecting film 5A and a channel protecting film 5B whose adhesion is improved. After the channel protecting film composed of the two layers is patterned to be a gate electrode pattern, an electrode contact layer 7 and a Ti film are formed. By patterning the Ti film, the electrode contact layer 7 and the active semiconductor layer 4, a source electrode 8S and a drain electrode 8D which cover a part of the channel protecting film are formed, and element isolation is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display (l
liquid crystal display: LC
D), or electroluminescence (elec)
thin film transistor (thin film tram) used for driving a troluminance (EL) or the like.
The invention relates to an improved method of manufacturing a transistor (TFT).

At present, LCDs and the like are required to have large screens, and it is no exaggeration to say that "manufacturing yield = manufacturing yield of TFTs". Therefore, the development of manufacturing technology in which no single defective TFT appears Is expected.

[0003]

11 to 17 are explanatory views of a TFT in a process main part for explaining a conventional example, in which a left side is a main part plane, and a right side is a main part cut side surface. Respectively, and will be described below with reference to these figures. Incidentally, for the sake of simplicity, in the explanatory view showing the plane of the main part, the layers above the gate electrode are appropriately omitted.

See FIG. 11 11- (1) By applying the sputtering method, T having a thickness of, for example, 800 [Å] is formed on the transparent insulating substrate 1 made of glass.
The i-film is formed and the Ti film is patterned by applying an ordinary lithography technique to the gate electrode 2
To form.

11- (2) Plasma Chemical Vapor Deposition
l vaporposition: P-CVD)
Depending on the application of the method, the thickness, for example 3000 [Å]
Gate insulating film 3 made of SiN having a thickness of, for example, 150
An operating semiconductor layer 4 of [Å] made of amorphous Si and a channel protection film 5 made of SiN having a thickness of, for example, 1400 [Å] are sequentially formed.

See FIG. 12 12- (1) By applying a resist process in the lithographic technique, a resist film is formed on the entire surface, ultraviolet rays are irradiated from the back surface of the substrate 1 and then development is performed, and then a gate is formed. Electrode 2
The resist film is left only on the top. In the drawing, this resist film is designated by the symbol 6.

See FIG. 13 13- (1) The protective film 5 is patterned using the resist film 6 as a mask by applying a wet etching method using a buffer hydrofluoric acid as an etchant. 13- (2) The resist film 6 used as the mask is peeled off.

See FIG. 14 14- (1) By applying the P-CVD method, the thickness is, for example, 500.
A contact layer 7 made of n ⁺ -amorphous Si of [Å] is formed. 14- (2) By applying the sputtering method, the thickness, for example, 1
A Ti film of 000 [Å] is formed.

15- (1) A resist film having a source electrode pattern and a drain electrode pattern is formed by applying a resist process in the lithography technique.

15- (2) Reactive ion etching using Cl type gas as etching gas
By applying the g: RIE method, the Ti film, the n ⁺ -amorphous Si electrode contact layer 7, and the amorphous Si operating semiconductor layer 4 are patterned using the resist film as a mask. After this step, the source electrode 8S and the drain electrode 8D made of a Ti film are formed, and element isolation is performed.

See FIG. 16 16- (1) By applying the sputtering method, the thickness is, for example, 5
000 [Å] Mo film is formed. 16- (2) Resist process in lithography technology, and
By applying a wet etching method using a phosphoric acid aqueous solution as an etchant, the Mo film is patterned to form the drain bus line 9.

See FIG. 17 17- (1) By applying the sputtering method, the thickness is, for example, 8
00 (Å) ITO (indium tin oxide)
e) Form a film.

17- (2) Resist process in lithography technology, and
The ITO film is patterned by applying a wet etching method using a hydrochloric acid-based aqueous solution as an etchant to form the pixel electrode 10.

Although only one TFT formed in this manner is shown in the figure, it goes without saying that it is actually formed in a matrix and each corresponds to a pixel of the LCD.

[0015]

Generally, a thin film formed by the P-CVD method has a higher withstand voltage as it has a lower stress. Therefore, in the case of a TFT, the thin film is used as a gate insulating film or a channel protective film. It is required to use a stress insulating film.

Further, since the channel protective film in the TFT also has a role of stopping etching, it is also required that the film has a low etching rate against an etchant such as buffer hydrofluoric acid.

As the insulating film having a low stress and a low etching rate, it is widely practiced to add H ₂ during the formation of a SiN film. However, after exposing the Si ₂ N ₂ added film to the atmosphere, If another film is formed on top of it, the adhesion is very poor and it often peels off.

In the manufacturing process of the TFT, as is apparent from FIG. 17, a part of the source electrode 8S and a part of the drain electrode 8D are formed on the channel protective film 5 with the electrode contact layer 7 interposed therebetween. However, there is a problem that peeling occurs at a portion indicated by an arrow in FIG.

If peeling occurs, the characteristics of the TFT naturally deteriorate, and after the panel is formed as an LCD, the color filter facing the TFT matrix through the liquid crystal is naturally formed. This causes the point defect to occur when the ITO film is touched, and the entire LCD becomes defective.

According to the present invention, an insulating film having both a low stress property and a good adhesive property is used as a channel protection film, and a high withstand voltage is obtained, but peeling from a source electrode or a drain electrode does not occur. To do so.

[0021]

FIG. 1 and FIG. 2 are side sectional views showing a main part of a TFT in a process step for explaining the principle of the present invention, and are used in FIGS. 11 to 17. The same symbols as those used to represent the same parts or have the same meanings.

1- (1) In the same manner as the conventional technique described above, a gate electrode 2 made of a Ti film is formed on a transparent insulating substrate 1 made of glass.
Then, the gate insulating film 3 made of SiN and the operating semiconductor layer 4 made of amorphous Si are formed.

1- (2) This step is a series of steps from the step 1- (1), but since it is one of the characteristic features of the present invention, it will be described in a separate section. For example, film formation is performed while adding H ₂ to form a channel protection film 5A made of low-stress SiN, and then N ₂ is added without adding H _2.
A channel protective film 5B made of SiN is formed in which Si is made smaller than SiN having low stress to enhance adhesion. That is, the channel protective film is composed of two layers having different properties. Since H ₂ is not added to the channel protective film 5B having enhanced adhesion, the channel protective film 5B has a higher stress than the low stress channel protective film 5A, and is thin so as not to increase the stress of the entire channel protective film. The film thickness. Here, low stress means 2 × 10 ⁹ [dyne /
cm ² ], which means that it is less than or equal to. Further, the etching rate of the channel protective films 5B and 5A with respect to the etchant, for example, buffered hydrofluoric acid is 5B> 5.
It is desirable to set to A. The reason for this is that when 5B <5A, the lower channel protection film 5A is formed when etching is performed.
On the other hand, the channel protection film 5B in the upper layer is in an overhang state, and later, n ⁺ -amorphous Si
This is due to the occurrence of step breakage when the electrode contact layer made of and a Ti film to be an electrode are formed.

See FIG. 2 2- (1) After that, the resist film is formed, ultraviolet rays are irradiated from the rear surface of the substrate 1, and development is performed in the same manner as in the conventional technique, and only on the gate electrode 2. Leave the resist film. 2- (2) After patterning the protective films 5B and 5A using the resist film as a mask, the resist film used as the mask is peeled off.

2- (3) An electrode contact layer 7 made of n ⁺ -amorphous Si and a Ti film are sequentially formed. 2- (4) A resist film having a source electrode pattern and a drain electrode pattern is formed.

2- (5) Ti film, n ⁺ -amorphous S using a resist film having a source electrode pattern and a drain electrode pattern as a mask
The i electrode contact layer 7 and the amorphous Si operating semiconductor layer 4 are patterned to form a source electrode 8 made of a Ti film.
The S and drain electrodes 8D are formed and the elements are separated.

In the TFT thus obtained, the channel protective film maintains a low stress and has a high withstand voltage, and the adhesiveness with the source electrode 8S and the drain electrode 8D formed via the electrode contact layer 7 is high. Is good.

From the above, in the method of manufacturing a thin film transistor according to the present invention, (1) a gate electrode (eg, gate electrode 2G) is formed on a transparent insulating substrate (eg, transparent insulating substrate 1). And then adhere to at least the gate insulating film (for example, the gate insulating film 3) and the operating semiconductor layer (for example, the operating semiconductor layer 4) and the low stress channel protective film (for example, the channel protective film 5A) by applying the plasma chemical vapor deposition method. And a channel protection film (for example, the channel protection film 5B) having enhanced properties are sequentially formed, and then the two-layer channel protection film is patterned by self-alignment with the gate electrode. The step of forming an electrode contact layer (for example, the electrode contact layer 7) and an electrode material film (for example, a Ti film) after that. Patterning the polar contact layer and the operating semiconductor layer to form a source electrode (for example, source electrode 8S) and a drain electrode (for example, drain electrode 8D) that hang on a part of the channel protection film, and perform element isolation. It is characterized by being

(2) In the above-mentioned (1), in the atmosphere in which the channel protective film (for example, the channel protective film 5B) of which the adhesion is enhanced among the two layers of channel protective film is a SiN film and H ₂ is not added Is characterized in that the amount of Si of Si / N is formed to be larger than that of a low stress channel protective film (for example, channel protective film 5A) or a gate insulating film (for example, gate insulating film 3). Alternatively,

(3) In the above (1), the low-stress channel protective film of the two-layer channel protective film is SiO _2.
It is characterized in that it is formed by using.

[0031]

By adopting the above-mentioned means, the side of the two-layer channel protective layer on which the source electrode and the drain electrode are formed, that is, the channel protective layer on the upper side has the conventional adhesiveness with the electrode contact layer. The peeling of the source electrode and the drain electrode is prevented because it is more than five times better than the low stress single layer film, and moreover, in the lower channel protective layer which occupies most of the channel protective layer. Since the stress is kept low and dominates the stress of the entire channel protective layer, lowering of the dielectric strength does not substantially pose a problem.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 3 to 10 are explanatory views of a TFT in a process main part for explaining one embodiment of the present invention, in which a left side is a main part plane and a right side is a main part. Each of the cut side surfaces is shown, and will be described below with reference to these drawings. For the sake of simplicity, in the explanatory view showing the plane of the main part, the layers above the gate electrode are omitted as appropriate, and
The same symbols as those used in FIGS. 1 and 2 and FIGS. 11 to 17 represent the same parts or have the same meanings.

See FIG. 3 3- (1) By applying the sputtering method, T having a thickness of, for example, 800 [Å] is formed on the transparent insulating substrate 1 made of glass.
An i film is formed. 3- (2) A resist film having a pattern of gate electrodes and gate bus lines is formed by applying a resist process in lithography technology.

3- (3) By applying the RIE method using a Cl-based gas as an etching gas, the resist film formed in step 3- (2) is used as a mask to form in step 3- (1). The Ti film is patterned to form the gate electrode 2G and the gate bus line 2B.

See FIG. 4. 4- (1) By applying the P-CVD method, the thickness is, for example, 30
A gate insulating film 3 made of 00 [Å] SiN and an operating semiconductor layer 4 made of amorphous Si having a thickness of, for example, 150 [Å] are sequentially formed.

4- (2) Subsequently, by applying the P-CVD method, H ₂
In the atmosphere where S is added, for example, a thickness of 1000 [Å] S
In the low-stress channel protection film 5A made of iN, and in an atmosphere in which H ₂ is not added, the Si / N value is increased, that is, the Si amount is increased and the adhesion is made of SiN having a thickness of, for example, 200 [Å]. The channel protection film 5B having enhanced properties is sequentially formed.

See FIG. 5 5- (1) By applying a resist process in the lithographic technique, a resist film is formed on the entire surface, and ultraviolet rays are irradiated from the back surface of the substrate 1 and then development is performed to form a gate. Electrode 2
The resist film is left only on G. In the figure,
This resist film is designated by symbol 6.

See FIG. 6 6- (1) By applying a wet etching method using a buffer hydrofluoric acid (for SiN) as an etchant, the channel protection films 5B and 5A are formed with the resist film 6 as a mask. Pattern into a pattern. 6- (2) The resist film 6 used as the mask is peeled off.

See FIG. 7 7- (1) By applying the P-CVD method, an electrode contact layer 7 made of n ⁺ -amorphous Si having a thickness of, for example, 500 [Å] is formed on the entire surface. 7- (2) A Ti film having a thickness of, for example, 1000 [Å] is formed on the entire surface by applying the sputtering method.

See FIG. 8 8- (1) A resist film having a source electrode pattern and a drain electrode pattern is formed by applying a resist process in the lithography technique.

8- (2) RIE using (BCl ₃ + Cl ₂ ) as etching gas
By applying the method, T
The i film, the n ⁺ -amorphous Si electrode contact layer 7, and the amorphous Si operating semiconductor layer 4 are patterned.
After this step, the source electrode 8S and the drain electrode 8D made of a Ti film are formed, and element isolation is performed.

See FIG. 9 9- (1) By applying the sputtering method, the thickness is, for example, 5
000 [Å] Mo film is formed. 9- (2) Resist process in lithography technology, and
By applying a wet etching method using a phosphoric acid aqueous solution as an etchant, the Mo film is patterned to form the drain bus line 9.

See FIG. 10. 10- (1) By applying the sputtering method, the thickness is, for example, 8
An ITO film of 00 [Å] is formed.

10- (2) Resist process in lithography technology, and
The ITO film is patterned by applying a wet etching method using a hydrochloric acid-based aqueous solution as an etchant to form the pixel electrode 10.

The withstand voltage of the channel protective film in the TFT obtained as described above is maintained sufficiently high, and
It goes without saying that the source electrode and the drain electrode are not peeled off. The present invention is not limited to the above-described embodiments, and many modifications can be made by applying ordinary techniques. For example, it is possible to replace the channel protective film made of low stress SiN with a channel protective film made of SiO ₂ .

[0046]

In the method of manufacturing a thin film transistor according to the present invention, the gate electrode is formed on the transparent insulating substrate, and then the plasma chemical vapor deposition method is applied to the gate insulating film, the operating semiconductor layer and the low dielectric layer. A channel protective film consisting of two layers of a channel protective film for stress and a channel protective film with enhanced adhesion is sequentially formed, and the channel protective film consisting of two layers is patterned into a gate electrode pattern, and then an electrode contact layer and an electrode material. A film is formed, and the electrode material film, the electrode contact layer, and the operating semiconductor layer are patterned to form a source electrode and a drain electrode that hang on a part of the channel protective film, and at the same time, element isolation is performed.

By adopting the above structure, the side of the two-layered channel protective layer on which the source electrode and the drain electrode are formed, that is, the channel protective layer on the upper side has the conventional adhesiveness with the electrode contact layer. The peeling of the source electrode and the drain electrode is prevented because it is more than five times better than the low stress single layer film, and moreover, in the lower channel protective layer which occupies most of the channel protective layer. Since the stress is kept low and dominates the stress of the entire channel protective layer, lowering of the dielectric strength does not substantially pose a problem.

[Brief description of drawings]

FIG. 1 is a cross-sectional side view showing a main part of a TFT in a process step for explaining the principle of the present invention.

FIG. 2 is a side sectional view showing a main part of a TFT in a process main part for explaining the principle of the present invention.

FIG. 3 is an explanatory diagram of a TFT in a process main part for explaining one embodiment of the present invention.

FIG. 4 is an explanatory diagram of a TFT in a process main part for explaining an embodiment of the present invention.

FIG. 5 is an explanatory diagram of a TFT in a process essential part for explaining an embodiment of the present invention.

FIG. 6 is an explanatory diagram of a TFT in a process essential part for explaining an embodiment of the present invention.

FIG. 7 is an explanatory diagram of a TFT at a process main part for explaining one embodiment of the present invention.

FIG. 8 is an explanatory diagram of a TFT in a process essential part for explaining one embodiment of the present invention.

FIG. 9 is an explanatory diagram of a TFT in a process essential part for explaining an embodiment of the present invention.

FIG. 10 is an explanatory diagram of a TFT in a process essential part for explaining one embodiment of the present invention.

FIG. 11: TF in the process key point for explaining a conventional example
It is explanatory drawing of T.

[Fig. 12] TF at a process key point for explaining a conventional example
It is explanatory drawing of T.

[FIG. 13] TF at a process key point for explaining a conventional example
It is explanatory drawing of T.

FIG. 14: TF in the process key point for explaining a conventional example
It is explanatory drawing of T.

FIG. 15: TF in the process key point for explaining a conventional example
It is explanatory drawing of T.

FIG. 16: TF at a process key point for explaining a conventional example
It is explanatory drawing of T.

FIG. 17: TF in the process key point for explaining the conventional example
It is explanatory drawing of T.

[Explanation of symbols]

 1: Transparent Insulating Substrate 2: Gate Electrode 2G: Gate Electrode 2B: Gate Bus Line 3: Gate Insulating Film 4: Operating Semiconductor Layer 5A: Low Stress Channel Protective Film 5B: Adhesive Enhanced Channel Protective Film 6 : Resist film 7: Electrode contact layer 8S: Source electrode 8D: Drain electrode 9: Drain bus line 10: Pixel electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomotaka Matsumoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (3)

[Claims] 1. A channel in which adhesion is enhanced at least with a gate insulating film, an operating semiconductor layer, and a low-stress channel protective film by applying a plasma chemical vapor deposition method after forming a gate electrode on a transparent insulating substrate. A step of sequentially forming a channel protective film consisting of two layers with a protective film, and then patterning the channel protective film consisting of the two layers by self-alignment with a gate electrode, and then forming an electrode contact layer and an electrode material film And a step of patterning the electrode material film, the electrode contact layer, and the operating semiconductor layer to form a source electrode and a drain electrode that hang on a part of the channel protective film, and performing element isolation. A method of manufacturing a thin film transistor, comprising: 2. A channel protective film or a gate having a low stress in the Si amount of Si / N in an atmosphere in which H ₂ is not added, wherein the channel protective film of the two-layer channel protective film having enhanced adhesion is a SiN film. The method of manufacturing a thin film transistor according to claim 1, wherein the number of the thin film transistors is larger than that of the insulating film. 3. The method of manufacturing a thin film transistor according to claim 1, wherein the low-stress channel protective film of the two-layer channel protective film is formed of SiO ₂ .