JPH05267248A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05267248A JPH05267248A JP6421592A JP6421592A JPH05267248A JP H05267248 A JPH05267248 A JP H05267248A JP 6421592 A JP6421592 A JP 6421592A JP 6421592 A JP6421592 A JP 6421592A JP H05267248 A JPH05267248 A JP H05267248A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist layer
- etching
- photoresist
- semiconductor device
- carbon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体集積回路等の半
導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a semiconductor integrated circuit.
【０００２】[0002]
【従来の技術】半導体集積回路の製造工程において、２
層のフォトレジスト層を連続して形成する場合がある。
例えばＭＯＳＦＥＴ（金属酸化膜半導体型電界効果トラ
ンジスタ）による半導体集積回路を製造する場合、ま
ず、半導体基板の表面にＳｉ3Ｎ4等による絶縁層が形成
された後、この絶縁層に対し、トランジスタの形成され
る能動領域に対応した開口部を有する第１のフォトレジ
スト層が形成され、このフォトレジスト層によって覆わ
れていない領域の絶縁層が選択的に除去される。ここ
で、絶縁膜がＳｉ3Ｎ4である場合、従来はＣＦ4、ＣＨ
Ｆ3等の炭素系のエッチングガスが使用されていた。そ
して、第１のフォトレジスト層を除去することなく、反
転防止用イオン注入を行わない領域を覆う第２のフォト
レジスト層が形成される。図３は以上の処理を終えた段
階での半導体集積回路の断面構造を示すものである。図
３において、１は半導体基板、２は絶縁層、３は絶縁層
２をパターニングするために形成された第１のフォトレ
ジスト層、４は第２のフォトレジスト層である。このよ
うに第１および第２のフォトレジスト層が塗布された状
態においてイオン注入が行われる。この結果、第１およ
び第２のフォトレジスト層のいずれにも覆われていない
領域にイオンが注入される。また、ゲート電極の形成後
にトランジスタのソースおよびドレイン領域を形成する
場合においても、ゲート電極形成に使用したフォトレジ
スト層を除去することなく、ソース、ドレイン形成のた
めのフォトレジスト層が塗布される。この場合もゲート
電極であるポリシリコン、ポリサイド等をエッチングす
るのに炭素系のエッチングガスが使用されていた。2. Description of the Related Art In the process of manufacturing a semiconductor integrated circuit, 2
The photoresist layer of layers may be formed sequentially.
For example, when manufacturing a semiconductor integrated circuit using a MOSFET (metal oxide semiconductor field effect transistor), first, an insulating layer of Si 3 N 4 or the like is formed on the surface of a semiconductor substrate, and then a transistor of the insulating layer is formed on the insulating layer. A first photoresist layer having an opening corresponding to the active region to be formed is formed, and the insulating layer in the region not covered by the photoresist layer is selectively removed. Here, when the insulating film is Si 3 N 4 , conventionally, CF 4 and CH are used.
A carbon-based etching gas such as F 3 has been used. Then, without removing the first photoresist layer, a second photoresist layer is formed to cover the region where the inversion prevention ion implantation is not performed. FIG. 3 shows a cross-sectional structure of the semiconductor integrated circuit at the stage where the above processing is completed. In FIG. 3, 1 is a semiconductor substrate, 2 is an insulating layer, 3 is a first photoresist layer formed for patterning the insulating layer 2, and 4 is a second photoresist layer. Ion implantation is performed in the state where the first and second photoresist layers are thus coated. As a result, ions are implanted in the regions not covered by the first and second photoresist layers. Also, when forming the source and drain regions of the transistor after forming the gate electrode, the photoresist layer for forming the source and drain is applied without removing the photoresist layer used for forming the gate electrode. Also in this case, a carbon-based etching gas has been used to etch polysilicon, polycide, etc., which are gate electrodes.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上述した従
来の半導体装置の製造方法を用いた場合、第１のフォト
レジスト層上に濡れ性の悪いポリマー層が形成され、第
１および第２の各フォトレジスト層間の密着性が悪化す
るという問題がある。このため、第１のフォトレジスト
層のパターンが幅の狭い間隙を有する場合は、第１のフ
ォトレジスト層表面の濡れ性が悪いために第２のフォト
レジスト層が間隙内に行き渡らず、第２のフォトレジス
ト層と基板との間に空洞が形成されたり、塗布膜厚が不
均一になる等の不具合が生じた。そして、このような空
洞や不均一な膜厚のフォトレジスト層が形成されると、
第２のフォトレジスト層を用いたパターニングが正常に
行われず、また、パターニングの際の第２のフォトレジ
スト層のマスク性が悪く、本来イオン注入すべきでない
領域までイオン注入されてしまうという問題があった。
この対策として、第１のフォトレジスト層の表面に、例
えばＮ2、Ａｒ等の不活性ガスによるプラズマ処理等を
施す改質処理工程を追加することが考えられる。しか
し、そのようにした場合、下記の問題が生じる。 余分な工程、設備が必要である。 工程の追加に伴って半導体装置に付着する異物が増加
し、製造歩留りが低下する。 第１のフォトレジスト層の形状、寸法が変化する。こ
のため、図３に符号６によって示すようなマスク性の低
下した領域、すなわち、本来フォトレジスト層によって
覆われているべきであるのにフォトレジスト層によって
覆われていない領域が形成される。この場合、第１およ
び第２のフォトレジスト層をマスクとしたイオン注入あ
るいはエッチング等の処理が行われると、マスク性の低
下した領域に対してもその処理が施されてしまう。この
発明は上述した事情に鑑みてなされたものであり、工程
数を増やすことなく、第１および第２のフォトレジスト
層を良好に形成することができ、所期の素子パターンを
正確に形成することができる半導体装置の製造方法を提
供することを目的とする。By the way, when the above-described conventional method for manufacturing a semiconductor device is used, a polymer layer having poor wettability is formed on the first photoresist layer, and each of the first and second polymer layers is formed. There is a problem that the adhesion between the photoresist layers deteriorates. Therefore, when the pattern of the first photoresist layer has a narrow gap, the second photoresist layer does not reach the gap because the wettability of the surface of the first photoresist layer is poor, There were problems such as formation of cavities between the photoresist layer and the substrate and non-uniform coating film thickness. Then, when such a cavity or a photoresist layer having a non-uniform thickness is formed,
There is a problem that patterning using the second photoresist layer is not normally performed, and the masking property of the second photoresist layer at the time of patterning is poor, so that ions are implanted even in a region that should not be originally implanted. there were.
As a countermeasure against this, it is conceivable to add a modification treatment step of performing plasma treatment or the like on the surface of the first photoresist layer with an inert gas such as N 2 or Ar. However, when doing so, the following problems occur. Extra processes and equipment are required. As the number of steps is increased, the amount of foreign matter attached to the semiconductor device increases, and the manufacturing yield decreases. The shape and dimensions of the first photoresist layer change. For this reason, a region having a reduced masking property as shown by reference numeral 6 in FIG. 3, that is, a region which should originally be covered with the photoresist layer but is not covered with the photoresist layer is formed. In this case, when a process such as ion implantation or etching using the first and second photoresist layers as a mask is performed, the process is also performed on the region where the mask property is deteriorated. The present invention has been made in view of the above-mentioned circumstances, and the first and second photoresist layers can be favorably formed without increasing the number of steps, and a desired element pattern can be accurately formed. An object of the present invention is to provide a method of manufacturing a semiconductor device that can be manufactured.
【０００４】[0004]
【課題を解決するための手段】この発明は、素子を形成
すべき基板表面に対し、第１のフォトレジスト層を塗布
する工程と、前記第１のフォトレジスト層における所定
の領域を炭素ガスを全く含まないエッチングガスあるい
は炭素化合物を主成分として含まないエッチングガスを
使用して選択除去する第１のエッチング工程と、前記第
１のフォトレジスト層および前記基板表面を覆う第２の
フォトレジスト層を塗布する工程と、前記第２のフォト
レジスト層における所定の領域を選択除去する第２のエ
ッチング工程とを具備することを特徴としている。According to the present invention, a step of applying a first photoresist layer to a surface of a substrate on which an element is to be formed, and carbon gas is applied to a predetermined region of the first photoresist layer. A first etching step of selectively removing using an etching gas that does not contain at all or an etching gas that does not contain a carbon compound as a main component; and a second photoresist layer that covers the first photoresist layer and the substrate surface. The method is characterized by comprising a coating step and a second etching step of selectively removing a predetermined region in the second photoresist layer.
【０００５】[0005]
【作用】上記構成によれば、改質処理工程を行うことな
く、第１および第２のフォトレジスト層間の濡れ性、密
着性が改善される。According to the above structure, the wettability and the adhesion between the first and second photoresist layers are improved without performing the modification process.
【０００６】[0006]
【実施例】以下、本発明による半導体装置の製造方法の
実施例について説明する。本製造方法においては、半導
体基板全面に第１のフォトレジスト層を塗布した後、主
エッチングガスとして炭素を含まないガス、例えばＳＦ
6、ＮＦ3、Ｃｌ2等によるエッチングガスを用いてドラ
イエッチングを行い、第１のフォトレジスト層のパター
ニングを行う。このように第１のフォトレジスト層のエ
ッチングに炭素を含まないエッチングガスを用いると、
レジスト表面に濡れ性を劣化させるポリマー層が形成さ
れなくなる。従って、第１および第２のフォトレジスト
層間の密着性が向上する。図１に本製造方法を適用した
半導体装置の第２のフォトレジスト層のパターニング完
了段階での断面構造を示す。このように改質処理やポリ
マー層除去処理等の工程を追加することなく、第１およ
び第２のフォトレジスト層間の密着性が改善され、半導
体装置の製造歩留りが向上する。Embodiments of the method of manufacturing a semiconductor device according to the present invention will be described below. In the present manufacturing method, after coating the first photoresist layer on the entire surface of the semiconductor substrate, a gas containing no carbon, such as SF, is used as a main etching gas.
Dry etching is performed using an etching gas of 6 , NF 3 , Cl 2 or the like to pattern the first photoresist layer. As described above, when the etching gas containing no carbon is used for etching the first photoresist layer,
A polymer layer that deteriorates wettability is not formed on the resist surface. Therefore, the adhesion between the first and second photoresist layers is improved. FIG. 1 shows a cross-sectional structure at the completion of patterning of the second photoresist layer of the semiconductor device to which the present manufacturing method is applied. As described above, the adhesion between the first and second photoresist layers is improved and the manufacturing yield of the semiconductor device is improved without adding a process such as a modification process or a polymer layer removal process.
【０００７】[0007]
【発明の効果】以上説明したように、この発明による半
導体装置の製造方法は、素子を形成すべき基板表面に対
し、第１のフォトレジスト層を塗布する工程と、前記第
１のフォトレジスト層における所定の領域を炭素ガスを
全く含まないエッチングガスあるいは炭素化合物を主成
分として含まないエッチングガスを使用して選択除去す
る第１のエッチング工程と、前記第１のフォトレジスト
層および前記基板表面を覆う第２のフォトレジスト層を
塗布する工程と、前記第２のフォトレジスト層における
所定の領域を選択除去する第２のエッチング工程とを有
するので、製造工程を増やすことなく、第１および第２
のフォトレジスト層間の密着性を改善することができ
る。従って、所期の形状の素子パターンが正確に形成さ
れ、半導体装置の製造歩留りが向上するという効果が得
られる。As described above, in the method of manufacturing a semiconductor device according to the present invention, the step of applying the first photoresist layer to the surface of the substrate on which the element is to be formed, and the first photoresist layer A first etching step of selectively removing a predetermined region of the substrate using an etching gas containing no carbon gas or an etching gas containing no carbon compound as a main component, and the first photoresist layer and the substrate surface. Since the method includes the step of applying the second photoresist layer to cover and the second etching step of selectively removing a predetermined region in the second photoresist layer, the first and second steps can be performed without increasing the number of manufacturing steps.
The adhesion between the photoresist layers can be improved. Therefore, an element pattern having a desired shape is accurately formed, and the manufacturing yield of semiconductor devices is improved.
【図１】 この発明の一実施例による製造方法を適用し
た半導体装置の断面構造を示す図である。FIG. 1 is a diagram showing a sectional structure of a semiconductor device to which a manufacturing method according to an embodiment of the present invention is applied.
【図２】 従来の製造方法を適用した半導体装置の断面
構造を示す図である。FIG. 2 is a diagram showing a cross-sectional structure of a semiconductor device to which a conventional manufacturing method is applied.
【図３】 従来の製造方法を適用した半導体装置の断面
構造を示す図である。FIG. 3 is a diagram showing a cross-sectional structure of a semiconductor device to which a conventional manufacturing method is applied.
１……半導体基板、３……第１のフォトレジスト層、４
……第２のフォトレジスト層。1 ... Semiconductor substrate, 3 ... First photoresist layer, 4
...... Second photoresist layer.
Claims (1)
のフォトレジスト層を塗布する工程と、 前記第１のフォトレジスト層における所定の領域を炭素
ガスを全く含まないエッチングガスあるいは炭素化合物
を主成分として含まないエッチングガスを使用して選択
除去する第１のエッチング工程と、 前記第１のフォトレジスト層および前記基板表面を覆う
第２のフォトレジスト層を塗布する工程と、 前記第２のフォトレジスト層における所定の領域を選択
除去する第２のエッチング工程とを具備することを特徴
とする半導体装置の製造方法。1. A first surface of a substrate on which an element is to be formed.
And a step of selectively removing a predetermined region of the first photoresist layer by using an etching gas containing no carbon gas or an etching gas containing no carbon compound as a main component. Etching step, a step of applying a second photoresist layer covering the first photoresist layer and the surface of the substrate, and a second etching step of selectively removing a predetermined region in the second photoresist layer. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4064215A JP2913987B2 (en) | 1992-03-19 | 1992-03-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4064215A JP2913987B2 (en) | 1992-03-19 | 1992-03-19 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05267248A true JPH05267248A (en) | 1993-10-15 |
| JP2913987B2 JP2913987B2 (en) | 1999-06-28 |
Family
ID=13251648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4064215A Expired - Lifetime JP2913987B2 (en) | 1992-03-19 | 1992-03-19 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2913987B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59107516A (en) * | 1982-12-13 | 1984-06-21 | Nec Corp | Manufacture of semiconductor device |
| JPH02214153A (en) * | 1989-02-14 | 1990-08-27 | Sumitomo Metal Ind Ltd | Manufacture of mos integrated circuit |
-
1992
- 1992-03-19 JP JP4064215A patent/JP2913987B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59107516A (en) * | 1982-12-13 | 1984-06-21 | Nec Corp | Manufacture of semiconductor device |
| JPH02214153A (en) * | 1989-02-14 | 1990-08-27 | Sumitomo Metal Ind Ltd | Manufacture of mos integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2913987B2 (en) | 1999-06-28 |
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