JPH05266693A - Inspecting system for memory device - Google Patents

Abstract

PURPOSE:To enable inspection of a trouble of an address line together with a fault of a bit and thereby to improve the reliability of the inspection and also to minimize the number of times of the inspection and thereby to shorten the time for the inspection, by a method wherein data sequences being in the number most approximate to the number of constructions of data units and being prime numbers each other are used for the data for inspection of bits. CONSTITUTION:A microprocessor 1 writes/sequentially data patterns for inspection of bits stored in a register 4 in all memory areas of RAM 3 specified sequentially by an address pointer 2 and reads them out for detecting the existence or nonexistence of a bit fault. Herein, 2n-1 kinds of data patterns are stored in sequential arrangement in the register 4. Accordingly, the same data pattern appears only when the data patterns in the (number of the kinds of data patterns +1)=2<n> are arranged, and thus abnormality of an address line can be inspected irrespective of the number of bit lines thereof. According to this constitution, the abnormality of a bit and the address line can be detected in the minimal number of times of inspection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM (Electrica) mounted on a small electronic device such as an IC card.
ly Erasable Programmable
The present invention relates to a memory device inspection system for detecting an abnormality in a ROM) or a RAM.

[0002]

2. Description of the Related Art As a method of inspecting a memory device such as an EEPROM or a RAM, the following bit read / write inspection method has been conventionally performed. This bit read / write inspection method first writes a data pattern consisting of a specific bit data string in all memory areas of the memory device, then reads the data written in all memory areas and checks that the pattern is written. To do. next,
The same test is performed to read and write the bit data string of the data pattern, which is obtained by inverting the bits of the bit data string of the data pattern, in the memory device, and the normality / abnormality caused by the bit defect of the memory device is checked by this.

Further, as another inspection method, for example, an 8-bit memory device will be described as an example. The number of data components of the inspection data string is sequentially written in the memory area at a cycle of 0 to 255, and then written. There is a method of sequentially reading data and inspecting the memory device for normality / abnormality.

[0004]

However, all of the above inspection methods have a drawback that the inspection becomes impossible when the address line is short-circuited or disconnected. That is, in the current memory device, access to the memory device is performed through several address lines, and if one or more of these address lines are disconnected, the disconnection occurs. Since the two pieces of data written via the portion of the address line which has generated the same are the same, it is impossible to detect a bit defect (error) by the inspection method using the bit data string or the data of 256 cycles as described above. Because.

The present invention solves the above-mentioned drawbacks of the prior art. In addition to the bit defect inspection, the address line disconnection and short circuit can be inspected, and the reliability of the inspection can be remarkably improved. The purpose is to provide an inspection system.

Another object of the present invention is to perform read / write inspection of all bits in a memory device with a minimum number of times.
An object of the present invention is to provide a memory device inspection system capable of shortening the inspection time.

[0007]

According to another aspect of the present invention, there is provided an inspection system for a memory device, wherein data used for bit inspection of a memory device for storing data is a disjoint number of data that is closest to the number of constituent data units of the data. Storage means for storing and holding as a column, writing the data sequence from the first address to the final address of the entire memory area of the memory device, and then reading the written data sequence to determine normality / abnormality of the memory device And a determination means for performing the above-mentioned purpose, whereby the above object is achieved.

Preferably, the relatively prime number is the data configuration number-1.

[0009]

The operation of the system configuration will be described below by taking an 8-bit memory device as an example of the memory device.

Here, 8 bits means that a total of 256 recordings of 0 to 255 can be performed. Therefore, according to such a memory device, if "00H" is read and written as the same data, for example, even if a disconnection or a short circuit occurs in the adjacent address lines, the two data become the same, and the inspection OK Is falsely detected.

Assuming that a data sequence consisting of a sequence of 0 to 255, which is incremented by 1, is read from and written to the memory device, if adjacent address lines are short-circuited, short-circuiting between 256-bit multiples causes an error. Nevertheless, it will be erroneously detected as inspection O / K.

On the other hand, instead of a data sequence consisting of a sequence of 0 to 255, which is sequentially increased by 1, the number of data sequences that are coprime closest to the number of constituent data units, that is, data that is a power of two. A data string of "the number of data constituents (= 256) -1", which is the nearest disjoint number of data strings obtained by subtracting 1 from the number of constituents,
That is, in the case of 8 bits, if a data string of 255 cycles of 0 to 254 is used, a short circuit between multiples of 256 bytes can be detected as a short circuit. Therefore, by reading and writing such a data string in order from the first address to the last address of the entire memory area of the memory device, it is possible to inspect for an abnormality in the electrical wiring such as disconnection or short circuit.

It should be noted that, since the number of data components is -1, 2 ¹⁶ -1 = 65536-1 = for a 16-bit memory device.
A data string of 65535 is used.

The above reason will be explained generally and in more detail. Now, ^assuming that the data string, that is, the type of data pattern is 2 ⁿ -1 (n ≧ 2), 2 ⁿ −1 and 2 ^m (m ≧ 0).
The integer) is mathematically prime to each other. This means that if 2 ⁿ -1 kinds of data patterns are arranged in order, the pattern arrangement becomes 2 ⁿ -1 periods every 2 ^{m, which} is the same as every other pattern. In other words, it means that the same data pattern appears only when the data patterns of the number of data pattern types + 1 = 2 ⁿ are arranged. For the above-mentioned reason, the address line can be set to any n regardless of the total number of bits of the address line which constitutes the actual memory device.
When -1 line is extracted, the same data pattern is not written in the 2 ⁿ -1 memory areas configured by this, so when n-1 or less address lines are short-circuited or disconnected. Will be able to inspect the anomaly.

In addition, the above-mentioned "number of data components-
If a data string of "1" is used as pattern data, and a data string of a pattern obtained by bit-reversing this pattern is read and written in all memory areas of the memory device, "0" and "1" check of all bits, that is, You can check for bit defects. If any of the data lines is abnormal, it can be detected.

[0016]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 shows a system configuration of an inspection system for a memory device according to the present invention. The microprocessor 1 sequentially writes the data pattern for bit inspection stored in the register 4 in the entire memory area of the RAM 3 sequentially designated by the address pointer 2 via the data bus 5, and subsequently reads the written data pattern. Then, the presence or absence of a bit defect is detected.

Here, as described in the above section of operation, the register 4 stores 2 ⁿ -1 data patterns, and this data pattern and the bit-inverted data pattern are written in the RAM 3. Then, if the data is subsequently read out, it is possible to inspect for the presence or absence of a bit defect as well as the presence or absence of an abnormality in the electrical wiring such as a short circuit or a disconnection, for the reasons described above.

The bit-inverted data pattern can be generated by bit-inverting the register 4.

Data pattern writing and inspection processing to the RAM 3 will be described below with reference to FIGS. 2 and 3. Here, the RAM 3 of this embodiment is an 8-bit RAM, and the data pattern is composed of 255 kinds of data strings from 0 to 254, and 0 is an initial value,
Let 254 be the upper limit.

In the writing process shown in FIG. 2, the microprocessor 1 first sets the address B of the address pointer 2 to the start address in step S1. continue,
In step S2, the data number (number indicating the order of writing) A of the data pattern stored in the register 4 is set to the initial value.

Then, in step S3, the data A is written in the address (B) of the RAM 3 designated by the address pointer 2. Then, in step S4, the address B is changed to B
The data number A is incremented to A + 1 in step S5.

Next, in step S6, it is determined whether or not the data number A exceeds the upper limit of the data pattern, that is, whether or not the designation of the data number of the data pattern is completed,
If it is confirmed that it has not been completed, the process proceeds to step S8, where it is determined whether or not the address B has exceeded the end address. If it is confirmed that it has been exceeded, this write processing is terminated.

On the other hand, if it is confirmed in step S6 that the data number exceeds the upper limit of the data pattern, then in step S7 the data number A is set to the initial value of the data pattern, and the process of step S8 is repeated. ..

Next, the data inspection process will be described with reference to FIG. The microprocessor 1 firstly performs step S11.
Then, the address B of the address pointer 2 is set to the start address. Then, in step S12, the data number A of the data pattern is set to the initial value.

Then, in step S13, the data written in the address (B) of the RAM 3 is read, the read data is compared with the data of the data number A, and it is checked whether or not the two data match. If you confirm that they do not match, an error has occurred. In this case, RA
It is determined that an abnormality has occurred in M3, and this inspection processing ends abnormally and ends.

On the other hand, if it is confirmed in step S13 that both data match, the process proceeds to step S14,
Here, the address B is incremented to B + 1, and subsequently the data number A is incremented to A + 1 in step S15.

Then, in step S16, it is determined whether the data number A exceeds the upper limit of the data pattern, that is, whether the data number A of the data pattern read from the register 4 for comparing the two data exceeds the upper limit. .. If it is confirmed that the number is not exceeded, step S18
Then, it is determined whether or not the address B of the data read target exceeds the end address, and when it is confirmed that the end address has been exceeded, the inspection process ends normally.

On the other hand, if it is confirmed in step S16 that the data number exceeds the upper limit of the data pattern, then in step S17 the data number A is set to the initial value of the data pattern, and the process of step S18 is repeated. ..

[0030]

As described above, the inspection system for a memory device according to the present invention uses, as data to be used for bit inspection of a memory device for storing data, a disjoint number of data strings closest to the number of constituents of the data unit of the data, That is, since the data string of "the number of data components-1" is used, it is of course possible to inspect for a bit defect, and it is also possible to perform a short circuit between multiples of all bytes which has been erroneously detected in the past, that is, a short circuit or a disconnection of an address line. It is possible to inspect whether the electrical wiring is normal or abnormal.

Further, since the read / write inspection of all bits can be performed with the minimum number of times, there is an advantage that the inspection efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of an inspection system for a memory device according to the present invention.

FIG. 2 is a flowchart showing an 8-bit RAM data writing process.

FIG. 3 is a flowchart showing an 8-bit RAM data inspection process.

[Explanation of symbols]

 1 Microprocessor 2 Address pointer 3 RAM 4 Register

Claims (2)

[Claims] 1. Storage means for storing and holding data used for bit inspection of a memory device for storing data as a data sequence of a disjoint number closest to the constituent number of the data unit of the data, and the data sequence. An inspection system for a memory device, comprising: writing means from the first address to the last address of the entire memory area of the memory device; and subsequently reading the written data string to determine whether the memory device is normal or abnormal. 2. The data composition number minus 1
The inspection system for a memory device according to claim 1.