JPH05265912A - Command code issuing method - Google Patents

Abstract

PURPOSE:To give a flexibility to the issuing method of a command code from a host device to a peripheral equipment, to save the control load on the host device, and to efficiently control the peripheral equipment. CONSTITUTION:An address is issued from the host device, and held in an address register 13, and an operation start code is issued, and a sequence control circuit 17 is started. Then, an operation code is read from an instruction code memory 12 based on the address, and inputted to instruction code and decode parts 14 and 15, and the peripheral equipment is operated based on the decode result. And also, when the operation code issued from the host device is inputted to the instruction code and decode parts 14 and 15, and the sequence control circuit 17 is started by the operation start code, the peripheral equipment is operated based on the decode result of the operation code issued from the hose device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction code issuing method in a system including a host device and peripheral devices.

In a system including a host device and a peripheral device, control of the peripheral device is managed by the host device. In recent years, the high functionality and high integration of systems have been achieved by the high functionality and high integration of the semiconductor devices used in these systems, which has made the control of peripheral devices complicated, and at the same time, The control load on the peripheral device of the host device also increases. Furthermore, as the type and quantity of peripheral devices increase and the scale of the system increases,
The time that the host device spends controlling each peripheral device is decreasing.

Therefore, when the host device controls each peripheral device, it is required to reduce the control load on the host device and to efficiently control each peripheral device.

[0004]

2. Description of the Related Art As a conventional system composed of a host device and peripheral devices, there are systems shown in FIGS.

The system 30 shown in FIG.
1 and a peripheral device 32, and the peripheral device 32 includes a register / decoder circuit 33. When the host device 31 wants to operate the peripheral device 32, it issues an instruction code directly to the peripheral device 32. In the peripheral device 32, the instruction code from the host device 31 corresponds to the register / decoder circuit 33.
And the predetermined processing is executed based on the decoding result.

The system 40 shown in FIG.
1 and a peripheral device 42, and the peripheral device 42 includes a sequencer 43, a memory 44, a register / decoder circuit 45, and the like. The sequencer 43 is an instruction code memory 44.
And a series of instruction codes for controlling the peripheral device 42 are stored in advance in the memory 44. When the host device 41 wants to operate the peripheral device 42, it issues to the sequencer 43 the head address data in which the instruction code to be operated is stored and a start-up instruction for starting the operation of the sequencer 43.
In the peripheral device 42, the sequencer 4
3 is activated, and the sequencer 43 sequentially reads out the instruction code after a predetermined address from the memory 44. The read instruction code is decoded by the register / decoder circuit 45, and predetermined processing is executed based on the decoding result.

[0007]

However, in the instruction code issuing method shown in FIG. 8, the host device 31 needs to issue all the instruction codes for operating the peripheral device 32, which imposes a burden on the host device 31. There is a problem that it becomes heavier.

Also, in the instruction code issuing method shown in FIG.
If a series of instruction codes are set in the memory 44 and the host device 41 activates the sequencer 43, a plurality of instruction codes can be executed at once. However, when the host device 41 controls the peripheral device 42 to operate with one instruction code, the instruction code is issued to the peripheral device 42 at least twice with the address data and the activation instruction to activate the sequencer 43. However, there is a problem that the more functions that operate with one instruction code, the lower the efficiency.

The present invention has been made in order to solve the above-mentioned problems, and the method of issuing an instruction code from a host device to a peripheral device can be made flexible to reduce the control load on the host device. The purpose is to be able to control peripheral devices efficiently.

[0010]

In order to achieve the above object, a first invention is an instruction code memory in which a series of instruction codes is stored in advance, and an address register for holding the next address for accessing the instruction code memory. And an instruction code decoding unit that decodes the input operation code, and when the operation start code is activated and the address is held in the address register, the operation code is read from the instruction code memory based on the address and the operation code is read. In a system including a peripheral device configured to include a sequence control circuit that updates the address of the address register while inputting to the decoding unit, and a system that includes a host device that issues an instruction code to the peripheral device, the address from the host device Is issued and held in the address register, then the operation start code Is issued to activate the sequence control circuit, or the host device issues an instruction code consisting of an operation code and an operation start code to input the operation code to the instruction code decoding unit, and to the sequence control circuit. Enabled to start by inputting the operation start code.

A second invention is the above system,
After the address is issued from the host device and held in the address register, an instruction code consisting of an operation code and an operation start code is issued and the operation code is input to the instruction code decoding unit, and the operation start code is sent to the sequence control circuit. I input it and started it.

[0012]

According to the first aspect of the present invention, when the operation start code is issued after the address is issued, the instructions after the address of the address register are sequentially read from the instruction code memory, and each read instruction code is read. The instruction is executed on the basis of the result of decoding. When issuing an instruction code including an operation code and an operation start code, the instruction is executed based on the decoding result of the issued operation code. Therefore, in the case of controlling to operate with a plurality of instruction codes, a plurality of instruction codes are executed by one activation by issuing an address and an operation start code, and when controlling to operate with one instruction code. Is executed by issuing an instruction code consisting of an operation code and an operation start code once. Therefore, it becomes possible to flexibly deal with issuing the instruction code, the control load on the host device is reduced, and the peripheral devices are efficiently controlled.

According to the second aspect of the invention, when the instruction code including the operation code and the operation start code is issued after the address is issued, the instruction is executed based on the decoding result of the issued operation code. It Thereafter, the instructions following the address of the address register are sequentially read from the instruction code memory, and the instructions are executed based on the decoding result of each read instruction code. Therefore, in the case of performing control to operate with a plurality of instruction codes subsequent to control to operate with one instruction code, it is sufficient to issue an address and issue an instruction code including an operation code and an operation start code. It will be possible to respond more flexibly in issuing.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. FIG. 2 shows a system configuration of an embodiment, in which the host device 1 includes a printer 2 as a peripheral device.
Also, the hard disk device 3 and the like are connected. The host device 1 outputs a block selection signal BA, a data signal DI such as an address or an instruction code, and a write enable WE to the printer 2, the hard disk device 3 and the like,
It is designed to execute a predetermined operation.

FIG. 1 shows a semiconductor device 10 for control built in the printer 2. The hard disk device 3
A peripheral semiconductor device such as the above has a control semiconductor device similar to the semiconductor device 10.

The semiconductor device 10 includes an address decoder 11,
An instruction code memory 12, an address register 13, an instruction code register 14 and an instruction code decoder 15 which form an instruction code decoding unit, a start / stop register 16, a sequence control circuit 17 and the like are provided.

The address decoder 11 is the host device 1
From the block select signal BA and outputs the address signal ad1 to select the address register 13, or outputs the address signal ad2 to select the instruction code register 14 and the start / stop register 16. There is.

The instruction code memory 12 stores in advance a series of instruction codes for operating the printer 2. FIG. 3 shows an example of storage of the instruction code memory 12, and the instruction code is stored in the instruction code memory 12 by uniquely assigning an address to each storage area 12a consisting of 1 byte and designating the address. , Write. For example, the instruction code A0H (H is a hexadecimal number) for executing the instruction A at the address N, the address (N +
1) Instruction code B0H for executing instruction B at address, instruction code C for executing instruction C at address (N + 2)
0H is stored as data.

Further, as shown in FIG. 4, each instruction code 20 has a 1-byte structure, the upper 4 bits are an operation code 21 defining an actual instruction, and the lower 4 bits activate the sequence control circuit 17. It is the sequence control code 22 as the operation start code. The operation code 21 of the instruction code 20 or the sequence control code 22
Code 0 (H) in is a code with no meaning.

The address register 13 holds an address for accessing the instruction code memory 12 next time, and when the write enable signal WE is input in a state selected by the address signal ad1,
The data signal DI of the address from the host device 1 is set via the data bus 18, and the instruction code memory 1
The address signal AD is output to 2. Further, the address register 13 has an update signal SA from the sequence control circuit 17.
The address is updated based on.

When the write enable signal WE is input while the instruction code register 14 is selected by the address signal ad2, the operation code of the instruction code data signal DI issued from the host device 1 is selected. Latch via data bus 18. Further, the instruction code register 14 latches the instruction code DR read from the instruction code memory 12 based on the latch signal LS from the sequence control circuit 17. The instruction code decoder 15 decodes the operation code latched in the instruction code register 14 and outputs it to the sequence control circuit 17.

When the write enable signal WE is input while the start / stop register 16 is selected by the address signal ad2, among the data signals DI of the instruction code issued from the host device 1,
The sequence control code 22 is latched via the data bus 18, the sequence control code 22 is decoded, and the start control signal SC or the stop control signal ST is output to the sequence control circuit 17.

The sequence control circuit 17 is activated on the basis of the activation control signal SC from the start / stop register 16, performs sequence management for each instruction based on the decoding result of the instruction code decoder 15, and outputs the address from the instruction code memory 12. The instruction code of the address designated by the register 13 is read and input to the instruction code register 14, and the update signal SA is output to update the address held in the address register 13.

Next, an example of control timing of the semiconductor device 10 by the host device 1 will be shown. FIG. 5 shows an example in which the instruction code stored in the instruction code memory 12 is activated by the sequence control circuit 17 and executed.

First, the address decoder 11 outputs the address ad1 to select the address register 13.
Then, the start address of the instruction code memory 12 storing the instruction code to be executed via the data bus 18 is transferred to the address register 13 as the data signal DI, and the write enable signal WE is output to output the address register 13 to the address register 13. Set this start address to. For example, the address N shown in FIG. 3 is set as the start address. The address signal AD of this head address is output from the address register 13, the instruction code A0 (H) at the address N of the instruction code memory 12 is read out, and is output to the instruction code register 14 as the instruction code DR.

Next, the address decoder 11 outputs the address ad2 to select the instruction code register 14 and the start / stop register 16. Then, the instruction code including the operation code 0 (H) and the sequence control code β (H) is transmitted via the data bus 18 to the data signal DI.
, The write enable signal WE is output, and the operation code 0 (H) is output to the instruction code register 14.
The sequence control code β (H) is set in the start / stop register 16. The sequence control code β
It is assumed that (H) has meaning to output the update signal SA.

The start / stop register 16 outputs a start control signal SC for starting the sequence control circuit 17 based on the sequence control code β (H). The sequence control circuit 17 is activated based on the activation control signal SC to output the latch signal LS to the instruction code register 14 and the update signal SA to output the address value held in the address register 13 to (N + 1). Increment to.

Based on the latch signal LS from the sequence control circuit 17, A (H) of the instruction code A0 (H) read from the instruction code memory 12 is latched in the instruction code register 14. The instruction code A (H) is decoded by the instruction code decoder 15, and the decode signal DEC provides necessary information to the sequence control circuit 17 and also the necessary information to the semiconductor device 10.

The end of the instruction A is managed by the sequence control circuit 17, and when the instruction A ends and the necessary control ends, the address (N + 1) address of the instruction code memory 12 is determined based on the address (N + 1) of the address register 13. The instruction code B0 (H) is read out. Then, B (H) of the instruction code B0 (H) is latched in the instruction code register 14 by the latch signal LS from the sequence control circuit 17, and the execution of the instruction B is started.
Hereinafter, the instructions C ... Are sequentially executed in the same manner.

FIG. 6 shows an example in which a host device directly issues an instruction code to execute an instruction. Address decoder 1
The address ad2 is output from 1 to select the instruction code register 14 and the start / stop register 16.
Then, the instruction code including the operation code A (H) and the sequence control code γ (H) is transferred as the data signal DI via the data bus 18, and the write enable signal WE is output to operate in the instruction code register 14. The code A (H) and the sequence control code γ (H) are set in the start / stop register 16. The sequence control code γ (H) has a meaning not to output the update signal SA.

The start / stop register 16 outputs a start control signal SC for starting the sequence control circuit 17 based on the sequence control code γ (H). The sequence control circuit 17 is activated based on this activation control signal SC. On the other hand, the decode signal DEC of the instruction code A (H) decoded by the instruction code decoder 15 supplies necessary information to the sequence control circuit 17 and also supplies necessary information to the semiconductor device 10.

The end of the instruction A is managed by the sequence control circuit 17, and the operation of the semiconductor device 10 is stopped when the instruction A is finished and necessary control is finished. FIG. 7 shows an example in which the host device 1 directly issues an instruction code to execute an instruction and then continuously executes the instruction code in the instruction code memory 12. In this example, the instructions Z, A, B, C ... Are sequentially executed.

First, the address decoder 11 outputs the address ad1 to select the address register 13.
Then, the start address of the instruction code memory 12 storing the instruction code to be executed via the data bus 18 is transferred to the address register 13 as the data signal DI, and the write enable signal WE is output to output the address register 13 to the address register 13. Set this start address to. For example, the address N shown in FIG. 3 is set as the start address. The address signal AD of the leading address is output from the address register 13.

Next, the address decoder 11 outputs the address ad2 to select the instruction code register 14 and the start / stop register 16. Then, the instruction code including the operation code Z (H) and the sequence control code β (H) is transmitted via the data bus 18 to the data signal DI.
As the operation code Z (H) to the instruction code register 14 by outputting the write enable signal WE.
The sequence control code β (H) is set in the start / stop register 16. The sequence control code β
It is assumed that (H) has meaning to output the update signal SA.

The start / stop register 16 outputs a start control signal SC for starting the sequence control circuit 17 based on the sequence control code β (H). The sequence control circuit 17 is activated based on this activation control signal SC. On the other hand, the decode signal DEC of the instruction code Z (H) decoded by the instruction code decoder 15 supplies necessary information to the sequence control circuit 17 and also supplies necessary information to the semiconductor device 10.

The end of the instruction Z is managed by the sequence control circuit 17, and when the instruction Z ends and the necessary control ends, the instruction code A0 at the address N of the instruction code memory 12 is based on the address N of the address register 13.
(H) is read. Then, the sequence control circuit 17 outputs the latch signal LS to the instruction code register 14 and outputs the update signal SA to increment the address value held in the address register 13 to (N + 1).

Therefore, in the instruction code register 14, the instruction code A0 read from the instruction code memory 12 based on the latch signal LS from the sequence control circuit 17.
A (H) of (H) is latched, and the execution of instruction A starts. Hereinafter, the instructions B, C ... Are sequentially executed in the same manner.

As described above, in the present embodiment, when controlling to operate with a plurality of instruction codes, a plurality of instruction codes can be executed at once by issuing an address and an operation start code. In the case of performing control to operate by one operation, it can be executed by issuing the instruction code including the operation code and the operation start code once. Therefore, it becomes possible to flexibly deal with issuing the instruction code, the control load on the host device 1 can be reduced, and the peripheral devices such as the printer 2 can be efficiently controlled.

Further, in this embodiment, since the instruction code consisting of the operation code and the operation start code is issued after the address is issued, the control operation with one instruction code is followed by a plurality of instruction codes. When performing the operation control, it is sufficient to issue an address and an instruction code including an operation code and an operation start code, which makes it possible to more flexibly deal with issuing the instruction code. The control load can be further reduced, and peripheral devices such as the printer 2 can be controlled more efficiently.

[0040]

As described in detail above, according to the present invention,
By giving flexibility to the method of issuing the instruction code from the host device to the peripheral device, the control load on the host device can be reduced, and the peripheral device can be efficiently controlled.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device of an embodiment.

FIG. 2 is a system configuration diagram of an embodiment.

FIG. 3 is a diagram showing an instruction code memory.

FIG. 4 is a diagram showing a format of an instruction code.

FIG. 5 is a timing chart showing the operation of the embodiment.

FIG. 6 is a timing chart showing the operation of the embodiment.

FIG. 7 is a timing chart showing the operation of the embodiment.

FIG. 8 is a diagram showing a conventional instruction code issuing method.

FIG. 9 is a diagram showing a conventional instruction code issuing method.

[Explanation of symbols]

1 Host Device 2 Printer as Peripheral Device 3 Hard Disk Device as Peripheral Device 10 Semiconductor Device (for Control) 11 Address Decoder 12 Command Code Memory 13 Address Register 14 Command Code Register 15 Comprising Command Code Decoding Unit 15 Command Code Decoding Unit Constituent instruction code decoder 16 Start / stop register 17 Sequence control circuit

Claims (2)

[Claims] 1. An instruction code memory (12) storing a series of instruction codes in advance, an address register (13) holding a next address for accessing the instruction code memory (12), and an input operation code. And an instruction code decoding unit (14, 15) for decoding the
When the address is held in 3), the operation code is read from the instruction code memory (12) based on the address and input to the instruction code decoding unit (14, 15), and the address of the address register (13) is set. In a system including a peripheral device configured to include a sequence control circuit (17) for updating and a host device that issues an instruction code to the peripheral device, an address is issued from the host device and the address register (13 ), The sequence control circuit (17) is activated by issuing an instruction code including an operation start code, or the host apparatus issues an instruction code including an operation code and an operation start code. The operation code is input to the decoding section (14, 15), and the sequence control circuit (1 The instruction code issuing method is characterized in that the operation start code is input to 7) so that the operation is started. 2. The system according to claim 1, wherein an address is issued from a host device and held in the address register (13), and then an instruction code including an operation code and an operation start code is issued to issue an instruction code. While inputting the operation code into the decoding section (14, 15),
An instruction code issuing method, characterized in that an operation start code is input to a sequence control circuit (17) to activate the operation.