JPH05265872A - Access control circuit - Google Patents

Abstract

PURPOSE:To provide a circuit for reducing the circuit scale of a large capacity semiconductor memory device concerning the circuit to control access to storage devices respectively composed of semiconductor memories. CONSTITUTION:This circuit is provided with an access object selecting means 100 to select any one of storage circuits 2 as the object of data access, a data transfer control means 102 to control the transfer of access data, a hard error detecting means 104 to detect the hard error of the accessed storage circuit 2, an alternative memory 8 to be accessed in place of the memory part of the storage circuit 2 for which the hard error is detected, a stored data saving means 106 to transfer the data in the storage circuit 2 detecting the hard error and the alternative memory 8 to an spare storage circuit 3, a saved data recovering means 108, and an access object switching means 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access control circuit for controlling access to a memory circuit each composed of a semiconductor memory.

An access control circuit is built in a semiconductor memory device, and access to each memory circuit (built in the device and made up of a semiconductor memory) is controlled by the access control circuit. Here, when the capacity of the semiconductor memory device is increased, the number of elements of the semiconductor memory forming each memory circuit becomes enormous, so that the frequency of occurrence of memory abnormality statistically increases. When the large-capacity device is incorporated in a computer system such as a center, a memory abnormality that occurs in a storage circuit often affects the device operation and the entire system, and it is necessary to prevent this reliably.

[0003]

2. Description of the Related Art In each memory circuit of a semiconductor memory device, an alternate memory that is accessed instead of a memory portion in which a memory abnormality (hard error) has occurred, and an upper side access target is a normal memory portion and an alternate memory. A switching circuit for switching is provided.

In the access control circuit, a circuit portion for detecting an error occurrence in the memory circuit from the access data, a circuit portion for rewriting the data when the occurrence of a soft error is confirmed, and a hard error. A circuit portion is provided for instructing the switching circuit of the corresponding memory circuit to switch to the alternate memory when the occurrence of is confirmed (when the soft error is not repaired).

Therefore, when a memory error of a hard error occurs in any of the storage circuits, the abnormal memory portion is replaced by the alternate memory, and therefore the semiconductor memory device operates normally as it is, despite the occurrence of the memory error. To be done.

[0006]

It has been confirmed that memory abnormalities occur sporadically and do not occur frequently at the same time. Therefore, an alternate memory having a small storage capacity is used.

However, as the capacity of the semiconductor memory device is further increased, and the number of memory circuits is also increasing accordingly, the circuit scale of the alternate memory and the switching circuit provided in each memory circuit cannot be ignored. As a result, the semiconductor memory device becomes larger.

The present invention has been made in view of the above conventional circumstances, and an object of the present invention is to make it possible to reduce the circuit scale of a semiconductor memory device having a large capacity and to make it more compact. It is to provide a control circuit.

[0009]

In order to achieve the above object, an access control circuit according to the present invention is constructed as shown in FIG. 1, and the access control circuit shown in the figure is constructed by a semiconductor memory. Access target selection means 100 for selecting one of the storage circuits 2 as a target of data access
A data transfer control means 102 for controlling transfer of access data performed between a data access target and an upper side, and a hard error detection means 10 for detecting a hard error of the accessed storage circuit 2 from the access data.
4, a replacement memory 8 that is accessed instead of the memory portion of the storage circuit 2 in which a hard error has been detected, and a memory that transfers the data in the storage circuit 2 and the replacement memory 8 in which a hard error has been detected to the spare storage circuit 3. Data saving means 106,
Saved data restoring means 108 for transferring the data of the spare memory circuit 3 to the normal memory circuit 2 that has been exchanged with the memory circuit 2 for detecting the hard error, and the memory circuit 2 for the object of data access.
And access target switching means 110 forcibly switching to either the alternation memory 8 or the spare memory circuit 3.

[0010]

In the present invention, the alternation memory 8 is used in the access control circuit.
Are provided, and the replacement memory 8 replaces the abnormal memory portion of each storage circuit 2.

When the memory abnormal memory circuit 2 is replaced with a normal one, the data stored in the memory abnormal memory circuit 2 and the alternate memory 8 is saved in the spare memory circuit 3, and this save is performed. The data is returned from the spare memory circuit 3 to the normal memory circuit 2 whose exchange has been completed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of an access control circuit according to the present invention will be described below with reference to the drawings.

FIG. 2 illustrates the configuration of the embodiment,
The access control circuit 1 is connected to a plurality of storage circuits 2 each formed of a semiconductor memory (the number of storage circuits 2 is two in the figure, but the number is actually larger), and a spare storage circuit 3 is connected. (The spare memory circuit 3 is connected only when the memory circuit 2 in which a hard error has occurred is replaced with a normal one).

The access control circuit 1 is provided with a replacement control circuit 4, a memory control circuit 5, a data control circuit 6, a check circuit 7, and a replacement memory 8, and a storage circuit 2 is a memory control circuit 5 and a data control circuit. The spare storage circuit 3 is connected to the circuit 6, and the spare storage circuit 3 is replaced with the control circuit 4, the memory control circuit 5,
It is connected to the data control circuit 6.

FIG. 3 shows the configurations of the memory control circuit 5 and the data control circuit 6. In the memory control circuit 5, the control processing section 5a, the decoder 5b, the comparison circuit 5c, the register circuit 5d, the counter circuit 5e, The multiplexer 5f is provided, and the data control circuit 6 is provided with data transfer circuits 6a and 6b.

In FIGS. 4, 5, 6, 7, 8, and 9, the operation of this embodiment is described with reference to a flow chart, in which the control processing circuit 5a and the decoder 5b are controlled by the access request signal from the upper side. When 10a and the address signal 11a are received (step 400), the comparison circuit 5c compares the content of the register 5d with the address signal 11a (step 40).
2).

/ * Normal operation * / When the output 9c of the comparison circuit 5c indicates a mismatch between the contents of the register 5d and the address signal 11a (a hard error has not occurred at the accessed address), the decoder 5b and the multiplexer 5f ( If NO in step 404), the memory selection signals 11c and 11d and the address signal 11b are transmitted to the memory circuit 2 (steps 406 and 408).

The control processing circuit 5a determines from the access request signal 10a whether the write access or the read access is performed (step 410). When the write access is performed, the data control signal 10c is transferred to the data transmission circuit 6a. , 6b in that order (step 41
2, 418), and the write control signal 10b is transmitted to the memory circuit 2 (step 422).

When the data control signal 10c is received, the data transmission circuit 6a takes in the data signal 12a (step 414) and adds redundant data to the data signal 12a to generate a write data signal 12b (step 41).
6).

When the data transmission circuit 6b receives the data control signal 10c, it stores the data signal 12b in the storage circuit 2.
When the write control signal 10b is received from the control processing circuit 5a (step 422), the memory circuit 2 stores the content of the data signal 12b (step 424).

When a read access is performed, the control processing circuit 5a controls the read access control signal 10.
b is transmitted to the memory circuit 2 (step 426), and the memory circuit 2 transmits the data signal 12b to the data transmission circuit 6b (step 428).

Further, when the control processor 5a transmits the data control signal 10c to the data transmission circuit 6b (step 4)
30), the data transmission circuit 6b receives the data signal 12b from the storage circuit 2 (step 432), and the check circuit 7 checks the data signal 12b received by the data transmission circuit 6b (step 434).

When the control processing unit 5a confirms that the signal 7a is not output from the check circuit 7 (no data abnormality has occurred) (NO in step 436), it sends the data control signal 10c to the data transmission circuit 6a ( Step 4
38), the data transmission circuit 6a transmits the read data signal 12a received from the data transmission circuit 6b to the upper side (step 440).

/ * Occurrence of soft error in memory * / When the control processing unit 5a confirms occurrence of data abnormality from the output of the check circuit 7 (YES in step 436, step 450), the decoder 5b outputs the selection signal 11c, 1
1d is output to the memory circuit 2 (step 452), and the multiplexer 5f outputs the address signal 11b (step 454).

Then, the check circuit 7 corrects the abnormal data and sends the data signal 12b to the data transmission circuit 6b (step 456), and the control processing circuit 5a sends the control signal 10b and the data control signal 10c (step). 458), the data transmission circuit 6b transmits the data signal 12b in which the abnormal data is corrected to the storage circuit 2 (step 4).
60).

When this transmission is performed, the data signal 12
b is written in the memory circuit 2 (step 462), the control processing circuit 5a controls the control signal 10c and the data control signal 10c.
Is transmitted (step 464).

Further, when the memory circuit 2 sends the data signal 12b to the data transmission circuit 12b (step 466) and the data transmission circuit 6b takes in the data signal 12b (step 468), the check circuit 7 causes the data transmission circuit 6b. Check again the data signal 12b received by (step 470).

When the check circuit 7 does not detect the occurrence of the data abnormality (NO in step 472), the abnormality at that time is repaired by the soft error in the memory. Control signal 10
c is output to the data transmission circuit 6a (step 438),
The data transmission circuit 6a transmits the read data signal 12a (restored data) received from the data transmission circuit 6b to the upper side (step 440).

/ * Occurrence of a hard error in memory * / On the other hand, when the occurrence of a data abnormality is detected again by the check circuit 7 (YES in step 472), the abnormality is caused by a hard error that cannot be repaired by rewriting. Judged as something.

When the check circuit 7 confirms that a memory hardware error has occurred, it outputs an abnormality detection signal 7a to the control processing circuit 5a.
To notify the error (step 474), the register circuit 5d takes in the address of the abnormal memory, and starts transmitting an error signal (step 476: notify the upper side of the memory error).

Then, the check circuit 7 corrects the abnormal data and sends it to the data transmission circuit 6a (step 47).
8), the control processing circuit 5a sends the data control signal 10c (step 480), and the data transmission circuit 6a sends the data signal 12a (step 490).

The register circuit 5d sends the memory selection signal 11e to the decoder 5b (step 492), and the decoder 5b sends the selection signals 11c and 11d (step 494).

Further, the control processing circuit 5a transmits the exchange processing control signal 9d to the exchange control circuit 4 (step 49).
6) Upon receipt of the exchange processing control signal 9d, the exchange control circuit 4 transmits the address control signal 9c to the counter circuit 5e and the multiplexer 5f (step 498), and the multiplexer 5f inputs the address control signal 9c when it receives the address control signal 9c. To the count signal 9g side (counter circuit 5e side) (step 500).

When the input of the multiplexer 5f is switched, the counter circuit 5e transmits a count signal to the multiplexer 5f (step 502), and the multiplexer 5f
f sends out the address signal 11b (step 504),
The control processing circuit 5a sends the control signals 10b and 10c (step 506), the memory circuit 2 sends the data signal 12b (step 508), and the data transmission circuit 6b takes in the data signal 12b from the memory circuit 2 (step 51).
0), the check circuit 7 checks the data signal 12b,
The abnormal data is corrected and the data signal 12c is transmitted to the alternation memory 8 (step 512), and the control processing section 5a transmits the control signal 10d to the alternation memory 8 (step 51).
4), the alternation memory 8 stores the data signal 12c (step 516), and the counter circuit 5e counts up (step 518).

When the counter circuit 5e reaches the count full and the operation of saving all the data read from the address portion of the abnormal memory and corrected in the alternation memory 8 is completed (YES in step 520), the control processing circuit 5
a stops outputting the exchange processing control signal 9d (step 522).

/ * After saving abnormal memory * / After that, the address signal 11a transmitted by the upper side
And the address of the abnormal memory fetched in the register circuit 5d is confirmed (YES in step 404).
S: The data of this address portion is corrected and saved in the alternate memory 8), and the comparison circuit 5c transmits the avoidance signal 9e to the control processing circuit 5a (step 530).

The multiplexer 5f also transmits the address signal 11b to the control processing circuit 5a (step 53).
2) When receiving both signals 9e and 11b, the control processing circuit 5a transmits the control signal 10d to the alternation memory 8 (step 534).

At that time, when it is confirmed that the write access is performed (step 536), the control processing circuit 5a transmits the data control signal 10c to the data transmission circuit 6a (step 538), and the data transmission circuit which has received the data control signal 10c. 6
a takes in the data signal 12a (step 540).

Further, the check circuit 7 adds redundant data to the fetched data signal 12a to add the data signal 12a.
c (step 542) and the alternation memory 8 stores the generated data signal 12c (step 544).

When a read access is performed (step 536), the alternation memory 8 is received by receiving the control signal 10d.
Sends the data signal 12c (step 546), the check circuit 7 checks and corrects the data signal 12c, sends the data signal 12a (step 548), and the control processing circuit 5a sends the control signal 10c (step 550). ), The data transmission circuit 6a transmits the read data signal 12a (read from the alternation memory 8) to the upper side (step 552).

/ * Installation of spare memory circuit * / When the error signal 13 is transmitted (step 476) and the occurrence of an abnormality is displayed on the device on the upper side, and the display is confirmed, the maintenance person confirms the spare memory circuit. 3 is attached to the semiconductor memory device and a replacement instruction signal 9a is given to the semiconductor memory device to instruct replacement of the memory circuit 2 (step 560).

The exchange instruction signal 9a is received by the exchange control circuit 4 and the control processing circuit 5a, and the exchange control circuit 4 sends out the address control signal 9c (step 562), and the counter circuit 5e is sent by the address control signal 9c. The input of the multiplexer 5f is switched to the count signal 9g side of the counter circuit 5e (step 564).

Further, the register circuit 5d transmits the address signal 11e of the abnormal memory to the decoder 5b (step 566), and the decoder 5b transmits the selection signals 11c and 11d (step 568).

Then, the counter circuit 5e sends out the count signal 9g (step 570), and the multiplexer 5f
Sends the address signal 11b (step 572), and the comparison circuit 5c compares the address signal 11e of the register circuit 5d with the count signal 9g of the counter circuit 5e (step 574).

At this time, when it is confirmed by the output 9e of the comparison circuit 5c that the address signal 11e and the count signal 9g do not match and the memory error is not generated (step 576), the control processing circuit 5a causes the control signal 10b. Is sent (step 578) and the memory error memory circuit 2
The data signal 12b is transmitted from the device (step 58).
0).

Next, the replacement control circuit 4 causes the control signal 9b.
Is transmitted to the spare storage circuit 3 (step 582), and the data signal 12b sent from the storage circuit 2 having the memory error is transmitted.
Is stored in the spare storage circuit 3 (step 584).

Further, the control processing circuit 5a transmits the data control signal 10 to the data transmission circuit 6b (step 58).
6) Then, the data transmission circuit 6b which receives this takes in the data signal 12b (step 588).

Then, when the check circuit 7 checks the data signal 12b taken in by the data transmission circuit 6b (step 590) and no data abnormality is detected (NO in step 592), the counter circuit 5e is counted up. (Steps 594, 596) and thereafter, the above operation is repeated from the transmission of the count signal 9g (Step 570).

However, if a data error is detected by the check circuit 7 during this process (YES in step 592),
The check circuit 7 sends the corrected data signal 12b (step 598), and the control processing circuit 5a sends the data control signal 10c (step 600).

When the data control signal 10c is received,
The data transmission circuit 6b sends out the data signal 12b corrected by the check circuit 7 (step 602), and the replacement control circuit 4 sends the control signal 9b to the spare storage circuit 3 (step 604), and the spare storage circuit. 3 is a data transmission circuit 6
The data signal 12b sent by the b is stored (step 6).
06).

Further, when it is confirmed from the output 9e of the comparison circuit 5c that the address signal 11e and the count signal 9g match and it is a memory error occurrence portion (step 5).
In 76), the control processing circuit 5a sends the control signal 10d to the alternation memory 8 (step 608).

When the control signal 10d is received, the alternation memory 8
Transmits the data signal 12c (step 610), the check circuit 7 checks and corrects the data signal 12c to generate the data signal 12b (step 612), and the spare storage circuit 3 stores the data signal 12b. (Steps 600, 602, 604, 606).

As described above, when the maintenance person mounts the spare memory circuit 3 on the semiconductor memory device and gives the replacement instruction signal 9a, the memory circuit 2 in which the memory error has occurred and the alternate memory 8 are generated.
Is transferred to the spare storage circuit 3.

/ * Replacement of memory circuit * / The maintenance person replaces the memory circuit 2 in which a memory error has occurred, then gives a replacement instruction signal 9a to the semiconductor memory device (step 620), and when this is received, the replacement control signal is sent. The circuit 4 outputs the address control signal 9c (step 622).

When the address signal 9c is received, the multiplexer 5f inputs the counter signal 9g of the counter circuit 5e.
(Step 624), the register circuit 5d sends out the address signal 11e of the abnormal memory (step 6).
26), the decoder 5b sends the selection signals 11c and 11d (step 628).

Then, the counter circuit 5e sends the count signal 9g (step 630), and the multiplexer 5f
Sends the address signal 11b (step 63).
2) The exchange control circuit 4 transmits the control signal 9b to the spare storage circuit 3 (step 634), and the spare storage circuit 3 sends out the data signal 12b (step 636).

Further, the control processor 5a controls the control signal 10b.
(Step 638), the replaced new storage circuit 2 receives the data signal 12 sent by the spare storage circuit 3.
b is stored (step 640).

Further, the control processing section 5a causes the data control signal 1
0c (step 642), the data transmission circuit 6b takes in the data signal 12b (step 64).
4) The check circuit 7 checks this (step 646).

At this time, if no data error is detected (NO in step 648), the counter circuit 5e.
Counts up (steps 650 and 652),
The above operation is repeated from the transmission of the count signal 9g (step 630).

However, if a data error is detected during this process (YES in step 648), the check circuit 7
Sends out the data signal 12b (modified) (step 654), and the control processing circuit 5a sends the data control signal 10b.
c is transmitted (step 656), the data transmission circuit 6b transmits the data signal 12b (step 658), and the exchange control circuit 4 transmits the control signal 9b (step 66).
0), the storage circuit 2 stores the corrected data signal (step 662).

In this way, the new storage circuit 2 replaced
When all the data is transferred from the spare storage circuit 3 to
The control processing circuit 5a outputs the reset signal 9f (step 664), and the register circuit 5d stops the transmission of the error signal 13 (step 666).

* / Summary of Embodiment * / As described above, when a memory error occurs in the memory circuit 2 of the semiconductor memory device, the error occurrence portion is replaced by the alternate memory 8 of the access control circuit 1.

When the spare memory circuit 3 is mounted in the semiconductor memory device, the memory circuit 3 in which the memory error has occurred and the data thereof are temporarily saved in the memory circuit 3.

When the memory circuit 2 in which the memory error has occurred is replaced with a new one, all the data saved in the spare memory circuit 3 is replaced with the new memory circuit 2 after replacement.
Returned to.

/ * Effect of the Embodiment * / According to the present embodiment, since the alternate memory 8 for substituting the memory error portion of the memory circuit 2 is provided in the access control circuit 1, the capacity of the semiconductor memory device can be increased. Even if the number of memory circuits 2 increases, the circuit scale for memory error substitution becomes constant, and therefore the circuit scale of the semiconductor memory device can be reduced, and therefore the device can be made smaller.

[0066]

As described above, according to the present invention, when a memory error occurs in the memory circuit, that portion is replaced by the access control circuit, so that the circuit scale of the semiconductor memory device is reduced. Can be further miniaturized.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the invention.

FIG. 2 is an explanatory diagram of a configuration of an embodiment.

FIG. 3 is a configuration explanatory diagram of a memory control circuit and a data control circuit.

FIG. 4 is a flowchart illustrating the operation of the embodiment.

FIG. 5 is a flowchart illustrating the operation of the embodiment.

FIG. 6 is a flowchart illustrating the operation of the embodiment.

FIG. 7 is a flowchart illustrating the operation of the embodiment.

FIG. 8 is a flowchart illustrating the operation of the embodiment.

FIG. 9 is a flowchart illustrating the operation of the embodiment.

[Explanation of symbols]

 1 Access Control Circuit 2 Storage Circuit 3 Spare Storage Circuit 4 Replacement Control Circuit 5 Memory Control Circuit 5a Control Processing Circuit 5b Decoder 5c Comparison Circuit 5d Register Circuit 5e Counter Circuit 5f Multiplexer 6 Data Control Circuit 6a Data Transmission Circuit 6b Data Transmission Circuit 7 Check circuit 8 Alternate memory

Claims (1)

[Claims] 1. An access target selecting means (100) for selecting one of storage circuits (2) each composed of a semiconductor memory as a target of data access, and a target of data access and an upper side. Data transfer control means for controlling transfer of access data (1
02) and a hard error detecting means (104) for detecting a hard error of the accessed storage circuit (2) from the access data.
And an alternate memory (8) that is accessed instead of the memory portion of the storage circuit (2) in which a hard error is detected, and data in the storage circuit (2) and the alternate memory (8) in which a hard error is detected are reserved. A storage data saving means (106) for transferring to the storage circuit (3) and a saving for transferring the data of the spare storage circuit (3) to a normal storage circuit (2) exchanged with the storage circuit (2) for detecting a hard error. Data recovery means (108), access target switching means (110) for forcibly switching the data access target to any of the storage circuit (2), alternate memory (8) and spare storage circuit (3). An access control circuit characterized by having.