JPH05265598A - Signal transfer system - Google Patents

Abstract

PURPOSE:To perform signal transfer from a Power-On side to a Power-Off side also from the Power-Off side to the Power-On side without generating the malfunction and destruction of a circuit in a device capable of performing the ON/OFF control of a power source at every unit. CONSTITUTION:This system is the inter-unit interface of the device separated to two units constituted of a first unit 1 and a second unit 2 and capable of performing the ON-OFF control of the power source independently by only the unit on one side, and an output gate 3, an input gate 4. and a first power source 5 are provided at the first unit 1, and an input gate 6, an output gate 7, a second power source 8, a power source control part 9, a third power source 10, and a clamping resistor 11 are provided at the second unit 2. The first power source 5 is turned off after an interface signal 12 which performs the signal transfer of the interface is fixed at a Low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface signal transmission / reception technique for a device capable of controlling ON / OFF of a power supply in units of units.
-Off side, Power-Off side to Power-
The present invention relates to a technique effectively applied to a signal transmission / reception method capable of preventing malfunction and destruction of an interface circuit in signal transmission / reception to an On side.

[0002]

2. Description of the Related Art Conventionally, it is well known that refreshing is performed by battery power supply in a device that protects memory when a power failure occurs by using a dynamic RAM. In this case,
In order to reduce the power consumption due to the refresh of the dynamic RAM at the time of power failure, the peripheral circuits other than the refresh section are not powered by the battery.
The malfunction of the circuit at the connection between the power supply unit and the non-power supply unit is prevented by using the following two methods.

For example, as a first method, Powe
The input of the r-On circuit is gated by a power failure notice signal, etc., to prevent malfunction in the transient state during power failure / power recovery.

The second method is Power-Off.
The output of the operating circuit is gated, and the power-on side input connected to this output is clamped to the high level to prevent malfunction.

As a device related to this type, there is a technique disclosed in Japanese Patent Laid-Open No. 1329521/55.

[0006]

Generally, it is well known that gate breakdown occurs when the voltage of the input / output pin of the gate becomes higher than the power supply voltage. Also, the input is Low level and H
There is a risk of malfunction at an intermediate level between the high level and, especially in the case of a CMOS gate, an overcurrent exceeding the gate design standard may flow into the gate and damage the gate. Usually, in a circuit that refreshes with battery support, a CMOS gate is used for power reduction, which is a particular problem.

On the other hand, when the apparatus is divided into a plurality of units and fed from a plurality of power sources, ON / OFF control of each power source is controlled separately or simultaneously, but the power source output voltage rises due to the difference in the load of the power source. / Due to a difference in power supply state such as a difference in fall time, a problem may occur in the connection circuit between the units and gate destruction may occur.

However, in the above-mentioned prior art, no consideration is given to this gate breakdown,
In other words, in the first method, the output level of the gate output which does not support the battery becomes indefinite at the time of Power-Off, and the input of the circuit which supports the battery connected to this output becomes the intermediate level, which may cause the gate breakdown. There is a problem that occurs.

In the second method, the power supply to the circuit not supporting the battery is turned off at the connecting portion between the circuit not supporting the battery and the circuit supporting the battery,
Since the interface signal is clamped to the high level, the power-on circuit outputs the power
The signal is transmitted to the circuit that is er-off
The r-Off circuit causes the output pin voltage> the power supply voltage and the circuit may be damaged or may be damaged. Furthermore, no consideration is given to the signal transfer from the battery supporting side to the battery non-supporting side. There is a problem.

Therefore, an object of the present invention is to provide a power control unit for controlling power ON / OFF for each unit.
An object of the present invention is to provide a signal transmission / reception system capable of exchanging signals from the r-On side to the Off side and from the Power-Off side to the On side without malfunction or destruction of the circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the signal transmission / reception system of the present invention comprises at least two or more units and a power supply for supplying electric power to these units, and this power supply is O
A signal transmission / reception system between units of a device capable of controlling N / OFF, wherein a fixing means for fixing a signal source output between the units to a Low level and a signal between the units are Ground.
A clamp resistor for clamping the level is provided.

[0014]

According to the above-mentioned signal transfer system, the power supply is turned on for each unit by providing the low level fixing means and the ground level clamp resistor.
ON / OFF control device, device with different power supply state from power supply to each unit, and further, signal transmission between units in the case of device with only one unit of power supply ON / OFF control The power can be turned off after fixing the output to the low level.

As a result, the value of the gate input on the Power-On side does not become the Low level and does not become the intermediate level, so that an overcurrent does not flow to the gate, and thus the gate can be prevented from being destroyed. ..

Similarly, the gate output on the Power-Off side is also at the Low level, and the output pin voltage> the power supply voltage is not satisfied, so that the gate breakdown can be prevented.

Further, the gate input on the Power-Off side is also at the Low level, and the condition of input pin voltage> power supply voltage is eliminated, and thereby the circuit can be prevented from being destroyed.

[0018]

Embodiment 1 FIG. 1 is a circuit diagram showing an inter-unit interface which is an embodiment of the signal transfer system of the present invention.

First, the configuration of the inter-unit interface of this embodiment will be described with reference to FIG.

The inter-unit interface of this embodiment is
For example, it is divided into two units, and one of the units is an inter-unit interface of a device capable of independently controlling ON / OFF of a power source, and is composed of a first unit 1 and a second unit 2, and an interface circuit between the units. Is realized by a CMOS type general-purpose logic LSI.

The first unit 1 is provided with an output gate 3, an input gate 4, a first power source 5, etc., while the second unit 2 is provided with an input gate 6, an output gate 7, a second power source 8, a power source control. A part (fixing means) 9, a third power supply 10, a clamp resistor 11 and the like are provided, and the interface signal 1
Signals are exchanged by 2 and 13.

The first power supply 5 supplies the power supply voltage to the output gate 3 and the input gate 4 of the first unit 1, and the second power supply 5
The power supply 8 supplies a power supply voltage to the input gate 6 and the output gate 7 of the second unit 2. Furthermore, the third
The power supply 10 is an auxiliary power supply, and at the same time when the breaker is turned on, the third power supply 10 is powered-on to supply the power supply voltage to the power supply control unit 9.

The clamp resistor 11 is a resistor that clamps the interface signal 12 to the ground level, that is, the low level. The resistance value is selected to be larger than the drive capability of the output gate 3 and the input leakage current of the input gate 6. It is desirable that the voltage generated by the flow of the voltage is equal to or less than the low level allowable value of the input gate 6 and the voltage value at which the output gate 3 is not destroyed when the power is turned off.

The power supply control section 9 includes the inhibition signal 14 of the output gate 3 of the first unit 1 and the input gate 6 of the second unit 2.
And a command by the inhibition signal 15 of the output gate 7,
For example, there are two modes, that is, the case where only the first unit 1 is Power-Off, and the case where both the first unit 1 and the second unit 2 are Power-Off, and the power supply control unit 9 receives a command from the outside. First power source 5 and second
The power supply 8 is controlled.

Next, the operation of this embodiment will be described.

For example, the case where the power supply to only the first unit 1 is stopped from the state where the power supply voltage is supplied to both the first unit 1 and the second unit 2 will be described.

First, when the power-off command of the first unit 1 is externally given to the power supply control unit 9, the power supply control unit 9 sets the inhibition signal 14 to Low and fixes the output gate 3 at Low level.

Next, the inhibition signal 15 is set to Low to close the input gate 6 of the second unit 2, and at the same time, the output gate 7 is fixed to Low level. After that, the first power source 5
To stop the power supply voltage of the first unit 1.

In this case, in the first unit 1, the output of the output gate 3 is fixed to the low level and further clamped to the low level by the clamp resistor 11, so that the first power supply 5 is turned off and after it is turned off. Since the interface signal 12 becomes Low level and the input level of the input gate 6 of the second unit 2 does not become the intermediate level, the gate destruction of the input gate 6 due to the overcurrent can be prevented and the output of the first unit 1 can be prevented. Since the output voltage of the gate 3 does not exceed the power supply voltage, the gate breakdown of the output gate 3 can be prevented.

Also in the second unit, the output of the output gate 7 is fixed to the low level, and the first power supply 5
Interface signal 13 after the OFF process and after
Becomes Low level, and the input gate 4 of the first unit 1
The input voltage of 1 does not exceed the power supply voltage, and the gate breakdown of the input gate 4 can be prevented.

Subsequently, in the case where the power supply voltage is supplied to both the first unit 1 and the second unit 2 from this state, that is, the power supply control unit 9 is externally powered down by the power of the first unit 1.
When the er-On command is given, the power supply control unit 9 turns on the first power supply 5 while fixing the inhibition signals 14 and 15 at the Low level.

After that, the low level fixing of the inhibition signals 14 and 15 is released, and the normal operation is restored. By performing the processing in this procedure, it is possible to prevent the gate breakdown of the output gate 3, the input gate 4, and the input gate 6 of the second unit 2 as in the case of the power-off of the first unit 1.

The interface signal 13 is Low.
Although the clamp resistance for clamping to the level is not connected, this is because the power supply of the output gate 7 of the second unit 2 is ON.
Since the output of the output gate 7 is fixed to the Low level by the inhibition signal 15, the clamp resistance to the Low level is unnecessary.

Therefore, according to the inter-unit interface of the present embodiment, the power supply controller 9 and the clamp resistor 11 for the interface signal are provided in the second unit 2 so that the interface signal 12 is fixed to the low level and then the first power source is supplied. Since 5 can be turned off, the input gate 6 of the second unit 2 does not reach the intermediate level,
In addition, the output voltage of the output gate 3 of the first unit 1 does not become higher than the power supply voltage.
Since the input voltage of the input gate 4 of the second unit 2 does not exceed the power supply voltage, the input gate 6 of the second unit 2
The gate breakdown of the output gate 3 and the input gate 4 of the unit 1 can be prevented.

[0035]

[Embodiment 2] FIG. 2 is a circuit diagram showing an inter-unit interface which is another embodiment of the signal transfer system of the present invention.

The inter-unit interface of this embodiment is
As in the first embodiment, the first unit 1a and the second unit 2 are included, and the first unit 1a includes the output gate 3 and
Clamp resistor 1 in addition to input gate 4 and first power supply 5
6 is added to the second unit 2, while the input gate 6, the output gate 7, the second power supply 8, the power supply control unit (fixing means) 9, the third power supply 10 and the clamp resistor 11 are added to the second unit 2. Is provided, and the difference from the first embodiment is that any of the units can independently control ON / OFF of the power supply in units of units.

That is, the output gate 7 of the second unit 2
A clamp resistor 16 is provided in the interface signal 13 between the input unit 4 and the input gate 4 of the first unit 1a, and the first unit 1a and the second unit 2 are symmetrically connected to each other. In the case of turning off, when only the second unit 2 is power-off, and when both the first unit 1a and the second unit 2 are both power-off, three types of control are possible.

Next, the operation of this embodiment will be described.

In this embodiment, since the same processing as the ON / OFF control of the power supply of only the first unit 1a as in the first embodiment is performed, the power supply of the second unit 2 is turned ON.
The case of controlling ON / OFF will be described.

First, from the state where the power supply voltage is supplied to both the first unit 1a and the second unit 2,
When the power supply to only the unit 2 is stopped, a power-off command of the second unit 2 is externally given to the power supply control unit 9, and the power supply control unit 9 sets the inhibition signal 15 to Low.
Then, the output gate 7 is fixed to the low level.

Next, the inhibition signal 14 is set to Low to close the input gate 4 of the first unit 1a, and at the same time, the output gate 3 is fixed to Low level. After that, the second power supply 8 is stopped to reduce the power supply voltage of the second unit 2.

In this case, the output of the output gate 7 of the second unit 2 is fixed at the Low level and further clamped by the clamp resistor 16 at the Low level.
Interface signal 13 after the OFF process and after
Becomes a low level, and the input level of the input gate 4 of the first unit 1a does not become an intermediate level. Therefore, the gate breakdown of the input gate 4 due to an overcurrent can be prevented, and the output gate 7 of the second unit 2 can be prevented. Since the output voltage does not become higher than the power supply voltage, the gate breakdown of the output gate 7 can be prevented.

Further, the output of the output gate 3 of the first unit 1a is fixed at the low level, and the OF of the second power supply 8 is turned off.
The interface signal 12 is Lo even after the F process and OFF.
It becomes the w level, the input voltage of the input gate 6 of the second unit 2 does not exceed the power supply voltage, and the gate breakdown of the input gate 6 can be prevented.

Subsequently, when the power supply voltage is supplied to both the first unit 1a and the second unit 2 from this state,
That is, P of the first unit 1a is externally supplied to the power control unit 9.
When the power-on command is given, the power control unit 9
The second signal with the suppression signals 14 and 15 fixed at Low level
Turn on the power supply 8.

After that, the fixing of the low level of the inhibition signals 14 and 15 is released, and the normal operation is resumed. By performing the processing in this procedure, it is possible to prevent the gate breakdown of the output gate 7, the input gate 6 and the input gate 4 of the first unit 1a as in the case of the power-off of the second unit 2.

Therefore, according to the inter-unit interface of this embodiment, the interface signal 1 is used as in the first embodiment.
Since the second power source 8 can be turned off after fixing 3 to the low level, the input gate 4 of the first unit 1a
Does not become an intermediate level, the output voltage of the output gate 7 of the second unit 2 does not exceed the power supply voltage, and the input voltage of the input gate 6 of the second unit 2 exceeds the power supply voltage. Therefore, the input gate 4 of the first unit 1a and the second unit 2
It is possible to prevent the output gate 7 and the input gate 6 from being destroyed.

In this embodiment, the input gates 4 and 6 are
The gates are suppressed by the suppression signals 14 and 15 when the power is turned off. This is for the purpose of preventing malfunction of the input gates 4 and 6 unlike the purpose of preventing the gate destruction. The malfunction of the input gate 4 of the unit 1a and the input gate 6 of the second unit 2 can be prevented.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the inter-unit interface of the above-described embodiment, the case where the signal transfer circuit between the first units 1 and 1a and the second unit 2 is realized by a CMOS type general-purpose logic LSI has been described. The present invention is not limited to the above-mentioned embodiment, and particularly when it is realized by an LSI which is not an interface dedicated circuit, and when the input / output pin voltage becomes higher than the power supply voltage of its own circuit, there is a possibility of causing gate breakdown, and further the input voltage. It is also widely applicable to the case where it is realized by a semiconductor in which an overcurrent may flow at a middle level.

Further, the suppression signals 14 and 15 are sent to the power supply control unit 9
Although the output from the first unit 1 or 1a or the second unit 2 is reset by the reset signal instead of the inhibition signals 14 and 15,
The present invention is also applicable to the case where the operation of the units 1 and 1a or the second unit 2 is stopped and fixed to the low level.

[0051]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). Fixing means for fixing the signal source output between the units to the Low level and the signal between the units are Gro.
By providing a clamp resistor that clamps to the und level, the power supply can be turned off after fixing the signal source output between the units to the low level.
The value of the gate input on the er-On side becomes Low level,
Since it does not reach the intermediate level, overcurrent does not flow in the gate, and the gate can be prevented from being destroyed.

(2). According to the above (1), Power-Off
Similarly, since the gate output on the side is also at the Low level, the output pin voltage> the power supply voltage does not hold, and thus the gate breakdown can be prevented.

(3). According to the above (1), Power-Off
Since the gate input on the side is also at the low level, the condition of input pin voltage> power supply voltage is eliminated, and this can prevent the circuit from being destroyed.

(4). According to the above (1) to (3), it is divided into two or more units and the power is turned ON / O in unit.
In the device that can control the FF, from the power ON side to the OF
A signal transfer system capable of preventing malfunction and destruction of the interface circuit in transfer of a signal from the OFF side to the ON side to the F side can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an inter-unit interface that is Embodiment 1 of a signal transfer system of the present invention.

FIG. 2 is a circuit diagram showing an inter-unit interface that is Embodiment 2 of the signal transfer system of the present invention.

[Explanation of symbols]

 1, 1a 1st unit 2 2nd unit 3 output gate 4 input gate 5 1st power supply 6 input gate 7 output gate 8 2nd power supply 9 power supply control section (fixing means) 10 3rd power supply 11 clamp resistance 12, 13 interface signal 14,15 Suppression signal 16 Clamp resistor

Claims (1)

[Claims] 1. A signal transmission / reception system between units of a device comprising at least two or more units and a power supply for supplying electric power to the units, the power supply being a unit for transmitting / receiving signals between units. Fixing means for fixing the signal source output between the units to the Low level and clamp resistors for clamping the signal between the units to the Ground level are provided, and after fixing the signal source output between the units to the Low level, the power supply A signal transmission / reception system characterized by turning off.