JP3295833B2 - Power supply redundancy system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply redundancy system, and more particularly to a power supply redundancy system used for space equipment.

[0002]

2. Description of the Related Art Space equipment is required to have a highly reliable operation in a severe space environment and to be small and light, so that a redundant configuration is often provided for each equipment or functional unit. Also have a redundant configuration.

In a redundant configuration of a power supply unit (DC / DC converter), a judgment voltage of an overvoltage detection circuit existing in each DC / DC converter is not generated from a secondary voltage supplied to a load, but is generated by a DC / DC converter. Some DC converters are configured to generate the output from the output of a rectifier circuit that is separately configured for exclusive use. In this case, only the power supply unit (DC / DC converter) has a redundant configuration, and the load unit has a single configuration.

Since each output of the DC / DC converter having the redundant configuration is commonly connected to a load, if an overvoltage is determined based on a voltage output to the load, any one of the outputs is determined. When the DC / DC converter fails and an overvoltage occurs, all the DC / DC converters detect abnormalities and stop functioning.

Therefore, a rectifier circuit is provided in each DC / DC converter separately from a voltage line to be supplied to a load, and an overvoltage is determined based on the output of the rectifier circuit. Function is stopped. This technique is disclosed in Japanese Unexamined Patent Publication No. 1-1335.
No. 70 discloses this in detail.

[0006] Further, as a redundant configuration of the power supply unit,
As shown in FIG. 9, the loads 34 to 36 and the power supply units 31 to 33
Are connected one to one, and the power supply unit 3 is connected to the loads 34 to 36.
There is a type in which 1 to 33 are simply triple redundant.

In this case, the majority of the outputs of the loads 34 to 36 are determined by a majority circuit 37 to determine the output value. The majority circuit 37 is supplied with power from the power supply unit 31.

Further, as a redundant configuration of the power supply unit, FIG.
0, the loads 44, 46 and the power supply units 41, 42 are connected one-to-one, and the diodes 43a, 43
In some cases, the power supply units 41 and 42 are connected to a load 45 and a majority circuit 47 through an OR (OR) circuit 43 using b.

[0009]

In the above-described conventional redundant configuration of the power supply unit, the overvoltage is determined only by the output of the rectifier circuit. Therefore, when an abnormality such as a voltage drop occurs in the DC / DC converter. , The abnormality cannot be detected.

Therefore, there is a possibility that the supply voltage to the load fluctuates even if a redundant configuration is adopted. That is, one D
When the output voltage of the C / DC converter decreases, there is no guarantee that the supply voltage to the load is stabilized by the output voltage of another normal DC / DC converter.

The above redundant configuration is ineffective when an abnormality occurs in the power supply line due to a cause on the load side, for example, a short circuit between the power supply and GND (ground) due to a failure of an electric component. That is, the above-described redundant configuration is a redundant configuration of only the power supply unit, and does not consider the operation abnormality caused by the load.

On the other hand, regarding the redundant system of the power supply line, (1) normal operation as a device when power supply voltage abnormally rises (overvoltage) (2) normal operation as a device when power supply voltage abnormally drops (low voltage) (3) Mitigation of voltage effect in OR circuit (response to large current load) (4) Supply of redundant power to majority circuit (5) Reduction in number of power supplies (6) Overcurrent (or voltage) due to common load There is a problem of protecting other loads against degradation, and it is desirable to solve these problems simultaneously.

However, in the case where the power supply section is simply made triple redundant with respect to the load, the normal operation as a device when the power supply voltage rises abnormally (overvoltage) in (1) and the majority circuit in (4) It is difficult to realize redundant power supply and reduction of the number of power supplies in (5).

In the case where the power supply unit is made double redundant with respect to the load, the power supply voltage abnormally rises (overvoltage) in (1).
Normal operation as a device at the time, (3) relaxation of the voltage effect in the OR circuit (corresponding to a large current load), and (6) other current against overcurrent (or voltage drop) caused by the common load. It is difficult to achieve load protection.

Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a configuration in which the number of redundant power supply units is not greater than the number of redundant load units, and which is one of overvoltage, voltage drop, and overcurrent. It is an object of the present invention to provide a power supply redundancy system that can normally operate equipment even when a single failure occurs.

[0016]

A first power supply redundancy system according to the present invention has a redundant configuration including a plurality of power supply units and a plurality of loads operated by power supplies supplied from the plurality of power supply units. At least one specific load is a power supply redundant system in which power is supplied from each of two or more power supply units, and a plurality of detection means for detecting an abnormality of power supply supplied from each of the plurality of power supply units, A plurality of transistors disposed on a plurality of power lines between the specific load and each of the two or more power units; and an on / off control of each of the plurality of transistors according to a detection result of the plurality of detection units. And control means for performing the following.

A second power supply redundancy system according to the present invention comprises:
In addition to the above-described configuration, the power supply apparatus further includes an instruction unit that instructs to forcibly supply power to the specific load via one of the plurality of transistors when power is turned on.

A third power supply redundancy system according to the present invention comprises:
In the above configuration, the specific load is a majority circuit that outputs a value according to majority logic for at least the outputs of the plurality of loads.

A fourth power supply redundancy system according to the present invention comprises:
In the above configuration, the plurality of transistors are transistors that have a low potential between a collector and an emitter when used in a saturation region.

A fifth power supply redundancy system according to the present invention comprises:
In the above structure, the plurality of transistors are field-effect transistors that have a low resistance between a drain and a source in an on state.

A sixth power supply redundancy system according to the present invention comprises:
A plurality of power supplies and a plurality of loads operated by the power supplied from the power supplies are redundantly configured, and at least one specific load of the plurality of loads is supplied with power from each of the first and second power supplies. A power supply redundant system to be supplied, wherein a plurality of detection means for detecting an abnormality of power supplied from each of the plurality of power supply units, and a plurality of detection units between the specific load and each of the first and second power supply units First and second transistors disposed on first and second power supply lines,
Control means for performing on / off control of each of the first and second transistors according to detection results of the plurality of detection means.

A seventh power supply redundancy system according to the present invention comprises:
In addition to the above-described configuration, the power supply apparatus further includes an instruction unit that instructs, when power is turned on, to forcibly supply power to the specific load via one of the first and second transistors.

An eighth power supply redundancy system according to the present invention comprises:
In the above configuration, the specific load is a majority circuit that outputs a value according to majority logic for at least the outputs of the plurality of loads.

A ninth power supply redundancy system according to the present invention comprises:
In the above configuration, the plurality of transistors are transistors that have a low potential between a collector and an emitter when used in a saturation region.

According to a tenth power supply redundancy system of the present invention, in the above configuration, the plurality of transistors are
The field effect transistor has a low resistance between the drain and the source in the on state.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

According to the present invention, a power supply line of a specific load among a plurality of loads having a redundant configuration is connected to a plurality of power supply sections having a redundant configuration similarly to the plurality of loads via an OR circuit using transistors. The power supply line is connected, and the on / off control of the transistor is performed by the abnormality detection signal when an abnormality occurs in the power line.

Thus, the power line in which the abnormality has occurred can be cut off, and only the normal power can be supplied to the specific load. Therefore, even if the power line is abnormal, the normal power can be supplied to the majority of the redundant loads. The operation can be maintained normally by the majority circuit.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, a power supply redundant system according to an embodiment of the present invention includes power supply units 1 and 2, loads 13 and 17 corresponding to power supply units 1 and 1 on a one-to-one basis, and transistors with low VCE (sat) function [or , Low RON function FET (F
Field Effect Transistor]], a load 15 connected to each of the power supply units 1 and 2 via the 6, 8 and a low VCE (sat) function transistor [or a low RON function FET] 10 and 12 And a majority circuit 19 connected to each of the power supply units 1 and 2 via the power supply unit.

Here, the low VCE (sat) function indicates that the potential between the collector (C) and the emitter (E) becomes low when the transistor is used in a saturation region (switching operation). It means that the voltage drop generated by passing through is small.

The low RON function indicates that the resistance between the drain and the source when the FET is turned on has a low resistance.
This means that the voltage drop generated by passing through the transistor is small.

The abnormality monitoring function of the power supply redundant system according to the embodiment of the present invention includes voltage monitoring circuits 3 and 4 for monitoring the voltages of the power supply units 1 and 2 (monitoring overvoltage and voltage drop).
And an overcurrent monitoring circuit 16 for monitoring the overcurrent (or voltage drop) of the load 15.

The voltage monitoring circuits 3 and 4 are circuits composed of transistors or comparators (OP amplifiers), resistors and capacitors, and the like.
Has the function of judging whether or not the voltage is within a predetermined voltage range, and outputting the judgment result as an on / off (“1” / “0”) signal.

The overcurrent monitoring circuit 16 also includes the voltage monitoring circuits 3 and 4
Similarly to the above, a circuit composed of a comparator (OP amplifier) and a resistor or a capacitor detects the occurrence of overcurrent, and outputs the detection result as an on / off (“1” / “0”) signal. Has functions.

Further, the redundancy control function of the power supply redundancy system according to one embodiment of the present invention is to turn on the power of the voltage monitoring circuits 3 and 4, the overcurrent monitoring circuit 16 and the loads 13 and 17 (Pow).
erOn) logic control circuits 5, 7 for controlling on / off of the transistors 6, 8 according to a predetermined logic based on a combination of the signals 24 to 28 from the circuits 14, 18
And control circuits 9 and 11 for controlling on / off of the transistors 10 and 12 according to signals 24 and 25 from the voltage monitoring circuits 3 and 4, respectively.

The logic control circuits 5 and 7 are composed of transistors, digital ICs (integrated circuits), resistors and capacitors, and the control circuits 9 and 11 are composed of transistors, resistors and capacitors.

If the power-on circuits 14 and 18 are designed so that the overcurrent monitoring circuit 16 monitors the overcurrent of the load 15 due to a voltage drop, the overcurrent monitoring circuit 16 and Are in the abnormal state, and the logic control circuits 5 and 7 do not operate to prevent the transistors 6 and 8 from being permanently turned off.

That is, when the power is turned on, the power-on circuits 14 and 18 are independent of the detection state of the overcurrent monitoring circuit 16,
If the voltage monitoring circuits 3 and 4 do not detect any abnormality, the transistors 6 and 8 are forcibly turned on.

The power-on circuits 14 and 18 each include a transistor or a digital IC, a resistor and a capacitor, and output an ON signal in synchronization with a self-diagnosis operation of each load after power-on, or after power-on. An ON signal is output by a dedicated circuit or the like that operates for a fixed time.

FIG. 2 is a diagram showing the logical operation of the logic control circuits 5 and 7 of FIG. FIG. 2A shows the logical operation of the logical control circuit 5, and FIG. 2B shows the logical operation of the logical control circuit 7.

In FIG. 2A, P1 indicates the value of the signal 26 from the power-on circuit 14, V1 indicates the value of the signal 24 from the voltage monitoring circuit 3, and I indicates the value of the overcurrent monitoring circuit 16.
, And R1 indicates an operation instruction for the transistor 6 by the logic control circuit 5.

The logic operation of the logic control circuit 5 will be described with reference to FIG. First, if P1, V1, and I are both in the off state, the logic control circuit 5 instructs the transistor 6 to perform an on operation [No. 1
reference].

When P1 and V1 are off and I is on, the logic control circuit 5 instructs the transistor 6 to perform an off operation [No. 2], P1, I
Is off and V1 is on, the logic control circuit 5 instructs the transistor 6 to perform an off operation [FIG.
No. of (a). 3].

If P1 is off and V1 and I are on, the logic control circuit 5 instructs the transistor 6 to perform an off operation [No. 4], if P1 is on and V1 and I are off, the logic control circuit 5 instructs the transistor 6 to perform an on operation [FIG.
No. of (a). 5].

If P1 and I are on and V1 is off, the logic control circuit 5 instructs the transistor 6 to perform an on operation [No. 6], P1, V
If 1 is on and I is off, the logic control circuit 5 instructs the transistor 6 to perform an off operation [FIG.
No. of (a). 7], and if P1, V1, and I are all in the on state, the logic control circuit 5 instructs the transistor 6 to perform the off operation [No. 8].

In FIG. 2B, P2 indicates the value of the signal 28 from the power-on circuit 18, V2 indicates the value of the signal 25 from the voltage monitoring circuit 4, and I indicates the value of the overcurrent monitoring circuit 16.
, And R2 indicates an operation instruction for the transistor 8 by the logic control circuit 7.

The logic operation of the logic control circuit 7 will be described with reference to FIG. First, if both P2, V2, and I are in the off state, the logic control circuit 7 instructs the transistor 8 to perform the on operation [No. 1
reference].

If P2 and V2 are off and I is on, the logic control circuit 7 instructs the transistor 8 to perform an off operation [No. 2], P2, I
Is off and V2 is on, the logic control circuit 7 instructs the transistor 8 to perform an off operation [FIG.
No. of (b). 3].

If P2 is off and V2 and I are on, the logic control circuit 7 instructs the transistor 8 to perform an off operation [No. If P2 is on and V2 and I are off, logic control circuit 7 instructs transistor 8 to perform an on operation [FIG.
No. of (b). 5].

If P2 and I are on and V2 is off, the logic control circuit 7 instructs the transistor 8 to perform an on operation [No. 6], P2, V
If 1 is on and I is off, the logic control circuit 7 instructs the transistor 8 to perform an off operation [FIG.
No. of (b). 7], and if P2, V2, and I are both on, the logic control circuit 7 instructs the transistor 8 to perform an off operation [No. 8].

FIG. 3 is a diagram showing the logical operation of each component in one embodiment of the present invention. In the figure, P1 indicates the value of the signal 26 from the power-on circuit 14, P2 indicates the value of the signal 28 from the power-on circuit 18, V1 indicates the value of the signal 24 from the voltage monitoring circuit 3, and V2 indicates The value of the signal 25 from the voltage monitoring circuit 4 is indicated, I indicates the value of the signal 27 from the overcurrent monitoring circuit 16, R1 indicates an operation instruction for the transistor 6 by the logic control circuit 5, and R2 indicates the logic control circuit 7 Indicates an operation instruction for the transistor 8 by
S1 indicates an operation instruction for the transistor 10 by the control circuit 9, and S2 indicates the transistor 1 by the control circuit 11.
2 indicates an operation instruction.

FIG. 4 is a timing chart showing an operation at the time of voltage drop according to one embodiment of the present invention, FIG. 5 is a timing chart showing an operation at the time of occurrence of overvoltage according to one embodiment of the present invention, and FIG. FIG. 7 is a timing chart illustrating an operation when an overcurrent occurs according to an embodiment of the present invention, and FIG. 7 is a timing chart illustrating an operation when power is turned on according to an embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

First, when the equipment is operating normally, the voltage monitoring circuits 3 and 4 and the overcurrent monitoring circuit 16 do not detect any abnormality, so that the logic control circuits 5 and 7 and the control circuits 9 and 11 are not detected.
, The transistors 6, 8, 10, and 12 are turned on (see No. 3 in FIG. 3).

When a voltage abnormality occurs due to the power supply unit 1 or the load 13, when the voltage monitoring circuit 3 detects the voltage abnormality, the transistors 6 and 10 are turned off under the control of the logic control circuit 5 and the control circuit 9 ( (See No. 4 in FIG. 3 and FIGS. 4 and 5).

As a result, the operation of the load 13 becomes abnormal, but the loads 15, 17 and the majority circuit 19 operate normally by the power of the power supply unit 2, so that the output of the device, that is, the output from the majority circuit 19 is normal. Operation.

In this case, the signal 24 from the voltage monitoring circuit 3 is also output to the power supply unit 1 in consideration of a case where a voltage drop occurs due to an overcurrent caused by the load 13, and the power supply unit 1
The operation is stopped in response to the input of "4".

When a voltage abnormality occurs due to the power supply unit 2 or the load 17, when the voltage monitoring circuit 4 detects the voltage abnormality, the transistors 8 and 12 are turned off under the control of the logic control circuit 7 and the control circuit 11 ( (See No. 5 in FIG. 3 and FIGS. 4 and 5).

As a result, the operation of the load 17 becomes abnormal, but the loads 13, 15 and the majority circuit 19 operate normally by the power of the power supply 1, so that the output of the equipment, that is, the output from the majority circuit 19 is normal. Operation.

In this case, the signal 25 from the voltage monitoring circuit 4 is also output to the power supply unit 2 in consideration of a case where a voltage drop occurs due to an overcurrent caused by the load 17, and the power supply unit 2
The operation is stopped in response to the input of "5".

When an overcurrent or a voltage drop occurs due to the load 15 and the overcurrent monitoring circuit 16 detects an abnormality, the transistors 6 and 8 are turned off under the control of the logic control circuits 5 and 7 (see FIG. 3). No. 6 and FIG. 6).

As a result, the operation of the load 15 becomes abnormal, but the loads 13, 17 and the majority circuit 19 are connected to the power supply unit 1,
2 operates normally with the power of 2, the output of the device, that is, the output from the majority circuit 19, operates normally.

When the overcurrent monitoring circuit 16 detects a voltage drop when the power is turned on, the operation is the same as when the abnormality is detected by the overcurrent monitoring circuit 16 described above. Will be turned off.

Therefore, when the power is turned on, the logic control circuits 5 and 7 turn on the transistors 6 and 8 according to the signals 26 and 28 from the power-on circuits 14 and 18 as necessary (Nos. 1 and 2 in FIG. 7), power is forcibly supplied to the load 15. The signals 26 and 28 from the power-on circuits 14 and 18 are turned on only during the period of supplying power to the load 15, and are turned off during other periods.

FIG. 8 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, a power supply redundant system according to another embodiment of the present invention includes power supplies 1, 2, 29 and loads 13, 15, which correspond to the power supplies 1, 2, 29 on a one-to-one basis.
17 and a transistor with low VCE (sat) function [or
Power supply units 1 and 2 via FETs with low RON function] 10 and 12
And a majority circuit 19 connected to each of them.

The abnormality monitoring function of the power supply redundant system according to another embodiment of the present invention includes a voltage monitoring circuit 3, 4 for monitoring the voltage of each of the power supply units 1, 2, 29 (overvoltage or voltage drop). 30.

The voltage monitoring circuits 3, 4, 30 are circuits composed of transistors or comparators (OP amplifiers), resistors and capacitors, etc.
It is determined whether 0, 21 is within a predetermined voltage range,
It has a function of outputting the determination result as an on / off (“1” / “0”) signal.

Further, the redundancy control function of the power supply redundancy system according to another embodiment of the present invention is to provide transistors 10 and 12 according to signals 24 and 25 from voltage monitoring circuits 3 and 4.
And control circuits 9 and 11 for controlling the turning on and off of.

The operation of another embodiment of the present invention will be described with reference to FIG. First, when the equipment is operating normally, the voltage monitoring circuits 3 and 4 do not detect any abnormality, so that the transistors 10 and 12 are controlled by the control circuits 9 and 11.
Turns on.

When a voltage abnormality occurs due to the power supply unit 1 or the load 13, when the voltage monitoring circuit 3 detects the voltage abnormality, the transistor 10 is turned off under the control of the control circuit 9. As a result, the operation of the load 13 becomes abnormal, but the load 17 and the majority circuit 19 operate normally by the power of the power supply unit 2, and the load 15 operates normally by the power of the power supply unit 29. That is, the output from the majority circuit 19 operates normally.

In this case, the signal 24 from the voltage monitoring circuit 3 is also output to the power supply unit 1 and the power supply unit 1 outputs the signal 2
The operation is stopped in response to the input of "4".

When a voltage abnormality occurs due to the power supply unit 2 or the load 17, when the voltage monitoring circuit 4 detects the voltage abnormality, the transistor 12 is turned off under the control of the control circuit 11. As a result, the operation of the load 17 becomes abnormal, but the load 13 and the majority circuit 19 operate normally with the power of the power supply unit 1 and the load 15 operates normally with the power of the power supply unit 29. That is, the output from the majority circuit 19 operates normally.

In this case, the signal 25 from the voltage monitoring circuit 4 is also output to the power supply unit 2 in consideration of a case where a voltage drop occurs due to an overcurrent caused by the load 17, and the power supply unit 2 outputs the signal 2
The operation is stopped in response to the input of "5".

When a voltage abnormality occurs due to the power supply unit 29, when the voltage monitoring circuit 30 detects the voltage abnormality, a signal 31 from the voltage monitoring circuit 29 is output to the power supply unit 29, and the power supply unit 29 Stop operation in response to input.

As a result, the operation of the load 15 becomes abnormal, but the loads 13, 17 and the majority circuit 19 are connected to the power supply unit 1,
2 operates normally with the power of 2, the output of the device, that is, the output from the majority circuit 19, operates normally.

In the above-described embodiment of the present invention, the power supply unit has a double redundant configuration, and the load unit has a triple redundant configuration. A single abnormality in the power supply line is assumed for both the load section and the load section as a triple redundancy. However, it is possible to apply one embodiment and another embodiment of the present invention to a more redundant configuration.

As described above, according to the detection results of the voltage monitoring circuits 3 and 4 for detecting the abnormality of the power supplied from the power supply units 1 and 2, the load 15 and the majority circuit 19 and the power supply units 1 and
The logic control circuits 5, 7 and the control circuits 9, 11 perform on / off control of the plurality of transistors 6, 8, 10, 12 disposed on the plurality of power supply lines 20, 21 between them. , Power lines 20, 2 in which an abnormality has occurred
1 and only normal power is applied to the load 15 and the majority circuit 1
9 can be supplied.

Therefore, in a configuration in which the number of redundancy of the power supply unit is not larger than the number of redundancy of the load unit, it is possible to normally operate the device even in the event of a single failure among overvoltage, voltage drop and overcurrent. Can be.

[0078]

As described above, according to the present invention, a redundant configuration is provided with a plurality of power supplies and a plurality of loads operated by the power supplied from the power supplies, and at least one of the plurality of loads is provided. In a power supply redundant system in which a specific load is supplied with power from each of two or more power supply units,
According to the detection results of the plurality of detection means for detecting an abnormality of the power supplied from each of the plurality of power units, the plurality of power units are arranged on the plurality of power lines between the specific load and each of the two or more power units. By performing on / off control of each of the plurality of transistors, the configuration is such that the number of redundant power supply units is not greater than the number of redundant load units. There is an effect that the device can be operated normally.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

2A is a diagram illustrating a logical operation of the logic control circuit of FIG. 1, and FIG. 2B is a diagram illustrating a logical operation of the logic control circuit of FIG.

FIG. 3 is a diagram showing a logical operation of each component of the embodiment of the present invention.

FIG. 4 is a timing chart showing an operation at the time of a voltage drop according to one embodiment of the present invention.

FIG. 5 is a timing chart showing an operation when an overvoltage occurs according to an embodiment of the present invention.

FIG. 6 is a timing chart showing an operation when an overcurrent occurs according to an embodiment of the present invention.

FIG. 7 is a timing chart showing an operation at power-on according to one embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional example.

FIG. 10 is a block diagram showing another configuration of the conventional example.

[Explanation of symbols]

 1, 2, 29 Power supply unit 3, 4, 30 Voltage monitoring circuit 5, 7 Logic control circuit 6, 8, 10, 12 Transistor 9, 11 Control circuit 13, 15, 17 Load 14, 18 Power-on circuit 16 Overcurrent monitoring Circuit 19 majority circuit

──────────────────────────────────────────────────続 き Continued on the front page (56) References JP-A-51-147742 (JP, A) JP-A-56-74723 (JP, A) JP-A-58-26531 (JP, A) JP-A-1- 133570 (JP, A) JP-A-3-212743 (JP, A) JP-A-3-291708 (JP, A) JP-A-4-17520 (JP, A) JP-A-5-111153 (JP, A) JP-A-5-252673 (JP, A) JP-A-7-36575 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) B64G 1/42-1/44 G06F 1/26 -1/32 G06F 11/16-11/20 H02H 3/05 H02J 1/00-1/16 H02J 9/00 H05K 10/00

Claims (6)

(57) [Claims] 1. A redundant configuration comprising a plurality of power supplies and a plurality of loads operated by power supplied from the power supplies, wherein at least one specific load among the plurality of loads is a power supply having at least two power supplies. Power supply system from which power is supplied from the power supply, and monitors voltage states of the plurality of power supply units
A plurality of power supply unit monitoring means, and a voltage state of the specific load.
Load monitoring means for monitoring the load,
Load monitoring means for monitoring the voltage state of the load, and the specific load
And a plurality of power lines between each of the two or more power units
A plurality of transistors disposed thereon, and the power supply unit monitoring
Means, the specific load monitoring means, and monitoring of the load monitoring means
On / off control of each of the plurality of transistors according to a result.
Power supply redundancy having logic control means for controlling
Long system. 2. The power supply redundancy system according to claim 1, further comprising an instruction means for instructing to supply power to said specific load via one of said plurality of transistors when power is turned on. 3. The power supply redundancy system according to claim 1, wherein the specific load is a majority circuit that outputs a value according to majority logic with respect to at least outputs of the plurality of loads. 4. A redundant configuration comprising a plurality of power supply units and a plurality of loads operated by power supplies supplied from the power supply units, wherein at least one specific load among the plurality of loads is a first and a second power supply. A power supply redundant system in which power is supplied in common from each of the power supply units;
A plurality of power supply unit monitoring means for monitoring a state, and the specific load;
Specific load monitoring means for monitoring the voltage state of the
Load monitoring means for monitoring the voltage state of the load excluding the load;
A first load between the specific load and each of the first and second power supply units.
A plurality of transistors arranged on the first and second power supply lines;
And the power supply unit monitoring unit and the specific load monitoring unit.
The first and the second according to the monitoring result of the load monitoring means.
Control means for performing on / off control of each of the transistors
A power supply redundancy system, comprising: 5. The power supply according to claim 4, further comprising an instruction unit for instructing, when power is turned on, forcibly supplying power to said specific load via one of said first and second transistors. Power redundancy system. 6. The power supply redundancy system according to claim 4, wherein the specific load is a majority circuit that outputs a value according to majority logic with respect to outputs of at least the plurality of loads.