JPH09182291A - Power supply redundancy system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to operate normally at a single failure caused by an overvoltage, a voltage drop or an overcurrent in a constitution, in which redundancy of power supply is not larger than redundancy of load part. SOLUTION: Transistors 6 and 8 are turned on and off under control of logic control circuits 5 and 7 on the basis of previously set assorted signals made up of signals 24 and 2 from voltage monitoring circuits 3 and 4, a signal 27 from an overcurrent monitoring circuit 16, and signals 26 and 28 from power-on circuits 14 and 18 of loads 13 and 17. In addition transistors 10 and 12 are turned on and off under control of control circuits 9 and 11 on the basis of signals 24 and 25 from the voltage monitoring circuit 3 and 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply redundancy system, and more particularly to a power supply redundancy system used for space equipment.

[0002]

2. Description of the Related Art Space equipment is required to have a highly reliable operation in a harsh space environment and to be small and lightweight. Is also a redundant configuration.

In the redundant configuration of the power supply section (DC / DC converter), the determination voltage of the overvoltage detection circuit existing in each DC / DC converter is not generated from the secondary voltage supplied to the load, but DC / DC converter. Some DC converters are configured to generate from the output of a rectifier circuit that is separately configured. In this case, only the power supply unit (DC / DC converter) has a redundant configuration and the load unit has a single configuration.

Since all the outputs of the redundant DC / DC converter are commonly connected to the load, if any of the outputs is judged based on the voltage output to the load, any one of them will be detected. When the DC / DC converter fails and overvoltage occurs, all the DC / DC converters detect an abnormality and stop functioning.

Therefore, in each DC / DC converter, a rectifier circuit is provided separately from the voltage line supplied to the load, and the output of the rectifier circuit is used to determine the overvoltage, so that only the abnormal DC / DC converter is detected. The function of is stopped. Regarding this technique, Japanese Patent Laid-Open No. 1-1335
No. 70, a detailed description is given.

Further, as a redundant configuration of the above power supply section,
As shown in FIG. 9, the loads 34 to 36 and the power supply units 31 to 33.
Are connected to each other in a one-to-one manner, and the power supplies 3 are connected to the loads 34 to 36.
There is one in which 1 to 33 are simply triple redundant.

In this case, the majority decision circuit 37 decides the output value of the outputs of the loads 34 to 36 by a majority decision, and the majority decision circuit 37 is supplied with power from the power supply section 31.

Further, as a redundant configuration of the power supply unit, FIG.
As shown in 0, the loads 44 and 46 and the power supply units 41 and 42 are connected in a one-to-one manner, and the diodes 43a and 43
There is also one in which the power supply units 41 and 42 are connected to the load 45 and the majority circuit 47 through the OR circuit 43 configured by using b to provide double redundancy.

[0009]

In the above-mentioned conventional redundant configuration of the power supply unit, since the overvoltage is only determined by the output of the rectifier circuit, when an abnormality such as a voltage drop occurs in the DC / DC converter. , The abnormality cannot be detected.

Therefore, the voltage supplied to the load may fluctuate even with the redundant configuration. That is, one D
When the output voltage of the C / DC converter drops, there is no guarantee that the output voltage of another normal DC / DC converter will stabilize the supply voltage to the load.

Further, the above redundant configuration is invalid when an abnormality occurs in the power supply line due to a cause on the load side, for example, a short circuit between the power supply and GND (ground) due to a failure of an electric component. That is, the above-mentioned redundant configuration is a redundant configuration of only the power supply unit, and the operation abnormality due to the cause on the load side is not considered.

On the other hand, regarding the redundant system of the power supply line, (1) normal operation as a device when the power supply voltage abnormally rises (overvoltage) (2) normal operation as a device when the power supply voltage abnormally falls (low voltage) (3) Mitigation of voltage effect in OR circuit (corresponding to large current load) (4) Supply of redundant power to majority circuit (5) Reduction of number of power supplies (6) Overcurrent (or voltage) due to common load There is a problem of protection of other loads against (degradation), and it is desirable to solve these problems at the same time.

However, in the case where the power supply unit is simply triple-redundant with respect to the load, (1) normal operation as a device when the power supply voltage abnormally rises (overvoltage) and (4) the majority circuit It is difficult to realize the redundant power supply of (1) and the reduction of the number of power supplies of (5).

Further, in the case where the power supply section is double redundant with respect to the load, (1) abnormal increase in power supply voltage (overvoltage)
Normal operation as a device at the time, (3) mitigation of voltage effect in the OR circuit (corresponding to large current load), and (6) other against overcurrent (or voltage drop) due to common load It is difficult to realize load protection.

Therefore, an object of the present invention is to solve the above-mentioned problems, and to prevent the redundant number of the power source section from exceeding the redundant number of the load section, and to select one of overvoltage, voltage drop and overcurrent. An object of the present invention is to provide a power supply redundancy system that can operate the equipment normally even when a single failure occurs.

[0016]

A first power supply redundancy system according to the present invention is redundantly configured by a plurality of power supply units and a plurality of loads operated by power supplies supplied from the power supply units, and the plurality of loads of the plurality of loads are provided. At least one of the specific loads is a power supply redundancy system in which power is supplied from each of two or more power supply units, and a plurality of detection means for detecting an abnormality in the power supply supplied from each of the plurality of power supply units, A plurality of transistors arranged on a plurality of power supply lines between the specific load and each of the two or more power supply units, and on / off control of each of the plurality of transistors according to detection results of the plurality of detection means. And control means for performing.

A second power supply redundancy system according to the present invention is
In addition to the above configuration, an instruction means for instructing to forcibly supply power to the specific load via any of the plurality of transistors when the power is turned on is provided.

A third power supply redundancy system according to the present invention is
In the above configuration, the specific load is a majority circuit that outputs a value according to the majority logic for at least the outputs of the plurality of loads.

A fourth power supply redundancy system according to the present invention is
In the above structure, the plurality of transistors are transistors having a low potential between the collector and the emitter when used in the saturation region.

A fifth power supply redundancy system according to the present invention is
In the above structure, the plurality of transistors are field effect transistors having a low resistance between the drain and the source when in the ON state.

A sixth power supply redundancy system according to the present invention is
A redundant configuration is made up of a plurality of power supply units and a plurality of loads that are operated by the power supplies supplied from these power supply units, and at least one specific load of the plurality of loads is supplied with power from each of the first and second power supply units. A power supply redundancy system for supplying power, wherein a plurality of detection means for detecting an abnormality in power supplied from each of the plurality of power supply units, and the specific load and each of the first and second power supply units are provided. First and second transistors arranged on the first and second power supply lines;
And a control unit for performing on / off control of each of the first and second transistors according to the detection results of the plurality of detection units.

A seventh power supply redundancy system according to the present invention is
In addition to the above configuration, an instruction means is provided for instructing to forcibly supply power to the specific load via one of the first and second transistors when the power is turned on.

An eighth power supply redundancy system according to the present invention is
In the above configuration, the specific load is a majority circuit that outputs a value according to the majority logic for at least the outputs of the plurality of loads.

A ninth power supply redundancy system according to the present invention is
In the above structure, the plurality of transistors are transistors having a low potential between the collector and the emitter when used in the saturation region.

According to a tenth power supply redundancy system of the present invention, in the above configuration, the plurality of transistors are
The field effect transistor has a low resistance between the drain and the source in the ON state.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

According to the present invention, the power supply line of a specific load among a plurality of loads having a redundant configuration is connected to a plurality of power supply units having a redundant configuration like a plurality of loads through an OR circuit using a transistor. When the power line is connected, the transistor is connected and ON / OFF is controlled by an abnormality detection signal.

As a result, the power supply line in which an abnormality has occurred can be cut off and only normal power can be supplied to a specific load. Therefore, even if the power supply line has an abnormality, the normal power is supplied to a majority of the loads having a redundant configuration. It becomes possible to supply, and it becomes possible to maintain normal operation of the equipment by the majority circuit.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, a power supply redundancy system according to an embodiment of the present invention includes power supply units 1 and 2, loads 13 and 17 corresponding to the power supply units 1 and 2 on a one-to-one basis, and a transistor having a low VCE (sat) function [or , FET with low RON function (F
Field Effect Transistor)] 6, a load 15 connected to each of the power supply units 1 and 2 via 6, 8 and a transistor with low VCE (sat) function [or FET with low RON function] 10, 12 It is composed of a majority circuit 19 connected to each of the power supply units 1 and 2 via the circuit.

Here, the low VCE (sat) function means that the potential between the collector (C) and the emitter (E) becomes low when the transistor is used in the saturation region (switching operation), This means that the voltage drop that occurs when the battery is passed through is small.

The low RON function means that the resistance between the drain and the source when the FET is turned on is low.
It means that the voltage drop generated through the transistor is small.

Further, the abnormality monitoring function of the power supply redundancy system according to the embodiment of the present invention has the voltage monitoring circuits 3 and 4 for monitoring the voltage of each of the power supply units 1 and 2 (monitoring overvoltage and voltage drop).
And an overcurrent monitoring circuit 16 for monitoring overcurrent (or voltage drop) of the load 15.

The voltage monitoring circuits 3 and 4 are circuits composed of transistors or comparators (OP amplifiers) and resistors and capacitors, and the power supply lines 20 and 21 to be monitored.
Has a function of determining whether or not the voltage is within a predetermined voltage range and outputting the determination result as an on / off (“1” / “0”) signal.

The overcurrent monitoring circuit 16 is also a voltage monitoring circuit 3, 4
Similarly to the above, a circuit composed of a comparator (OP amplifier), a resistor, a capacitor and the like detects the occurrence of overcurrent and outputs the detection result as an ON / OFF (“1” / “0”) signal. Have a function.

Further, the redundancy control function of the power supply redundancy system according to the embodiment of the present invention is such that the voltage monitoring circuits 3 and 4, the overcurrent monitoring circuit 16 and the loads 13 and 17 are powered on (Pow).
erOn) circuits 14 and 18 and signals 24 to 28 are combined to control the on / off of transistors 6 and 8 according to a predetermined logic.
And the control circuits 9 and 11 for controlling the on / off of the transistors 10 and 12 according to the signals 24 and 25 from the voltage monitoring circuits 3 and 4, respectively.

The logic control circuits 5 and 7 are composed of transistors, digital ICs (integrated circuits), resistors and capacitors, and the control circuits 9 and 11 are composed of transistors, resistors and capacitors.

When the power-on circuits 14 and 18 are designed so that the overcurrent monitoring circuit 16 monitors the overcurrent of the load 15 by the voltage drop, the overcurrent monitoring circuit 16 is until the load 15 is supplied with power. Is in an abnormality detection state, and the logic control circuits 5 and 7 do not operate, and the transistors 6 and 8 are permanently turned off.

That is, the power-on circuits 14 and 18 are irrespective of the detection state of the overcurrent monitoring circuit 16 when the power is turned on,
If the voltage monitoring circuits 3 and 4 have not detected an abnormality, the transistors 6 and 8 are forcibly turned on.

The power-on circuits 14 and 18 are composed of transistors or digital ICs, resistors and capacitors, and output an on-signal in synchronization with the self-diagnosis operation of each load after power-on, or after power-on. An ON signal is output by a dedicated circuit or the like that operates for a fixed time.

FIG. 2 is a diagram showing the logical operation of the logic control circuits 5 and 7 of FIG. 2A shows the logical operation of the logic control circuit 5, and FIG. 2B shows the logical operation of the logic control circuit 7.

In FIG. 2A, P1 indicates the value of the signal 26 from the power-on circuit 14, V1 indicates the value of the signal 24 from the voltage monitoring circuit 3, and I indicates the overcurrent monitoring circuit 16.
Of the signal 27, and R1 indicates an operation instruction to the transistor 6 by the logic control circuit 5.

The logic operation of the logic control circuit 5 will be described with reference to FIG. First, if P1, V1 and I are all in the off state, the logic control circuit 5 instructs the transistor 6 to perform the on operation [No. 1
reference].

If P1 and V1 are off and I is on, the logic control circuit 5 instructs the transistor 6 to perform an off operation [No. 2], P1, I
Is off and V1 is on, the logic control circuit 5 instructs the transistor 6 to turn off [FIG.
No. of (a). 3].

If P1 is off and V1 and I are on, the logic control circuit 5 instructs the transistor 6 to perform an off operation [No. 4], P1 is in the ON state, and V1 and I are in the OFF state, the logic control circuit 5 instructs the transistor 6 to perform the ON operation [FIG.
No. of (a). 5].

When P1 and I are on and V1 is off, the logic control circuit 5 instructs the transistor 6 to perform an on operation [No. 6], P1, V
If 1 is in the on state and I is in the off state, the logic control circuit 5 instructs the transistor 6 to perform the off operation [FIG.
No. of (a). 7], and P1, V1, and I are both in the ON state, the logic control circuit 5 instructs the transistor 6 to perform the OFF operation [No. 8].

In FIG. 2B, P2 indicates the value of the signal 28 from the power-on circuit 18, V2 indicates the value of the signal 25 from the voltage monitoring circuit 4, and I indicates the overcurrent monitoring circuit 16.
The value of the signal 27 from R.sub.2 to R.sub.2 indicates the operation instruction to the transistor 8 by the logic control circuit 7.

The logic operation of the logic control circuit 7 will be described with reference to FIG. First, if P2, V2, and I are both off, the logic control circuit 7 instructs the transistor 8 to perform an on operation [No. 1
reference].

When P2 and V2 are off and I is on, the logic control circuit 7 instructs the transistor 8 to perform an off operation [No. 2], P2, I
Is off and V2 is on, the logic control circuit 7 instructs the transistor 8 to turn off [FIG.
(B) No. 3].

When P2 is off and V2 and I are on, the logic control circuit 7 instructs the transistor 8 to perform an off operation [No. 4], P2 is on, and V2 and I are off, the logic control circuit 7 instructs the transistor 8 to perform an on operation [FIG.
(B) No. 5].

If P2 and I are on and V2 is off, the logic control circuit 7 instructs the transistor 8 to perform an on operation [No. 6], P2, V
If 1 is on and I is off, the logic control circuit 7 instructs the transistor 8 to turn off [FIG.
(B) No. 7]], P2, V2, and I are both in the ON state, the logic control circuit 7 instructs the transistor 8 to perform the OFF operation [No. 8].

FIG. 3 is a diagram showing the logical operation of each component of one embodiment of the present invention. In the figure, P1 indicates the value of the signal 26 from the power-on circuit 14, P2 indicates the value of the signal 28 from the power-on circuit 18, V1 indicates the value of the signal 24 from the voltage monitoring circuit 3, and V2 indicates The value of the signal 25 from the voltage monitoring circuit 4 is shown, I is the value of the signal 27 from the overcurrent monitoring circuit 16, R1 is an operation instruction for the transistor 6 by the logic control circuit 5, and R2 is the logic control circuit 7. Shows an operation instruction to the transistor 8 by
S1 indicates an operation instruction to the transistor 10 by the control circuit 9, and S2 indicates the transistor 1 by the control circuit 11.
2 shows an operation instruction for No. 2.

FIG. 4 is a timing chart showing the operation at the time of voltage drop according to the embodiment of the present invention, FIG. 5 is a timing chart showing the operation at the time of overvoltage occurrence according to the embodiment of the present invention, and FIG. 9 is a timing chart showing an operation when an overcurrent is generated according to an embodiment of the present invention, and FIG. 7 is a timing chart showing an operation at power-on according to an embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

First, when the equipment is operating normally, the voltage monitoring circuits 3 and 4 and the overcurrent monitoring circuit 16 do not detect any abnormality, so that the logic control circuits 5 and 7 and the control circuits 9 and 11 are not detected.
The transistors 6, 8, 10 and 12 are turned on by the control of (1) (see No. 3 in FIG. 3).

When a voltage abnormality occurs due to the power supply unit 1 or the load 13, when the voltage monitoring circuit 3 detects the voltage abnormality, the transistors 6 and 10 are turned off under the control of the logic control circuit 5 and the control circuit 9 ( Refer to No. 4 and FIGS.

As a result, the operation of the load 13 becomes abnormal, but the loads 15 and 17 and the majority decision circuit 19 operate normally by the power of the power supply section 2, so that the output of the equipment, that is, the output from the majority decision circuit 19 is normal. It will work.

In this case, in consideration of the case where a voltage drop occurs due to an overcurrent due to the cause of the load 13, the signal 24 from the voltage monitoring circuit 3 is also output to the power supply unit 1, and the power supply unit 1 outputs the signal 2
The operation is stopped in response to the input of 4.

When a voltage abnormality occurs due to the power supply section 2 or the load 17, and the voltage monitoring circuit 4 detects the voltage abnormality, the transistors 8 and 12 are turned off under the control of the logic control circuit 7 and the control circuit 11 ( Refer to No. 5 and FIGS.

As a result, the operation of the load 17 becomes abnormal, but the loads 13, 15 and the majority decision circuit 19 operate normally by the power of the power supply section 1, so the output of the device, that is, the output from the majority decision circuit 19 is normal. It will work.

In this case, considering the case where a voltage drop occurs due to an overcurrent due to the load 17, the signal 25 from the voltage monitoring circuit 4 is also output to the power supply unit 2, and the power supply unit 2 outputs the signal 2.
The operation is stopped in response to the input of 5.

When an overcurrent or a voltage drop occurs due to the load 15, and the overcurrent monitoring circuit 16 detects an abnormality, the transistors 6 and 8 are turned off under the control of the logic control circuits 5 and 7 (see FIG. 3). (See No. 6 and FIG. 6).

As a result, the operation of the load 15 becomes abnormal, but the loads 13 and 17 and the majority decision circuit 19 are
Since the power of 2 normally operates, the output of the device, that is, the output from the majority circuit 19 is in normal operation.

If the overcurrent monitoring circuit 16 detects a voltage drop when the power is turned on, the operation is the same as when the overcurrent monitoring circuit 16 detects an abnormality, and the power from the power supply units 1 and 2 to the load 15 is detected. Is cut off.

Therefore, when the power is turned on, the logic control circuits 5 and 7 turn on the transistors 6 and 8 by the signals 26 and 28 from the power-on circuits 14 and 18 as required (see Nos. 1 and 2 and FIG. 7), the power is forcibly supplied to the load 15. The signals 26 and 28 from the power-on circuits 14 and 18 are turned on only during the period in which power is supplied to the load 15, and are turned off during the other periods.

FIG. 8 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, a power supply redundancy system according to another embodiment of the present invention includes power supply units 1, 2, 29 and loads 13, 15, which respectively correspond to the power supply units 1, 2, 29 on a one-to-one basis.
17 and transistor with low VCE (sat) function [or
FET with low RON function]
It is composed of a majority circuit 19 connected to each.

The abnormality monitoring function of the power supply redundancy system according to another embodiment of the present invention is a voltage monitoring circuit 3, 4, which monitors the voltage of each of the power supply units 1, 2 and 29 (monitors overvoltage and voltage drop). It is composed of thirty.

The voltage monitoring circuits 3, 4, 30 are circuits composed of transistors or comparators (OP amplifiers), resistors, capacitors, etc., and the power supply line 2 to be monitored.
It is determined whether 0 or 21 is within a predetermined voltage range,
It has a function of outputting the determination result as an on / off (“1” / “0”) signal.

In addition, the redundancy control function of the power supply redundancy system according to another embodiment of the present invention is such that the transistors 10, 12 according to the signals 24, 25 from the voltage monitoring circuits 3, 4 are used.
It is composed of control circuits 9 and 11 for controlling the on / off of.

The operation of another embodiment of the present invention will be described with reference to FIG. First, when the equipment is operating normally, the voltage monitoring circuits 3 and 4 do not detect an abnormality, so that the transistors 10 and 12 are controlled by the control circuits 9 and 11.
Turns on.

When a voltage abnormality occurs due to the power supply unit 1 or the load 13, when the voltage monitoring circuit 3 detects the voltage abnormality, the control circuit 9 controls the transistor 10 to turn off. As a result, the operation of the load 13 becomes abnormal, but the load 17 and the majority decision circuit 19 operate normally by the power of the power supply unit 2, and the load 15 operates normally by the power of the power supply unit 29. That is, the output from the majority decision circuit 19 becomes a normal operation.

In this case, in consideration of a case where a voltage drop occurs due to an overcurrent due to the load 13, the signal 24 from the voltage monitoring circuit 3 is also output to the power supply unit 1, and the power supply unit 1 outputs the signal 2
The operation is stopped in response to the input of 4.

When a voltage abnormality occurs due to the power supply unit 2 or the load 17, when the voltage monitoring circuit 4 detects the voltage abnormality, the control circuit 11 controls the transistor 12 to turn off. As a result, the operation of the load 17 becomes abnormal, but the load 13 and the majority decision circuit 19 operate normally with the power of the power supply unit 1, and the load 15 operates normally with the power of the power supply unit 29. That is, the output from the majority decision circuit 19 becomes a normal operation.

In this case, considering the case where a voltage drop occurs due to an overcurrent due to the load 17, the signal 25 from the voltage monitoring circuit 4 is also output to the power supply unit 2, and the power supply unit 2 outputs the signal 2
The operation is stopped in response to the input of 5.

When the voltage abnormality occurs due to the power supply unit 29 and the voltage monitoring circuit 30 detects the voltage abnormality, the signal 31 from the voltage monitoring circuit 29 is output to the power supply unit 29, and the power supply unit 29 outputs the signal 31. Stops operation in response to input.

As a result, the operation of the load 15 becomes abnormal, but the loads 13, 17 and the majority circuit 19 are connected to the power supply unit 1,
Since the power of 2 normally operates, the output of the device, that is, the output from the majority circuit 19 is in normal operation.

In the above-described embodiment of the present invention, it is assumed that the power supply section has dual redundancy and the load section has triple redundancy, and a single abnormality of the power supply line is assumed. In another embodiment of the present invention, the power supply section is It is assumed that both the power supply line and the load portion are triple redundant, and a single abnormality in the power supply line is assumed, but one embodiment and another embodiment of the present invention can be applied to more redundant configurations.

As described above, the load 15 and the majority circuit 19 and the power supply unit 1 and the power supply unit 1, 4 are detected according to the detection results of the voltage monitoring circuits 3 and 4 for detecting the abnormality of the power supplies supplied from the power supply units 1 and 2.
By performing on / off control of each of the plurality of transistors 6, 8, 10, 12 arranged on the plurality of power supply lines 20, 21 between each of the two by the logic control circuits 5, 7 and the control circuits 9, 11. , The power line 20 or 2 where the abnormality occurred
1 is cut off and only normal power is supplied to the load 15 and the majority circuit 1
9 can be supplied.

Accordingly, the redundant number of the power source section does not become larger than the redundant number of the load section, and the equipment is normally operated even in the case of a single failure among overvoltage, voltage drop and overcurrent. You can

[0078]

As described above, according to the present invention, a redundant configuration is made up of a plurality of power supply units and a plurality of loads operated by the power supplies supplied from these power supply units, and at least one of the plurality of loads is provided. In a power supply redundancy system in which a specific load is supplied with power from two or more power supply units,
According to the detection result of the plurality of detection means for detecting the abnormality of the power supplied from each of the plurality of power supply units, the plurality of power supply units are arranged on the plurality of power supply lines between the specific load and each of the two or more power supply units. By controlling the on / off of each of a plurality of transistors, the redundant number of power supply units does not exceed the redundant number of load units, and even in the event of a single failure of overvoltage, voltage drop, or overcurrent. There is an effect that the device can be operated normally.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

2A is a diagram showing a logical operation of the logic control circuit of FIG. 1, and FIG. 2B is a diagram showing a logical operation of the logic control circuit of FIG.

FIG. 3 is a diagram showing a logical operation of each component of one embodiment of the present invention.

FIG. 4 is a timing chart showing an operation at the time of voltage drop according to an embodiment of the present invention.

FIG. 5 is a timing chart showing an operation when an overvoltage is generated according to an embodiment of the present invention.

FIG. 6 is a timing chart showing an operation when an overcurrent occurs according to an embodiment of the present invention.

FIG. 7 is a timing chart showing an operation at power-on according to an embodiment of the present invention.

FIG. 8 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional example.

FIG. 10 is a block diagram showing another configuration of the conventional example.

[Explanation of symbols]

 1, 2, 29 Power supply section 3, 4, 30 Voltage monitoring circuit 5, 7 Logic control circuit 6, 8, 10, 12 Transistor 9, 11 Control circuit 13, 15, 17 Load 14, 18 Power-on circuit 16 Overcurrent monitoring Circuit 19 Majority circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 1/26 H02M 3/00 C H02M 3/00 W G06F 1/00 330C

Claims (10)

[Claims] 1. A redundant configuration including a plurality of power supply units and a plurality of loads that are operated by power supplied from the power supply units, and at least one specific load of the plurality of loads is two or more power supply units. A redundant power supply system in which power is supplied from a plurality of detection means for detecting an abnormality in the power supply supplied from each of the plurality of power supply units, and between the specific load and each of the two or more power supply units. A plurality of transistors arranged on the plurality of power supply lines, and a control means for performing on / off control of each of the plurality of transistors according to a detection result of the plurality of detection means. . 2. The power supply redundancy system according to claim 1, further comprising an instruction means for instructing to forcibly supply power to the specific load via any one of the plurality of transistors when the power is turned on. 3. The power supply redundancy system according to claim 1, wherein the specific load is a majority circuit that outputs a value according to a majority logic for at least outputs of the plurality of loads. 4. The power supply according to claim 1, wherein the plurality of transistors are transistors having a low potential between a collector and an emitter when used in a saturation region. Redundant system. 5. The transistor according to claim 1, wherein the plurality of transistors are field effect transistors having a low resistance between a drain and a source in an on state.
The power supply redundancy system described in any one of. 6. A redundant configuration including a plurality of power supply units and a plurality of loads operated by the power supplies supplied from the power supply units, wherein at least one specific load of the plurality of loads is a first power supply and a second power supply. A power supply redundancy system in which power is supplied from each unit, a plurality of detection means for detecting an abnormality in the power supplied from each of the plurality of power supply units, the specific load, and the first and second power supply units. The first between each
And first and second transistors arranged on the second power supply line, and control means for performing on / off control of each of the first and second transistors according to the detection results of the plurality of detection means. A power supply redundancy system having. 7. The method according to claim 6, further comprising an instruction means for instructing to forcibly supply power to the specific load via one of the first and second transistors when the power is turned on. Power redundancy system. 8. The power supply redundancy system according to claim 6, wherein the specific load is a majority decision circuit that outputs a value according to a majority decision logic for at least the outputs of the plurality of loads. 9. The power supply according to claim 6, wherein the plurality of transistors are transistors having a low potential between a collector and an emitter when used in a saturation region. Redundant system. 10. The power supply redundancy system according to claim 6, wherein the plurality of transistors are field effect transistors having a low resistance between a drain and a source in an on state. .