JPH05265026A - Semiconductor element and liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide a semiconductor element capable of easily executing inspection even when the semiconductor element has many terminals or fine terminal pitches and attaining the improvement of reliability and the reduction of cost. CONSTITUTION:The semiconductor element provided with an internal circuit 10 formed on a semiconductor substrate and having a prescribed function, an input terminal 11 for applying an input terminal A from the external to the circuit 10 and an output terminal 12 for extracting an output signal B from the circuit 10 to the external is characteristically provided with a logical circuit 20 mounted on the same substrate as that of the circuit 10 to input the output signal B from the circuit 10, execute prescribed logical operation and reduce the number of outputs corresponding to the input and an inspection terminal 21 for extracting an output signal C from the circuit 20 to the external.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having multiple terminals and fine pitch output terminals, and more particularly to a semiconductor device which facilitates an operation test based on a signal appearing at the output terminals.

The present invention also relates to an active matrix type liquid crystal display device equipped with a thin film transistor and a diode, and more particularly to a liquid crystal display device which facilitates an operation test and a mounting test of a drive IC.

[0003]

2. Description of the Related Art In recent years, with the progress of semiconductor integrated circuit technology, semiconductor elements having more than 300 terminals and semiconductor elements having a pad pitch of 80 μm or less have appeared. In particular, it is often found in semiconductor devices used for driving display devices such as ASICs and liquid crystal displays (LCDs) and thermal printer heads (TPHs).

By the way, in order to inspect a semiconductor device,
As shown in FIG. 7, a signal input terminal 71 in the semiconductor element 70
The test probe pins are simultaneously applied to almost all the terminals of the signal output terminal 72 to check the operation of the internal circuit and determine the non-defective product. In this case, the input terminal 71 and the output terminal 72 also serve as inspection terminals. Some semiconductor devices have chips provided with other test pads, which are used to test the operation of a part of the internal circuit. That is, in the conventional semiconductor device structure, when the operation of the internal circuit is inspected, the test probe pins are simultaneously applied to almost all the terminals at the same time to perform the operation check and the pass / fail judgment.

However, as the pad pitch becomes finer and the number of terminals increases as the degree of integration of semiconductor elements increases, the method of using a probe card for inspection cannot be applied. The probe card has about 300 pins and a pitch of 8 due to mechanical and dimensional restrictions of the probe pins.
About 0 μm is the highest level at present. That is, in the case of a multi-terminal, fine-pitch semiconductor element, it was difficult to perform the inspection in the same manner as in the conventional method with the structure of the conventional semiconductor element.

On the other hand, a flat panel display device such as a liquid crystal display device has been attracting attention as a display device which may replace a CRT. Generally, these display devices are provided with a liquid crystal display section formed on a display substrate, hundreds to thousands of signal lines and scanning lines, and a driving IC (integrated circuit) for driving them. Of these, in the display area, the number of pixels is increasing and the pixel pitch is becoming finer for higher definition. Further, in the driving IC, it is required to arrange many (for driving) output terminals at a fine pitch in one driving IC for downsizing and cost reduction, and the number of terminals currently exceeds 200. Drive ICs and drive ICs with a terminal pitch of 100 μm or less have also appeared.

Conventionally, a TAB (Tape Automated Bonding) system has been widely used for connecting the drive IC to the signal line, the scanning line and the like. In the TAB method, an ILB (Inner Lead Bonding) that mounts a drive IC on a tape and an OLB (Oute Lead Bonding) that connects the tape on which the drive IC is mounted and a display substrate
r Lead Bonding) is required, but it is considered that the possible connection pitch is about 100 μm due to the accuracy of the tape carrier and the accuracy of the connection between the tape carrier and the display substrate.

On the other hand, in recent years, a technique for directly connecting a bare drive IC, such as a COG (Chip On Glass) mounting method capable of a finer connection pitch, has been actively developed in recent years. With the COG mounting method, the possible connection pitch is several tens of μm.
Can be made as fine as several μm. COG mounting method is a drive IC
Is connected to the wiring (terminal) on the display substrate as it is, and there are various methods such as using silver paste, using resin, and using low melting point metal.

FIG. 8 shows a conventional liquid crystal display device. The liquid crystal display device 80 includes a liquid crystal display section 82 formed on a display substrate 81, a signal line 83 connected to the liquid crystal display section 82, and a scanning line 84. Further, a drive IC (not shown) is mounted on the display substrate 81 by, for example, the COG method. Then, when the input signal 85 is given to the display substrate 81, the liquid crystal display unit 82 is driven via the drive IC, the signal line 83 and the scanning line 84.

Here, the operation test and the mounting inspection of the drive IC are performed by mounting the drive IC on the display substrate 81 and then applying test probe pins to the display substrate 81 such as around the drive IC. However, in this process, the production of test probe pins is approaching its limit under the present circumstances where the pixel pitch and the terminal pitch of the drive IC are becoming finer. In addition, since it takes time to align the test probe pins, work efficiency is poor, and there is a problem in inspection reliability.

[0011]

As described above, in the conventional inspection of the semiconductor element using the probe card, the number of terminals of the element is about 300, and the terminal pitch is about 80 μm. , Increase in number of terminals,
It was difficult to deal with the fine pitch of terminals. Further, even under the present circumstances, it is difficult to inspect a semiconductor device having a large number of terminals and a fine pitch, resulting in a decrease in reliability and an increase in cost.

In the liquid crystal display device having the conventional structure, when the new COG mounting method is adopted, the driving I
The operation test and mounting inspection of C have become difficult, resulting in a decrease in reliability and an increase in cost.

The present invention has been made in consideration of the above circumstances, and an object thereof is to easily inspect a semiconductor element having a large number of terminals or a semiconductor element having a fine terminal pitch. Another object of the present invention is to provide a semiconductor element which can contribute to improvement in reliability and cost reduction.

Another object of the present invention is to easily carry out an operation test and a mounting inspection of the drive IC, and also an inspection of the liquid crystal display portion, thereby improving reliability and reducing costs. It is to provide a liquid crystal display device that can contribute to the reduction of

[0015]

SUMMARY OF THE INVENTION The essence of the present invention is to form a logic circuit having an output signal to the outside of the semiconductor element as an input signal in the same element in order to facilitate the inspection of the semiconductor element. The output of is the terminal to be inspected. In addition, another gist of the present invention is to facilitate the operation test of the drive IC and the mounting inspection, and further the inspection of the liquid crystal display unit.
A logic circuit having a signal line and a scanning line as an input is formed on a display substrate, and the output is used as an inspection terminal.

That is, according to the present invention (claim 1), an internal circuit formed on a semiconductor substrate and having a predetermined function, an input terminal for applying an input signal from the outside to the internal circuit, and an output from the internal circuit. In a semiconductor device having an output terminal for taking out a signal to the outside, a logic for performing a predetermined logical operation with an output signal of the internal circuit as an input on the same substrate as the internal circuit and reducing the number of outputs with respect to the input A circuit is provided, and a test terminal for taking out the output signal of the logic circuit to the outside is further provided.

The present invention (claim 2) is a liquid crystal display device comprising a liquid crystal display section formed on a display substrate, and a signal line and a scanning line formed on the display substrate. Providing a logic circuit that performs a predetermined logical operation with part or all of the signal lines and scanning lines as inputs and reduces the number of outputs with respect to the inputs, and further provides a test terminal for extracting the output signal of this logic circuit to the outside. It is provided.

Here, the following (1) to (3) are mentioned as preferred embodiments of the present invention (claim 1). (1) The output signal from the internal circuit must be connected to the logic circuit via the output terminal. (2) The logic circuit is placed at a position where it loses its function due to dicing of the semiconductor wafer. (3) Compared with the terminal size or terminal pitch of the output terminal group,
The power supply, control terminal, and inspection terminal are enlarged.

[0019]

According to the present invention, the probe is applied to the input terminal of the semiconductor element to operate the internal circuit, the output signal of the internal circuit is input to the logic circuit, and the calculated signal is read from the inspection terminal. Since the operation test can be performed, it is possible to confirm the operation of the semiconductor element and determine whether the semiconductor element is good or bad without applying probe pins to a large number, sometimes hundreds of output terminals. That is, the operation test can be easily performed only by applying the probe to the input terminal such as the power supply terminal and the control terminal of the semiconductor element and the test terminal corresponding to the output of the logic circuit. Therefore, the size and pitch of the output terminals can be made extremely small as compared with the conventional one, and the semiconductor element can be miniaturized and the number of terminals can be increased. Furthermore, it is not necessary to apply test probe pins to a large number of output terminals, and it is possible to energize and check the operation with about 10 probe pins per chip. This makes it possible to perform burn-in in the wafer state and then determine whether the wafer is good or bad.

By inputting the output signal of the internal circuit to the logic circuit via the output terminal, a normal signal is transmitted to the output terminal to the outside of the semiconductor element which is judged to be non-defective by the inspection. Therefore, the reliability can be further improved. Generally, since the output terminal is located around the semiconductor element, it is easily damaged. However, this structure increases reliability because information on the output terminal can be surely obtained. Furthermore, since the logic circuit is not required during the actual operation of the semiconductor element, the area within the wafer can be effectively utilized by forming the logic circuit on the dicing. Further, by increasing the terminal size and the terminal pitch of the input terminal and the inspection terminal used for the inspection, it becomes possible to easily perform the alignment with the probe.

According to the present invention (claim 2), after the drive IC is mounted on the display substrate, an input signal for driving the display screen is given to the drive IC, and the output from the drive IC is input to the display substrate. The present signal or the signal that has passed through the liquid crystal display unit 82 is taken out, input to the logic circuit and processed. By taking out the processed signal from the inspection terminal, the operation inspection of the drive IC, the mounting inspection and the inspection of the liquid crystal display unit can be performed. At this time, the number of inspection terminals is significantly smaller than the number of terminals of the driving IC (that is, the number of signal lines and the number of scanning lines), so that the inspection is significantly facilitated. In other words, there is no need for a probing test for multiple, sometimes hundreds of signal and scan lines.
The reliability of the inspection is improved and the efficiency is remarkably improved.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic structure of a semiconductor device according to the first embodiment of the present invention. 10 in the figure
Is an internal circuit which is an original functional element, and an input signal A from the outside is given to an input terminal 11 of this internal circuit 10. The output signal B of the internal circuit 10 is transmitted to the output terminal 12, taken out to the outside, and given as an input signal of the logic circuit 20.

The logic circuit 20 performs a logic operation described later, in particular, a logic operation in which the number of outputs is smaller than the number of inputs, and its output signal C is transmitted to the check terminal 21.
Then, the quality of the internal circuit 10 is judged by taking out a signal from the inspection terminal 21 to the outside and monitoring it.

Here, in FIG. 1A, the output signal B is taken out in parallel with the output terminal 12 and used as the input signal of the logic circuit 20. In FIG. 1B, the output signal B is input to the logic circuit 20 via the output terminal 12. The circuits 10, 20 and the terminals 11, 12, 21 are formed on the same wafer.

FIG. 2 shows a specific example of the logic circuit 20 shown in FIG. Here, as a typical logic circuit, as shown in FIG.
2 shows a NOR circuit made up of Qnk, an AND circuit made up of p-channel MOS transistors Qp1 to Qpk in FIG. 2 (b), and an n-channel and p-channel M in FIG. 2 (c).
A circuit including OS transistors Qn1 and Qp2 to Qnk and capable of inspecting a short circuit between adjacent terminals of the output is shown.

Although FIGS. 2A to 2C are shown separately, the signals transmitted to the output terminal 12 of the internal circuit 10 are actually taken out in parallel. Here, output signals 1, 2, ..., K are made to correspond to the respective output terminals. .. k are connected to the gate of the transistor Q and to the source and drain of the transistor Q as shown in FIG. 2 to form a logic circuit. The H voltage and L voltage of the source and drain of the transistor Q are connected from an arbitrary position in the internal circuit 10.

In FIG. 2, an inspection terminal 21 ₁ is provided from the NOR circuit, an inspection terminal 21 ₂ is provided from the AND circuit, and an inspection terminal 21 ₃ is provided from the short circuit inspection circuit. The following (Table 1) shows the inspection results of the inspection terminals 21 _{1 to} 21 ₃ and the quality judgment.

[0029]

[Table 1]

In the NOR circuit of FIG. 2 (a), when the input signal A is given to the internal circuit 10 so that all the output signals 1, 2, ...
When 1 ₁ becomes H, and _one of the output signals 1, 2, ... K malfunctions and becomes H, the inspection terminal 21 ₁ becomes L and it is determined to be defective. Similarly, in the AND circuit of FIG. 2 (b), in the case of normal, when the output signal 1, 2 ... k gave input signal A so that all become H, the inspection terminals 21 ₂ becomes H, 1
If the terminal is abnormal and becomes L, the inspection terminal 21 ₂
Becomes L.

Although the logic circuit is formed by using the p-channel MOS transistor in FIG. 2B, a NAND-type logic circuit is formed by forming a circuit connecting the drain and the source of the transistor using the n-channel MOS transistor. , In this case, when the input signal 1 is given so that the output signals 1, 2, ...
1 ₂ goes to L, and when one terminal is abnormal and goes to L, the inspection terminal 21 ₂ goes to H.

In the short circuit inspection circuit of FIG. 2C, the n-channel MOS transistor is set to L and the p-channel M transistor is set to L.
If the OS transistor is set to H and operates normally, H is output to the inspection terminal 21 ₃ . When there is a short circuit, a voltage calculated from a design value such as the resistance in the circuit is output, and it can be judged by setting the value as a failure threshold value.

In these cases, as can be seen from FIG. 2, even if the internal circuit 10 has 1, 2, ..., K outputs, the number of test terminals of the logic circuit required for the pass / fail judgment is sufficient, and a significant reduction can be achieved. Although only three typical logic circuits are shown in FIG. 2, another logic circuit can be added if necessary. Also, the output signals 1, 2, ... K may be taken out in an arbitrary combination instead of taking them out in order and input to the logic circuit.

FIG. 3 shows an example in which the NOR circuit of FIG. 2A is actually wired. Source, drain, and connected by the shortest route possible the inspection terminals 21 ₁ and the gate. Although only a few are shown in FIGS. 2 and 3, resistors may be provided at various places to connect the circuits to protect them, or a calculated value may be obtained to determine the resistance value of each resistor. Although FIGS. 2 and 3 show the embodiment using the MOS transistor, this may be implemented not only by the MOS transistor but also by using a bipolar transistor. Alternatively, a diode may be used instead of the transistor.

FIG. 4 shows an example in which a logic circuit is constructed using diodes. In FIG. 4A, output signals 1, 2 ...
When the input signal A is applied to the internal circuit 10 so that all k are H, the inspection terminal 21 ₄ is H
When one of the output signals 1, 2, ... K malfunctions and becomes L, the inspection terminal 21 ₄ becomes lower than H by the value of the voltage drop due to the resistance, and it can be determined that there is a defect.

Similarly, in FIG. 4 (b), when the input signal A is applied to the internal circuit 10 so that all the output signals 1, 2, ...
₅ becomes L, and even if one of the output signals 1, 2, ... K malfunctions and becomes H, the inspection terminal 21 ₅ becomes higher than L by the value of the voltage that has flowed in, and it can be determined that there is a defect.

As described above, in this embodiment, the internal circuit 10
Logic circuit 20 which receives the output signal B of
Although a semiconductor device having a new structure provided with the inspection terminal 21 corresponding to the output of 0 is shown, this manufacturing method technically uses the conventional semiconductor manufacturing process although the number of members such as masks and the number of processes may increase slightly. Can be done easily.

As described above, according to this embodiment, the internal circuit 1
By forming the logic circuit 20 having the output signal B of 0 as an input signal in the same chip and taking out and monitoring the output signal C of the logic circuit 20 from the inspection terminal 21, the semiconductor element can be easily inspected. It was That is, the input terminal 11 such as the power supply terminal and the control terminal of the semiconductor element and the logic circuit 2
Only by applying a probe to the inspection terminal 21 corresponding to the output of 0, it is possible to confirm the operation of the semiconductor element without applying probe pins to the many output terminals 12. Therefore, the size and pitch of the output terminals 12 can be made extremely small as compared with the conventional one, and the size and the number of terminals of the semiconductor element can be reduced.

FIG. 5 is a schematic view showing a schematic structure of a semiconductor device according to the second embodiment of the present invention. Although only the structure of one chip is shown in the first embodiment,
In this embodiment, the structure of a wafer having a plurality of chips formed thereon will be described.

An output signal B from the internal circuit 10 or an output from the logic circuit 20 (not shown) of each chip is provided on the wafer 50 on which a plurality of the above-mentioned internal circuits 10 (not shown) are formed. A logic circuit 51 having the signal C as an input is formed, and a test terminal 52 for taking out an output signal C ′ of the logic circuit 51 to the outside is formed. Further, an input terminal 53 for applying an input signal A'from the outside is formed at one place on the wafer 50. Then, in order to branch the input signal A ′ from the input terminal 53 and supply it as the input signal A to the internal circuit 10 of each chip, wiring is formed on the wafer 50.

With such a configuration, by connecting the output signal B of the internal circuit 10 or the output signal C of the logic circuit 20 and connecting the output signal C ′ processed by the logic circuit 51 to the inspection terminal 53, The connection of ten or more points per wafer enables the inspection of the internal circuit 10 in the wafer and the burn-in test in the wafer state. This wiring is particularly effective in a semiconductor device having a high yield.

Regarding the arrangement of the logic circuit 20, even if the logic circuit 20 is provided in the element region, no support is given. However, since the logic circuit 20 is intended for the inspection of the internal circuit 10, after the inspection, that is, the wafer state. Wafer 50 if inspected
It becomes unnecessary after cutting from. Therefore, it is effective to arrange the logic circuit 20 on the dicing line, that is, at a position where the function is lost by dicing, in consideration of effective use of the area in the wafer.

Regarding the size of the terminals used for the inspection, in comparison with the terminal size and the terminal pitch of the output terminals, the size of the input terminals such as the power supply and control terminals and the inspection terminals are generally larger than those of the output terminals. The larger the value, the easier the inspection.

In general, semiconductor terminals have many terminals, and as semiconductor elements are miniaturized, the packaging of semiconductor elements is performed from a conventional resin-molded plastic package or ceramic package.
pe Carrier Package) and mounting methods for directly connecting bare chips such as flip chips are being used. In particular, when a bare chip is mounted, it is difficult to say that the semiconductor element cannot be sufficiently inspected or burned-in and the reliability of the semiconductor element cannot be guaranteed. Therefore, such a semiconductor element structure or wafer structure is adopted. This makes them easy and its effects are tremendous.

FIG. 6 is a view showing the schematic arrangement of a liquid crystal display device according to the third embodiment of the present invention. Here, the active matrix type liquid crystal display device (TFT-
LCD) is shown.

A liquid crystal display portion 62, signal lines 63 and scanning lines 64 are formed on the display substrate 61. The signal lines 63 and the scanning lines 64 form a matrix in the liquid crystal display unit 62. In addition to this, on the display substrate 61, the signal line 63
And a logic circuit 65 having the scan line 64 as an input is formed,
Further, a test terminal 66 for taking out the output signal of the logic circuit 65 to the outside is provided.

In such a structure, the input signal A is given to the display substrate 61. The input signal A is processed so as to drive the liquid crystal display unit 62 and transmitted through the signal line 63 and the scanning line 64. The signals on the signal line 63 and the scanning line 64 are
It is input to the logic circuit 65 formed on the display substrate 62.
The logic circuit 65 can be formed inside or outside the liquid crystal display unit 62 at any place. Various operations are performed in the logic circuit 65. The calculation result is transmitted as the output signal C to the inspection terminal 66. Then, a signal is taken out from the inspection terminal 66 and monitored to determine whether the operation of the drive IC or the mounting of the drive IC, and further the operation of the liquid crystal display device.

The structure of the logic circuit 65 is similar to that described with reference to FIGS. 2 and 3 in the previous embodiment. In the actual inspection, after the drive IC is mounted on the display substrate 61, the input signal A is given to the display substrate 61 and the inspection terminal 6
A probe pin is applied to 6 and the output signal of the logic circuit 65 is monitored. In this case, not only the inspection of the liquid crystal display unit 62 but also the short circuit of the signal line 63 and the scanning line 64 is recognized,
Reliable inspection can be easily performed.

In this embodiment, the driving IC is mounted by the COG mounting method using the low melting point metal. As shown in FIG. 2, the operation and the mounting inspection of the drive IC are performed even if the outputs (the number of signal lines and the number of scanning lines) of the drive IC are 1, 2, ... A significant decrease can be achieved with just the number.

In the embodiment, the case where the drive IC is used in the COG mounting method is shown, but in the case of a liquid crystal display device using, for example, polysilicon or the like, when the drive IC is integrated, the structure of the present invention is obtained. By providing the logic circuit, a liquid crystal display device that can be easily inspected can be realized.

In this embodiment, the logic circuit is formed so as to correspond to the output of each drive IC. However, if the drive IC has few malfunctions and mounting defects, all the signal lines or scanning lines are integrated into one. The inspection is further facilitated by forming the logic circuit.

As described above, the embodiment has shown the liquid crystal display device having a new structure in which the logic circuit 65 which receives the output signal of the driving IC and the inspection terminal 66 which is the output of the logic circuit 65 are provided. Although the number of members such as the above and the number of processes may slightly increase, technically it can be easily performed by using the conventional liquid crystal display device manufacturing process.

Further, the mounting process of the driving IC is generally performed after the cell process, but by using the liquid crystal device of the present invention, it is possible to easily inspect, and when the driving IC is mounted in the cell process, the mounting process is performed. It has become possible to implement with high reliability, such as the constraint conditions are relaxed and the reflow process can be performed. That is, the drive IC is mounted after the rubbing in the cell process and before the bonding of the counter substrate and the liquid crystal injection,
The inspection of the drive IC and the mounting inspection are performed by monitoring the signal from the inspection terminal on the display substrate on which the logic circuit is already formed, so that the mounting conditions are less restricted and the inspection can be facilitated. became. Further, by mounting a drive IC having a high defect occurrence rate at an early stage, damage to a normal portion due to repair can be reduced. This process is also effective as an inspection of the display substrate because the inspection of the display substrate can be performed easily and at a fast stage.

As described above, according to this embodiment, the logic circuit 65 for inputting a part or all of the signal lines 63 and the scanning lines 64 for driving the liquid crystal display section 62 is formed in the display substrate 61, and the logic circuit is formed. By making it possible to perform the inspection with the output of 65, the inspection of the drive IC and the mounting inspection are facilitated. In other words, it becomes possible to perform inspection without applying probe pins to a plurality of terminals, which sometimes drive hundreds of terminals, that drive the display screen, and as a result, the reliability of the inspection can be improved. Moreover, since it is not necessary to connect the signal line 63, the scanning line 64, and the output terminal of the drive IC to the probe pin,
It is also possible to make the pixel pitch and the pitch of the output terminals of the drive IC finer. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0055]

As described above in detail, the present invention (Claim 1)
According to the above, a logic circuit having an output signal to the outside of the semiconductor element as an input signal is formed in the same substrate, and the output of the logic circuit is used as the terminal to be inspected. Even a semiconductor element can be easily inspected, and it is possible to realize a semiconductor element that can contribute to improvement in reliability and cost reduction.

Further, according to the present invention (claim 2), since the logic circuit having the signal line and the scanning line as the input is formed on the display substrate and the output thereof is used as the inspection terminal, the operation test of the drive IC is performed. The mounting inspection and the liquid crystal display unit inspection can be easily performed, and it is possible to realize a liquid crystal display device that can contribute to improvement in reliability and cost reduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention,

FIG. 2 is a circuit diagram showing a specific configuration example of a logic circuit in FIG.

3 is a circuit diagram showing an example in which the NOR circuit in FIG. 2 is actually wired,

FIG. 4 is a circuit diagram showing an example in which the logic circuit in FIG. 1 is composed of diodes.

FIG. 5 is a diagram showing a schematic configuration of a semiconductor device according to a second embodiment,

FIG. 6 is a diagram showing a schematic configuration of a liquid crystal display device according to a third embodiment,

FIG. 7 is a diagram showing a schematic configuration of a conventional semiconductor device,

FIG. 8 is a diagram showing a schematic configuration of a conventional liquid crystal display device.

[Explanation of symbols]

10 ... Internal circuit, 11 ... Input terminal, 12 ... Output terminal, 20 ... Logic circuit, 21 ... Inspection terminal, 21 ₁ ... Inspection terminal (NOR circuit), 21 ₂ ... Inspection terminal (AND circuit), 21 ₃ ... Inspection terminal (Short-circuit inspection circuit), 21 ₄ ... Inspection terminal (AND circuit), 21 ₅ ... Inspection terminal (OR circuit), A ... Input signal, B ... Output signal (output signal from internal circuit 10), C ... Output signal ( Output signal from the logic circuit 20).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (2)

[Claims] 1. An internal circuit formed on a semiconductor substrate and having a predetermined function, an input terminal for applying an external input signal to the internal circuit, and an external output signal from the internal circuit. An output terminal, a logic circuit formed on the same substrate as the internal circuit, performing a predetermined logical operation with the output signal of the internal circuit as an input, and reducing the number of outputs with respect to the input, and an output signal of this logic circuit A semiconductor element comprising: an inspection terminal for taking out the semiconductor device to the outside. 2. A liquid crystal display unit formed on a display substrate, a signal line and a scanning line formed on the substrate, and part or all of the signal line and the scanning line formed on the substrate are input. A liquid crystal display device comprising: a logic circuit for performing a predetermined logic operation to reduce the number of outputs with respect to an input; and a test terminal for taking out an output signal of the logic circuit to the outside.