JPH05260434A - Picture recorder - Google Patents

Abstract

PURPOSE:To easily and optionally obtain a delay of a constant delay time with a secular drift and a temperature drift eliminated therefrom by delaying a synchronizing signal digitally in the unit of clocks. CONSTITUTION:A synchronizing signal delay circuit 5 arranged to an input section of a PLL circuit 16 synchronizing a sampling clock of an A/D converter 3 and a D/A converter 12 with an input signal is made up of a programmable counter counting a delay set by a 1st D flip-flop receiving a horizontal synchronizing signal separated from the input signal and a 2nd D flip-flop obtaining a synchronizing signal delayed from the input signal by a delay T1 while receiving a signal of a count output as a clock input to obtain a constant delay in the unit of clocks digitally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording apparatus configured to convert an analog video signal into a digital video signal, store the digital video signal in a recording medium, and convert the stored digital video signal into an analog signal video for output. It is about.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional image recording apparatus. In FIG. 4, 1 is a signal input terminal of a composite video signal, and 2 is a composite video signal input to a signal input terminal 1 and a luminance signal and a color. A video signal processing circuit including a separation circuit for separating a color signal into a signal and a demodulation circuit for demodulating a color signal into a color difference signal;
Is an A / D converter that converts an analog video signal output from the video signal processing circuit 2 into a digital video signal, and the converted digital video signal is written in a recording medium 30 such as a field memory. Reference numeral 4 is a sync separation circuit for separating the sync signal from the composite video signal, and 5 is a sync signal delay circuit for delaying the sync signal.

Reference numeral 6 is a frequency divider, 7 is a phase comparator for comparing the phases of the synchronizing signal and the output signal of the frequency divider 6, 8 is an LPF (low-pass filter), and 9 is a VCO.
The PLL circuit 16 is configured by each unit of 9.

Reference numeral 10 denotes the output signal of the synchronous delay circuit 5 and the PLL.
A sync signal generation circuit for inputting the output signal of the circuit 16 to generate a sync signal, 12 a D / A converter for converting a digital video signal read from the recording medium 30 into an analog video signal, and 13 a D / A A sync signal adding circuit for adding a sync signal to the analog video signal from the converter 12 is a color modulation circuit 14 for outputting the output signal of the sync signal adding circuit 13 to the signal output terminal 15 as a decoded video signal.

The signal converted into a digital video signal by the A / D converter 3 and written in the recording medium 30 is a video blanking signal including a sync signal portion of the composite video signal in consideration of the recording capacity and the efficiency at the time of quantization. It is general that only the image data excluding the copy is sampled and stored in the recording medium 30.

In this case, the sync signal passes through the sync separation circuit 4 and is separated from the video signal portion in advance, and the D / A converter 1
2 is added to the analog video signal output from the synchronization adding circuit 13
Will be added again at.

In such a configuration, the delay amount of the analog video signal generated in the video signal processing circuit 2 is different from the delay amount of the sync signal generated in the sync signal circuit section by the sync separation circuit 4 and the sync signal generation circuit 10. The position of the synchronizing signal added to the output signal is different from the position of the original synchronizing signal of the input signal, and in the case of image display, the horizontal phase shifts.

As means for correcting this time difference, conventionally, as shown in the figure, a sync signal delay circuit 5 is provided between the sync separation circuit 4 and the sync signal generation circuit 10 to provide a delay element such as a delay line or a monostable circuit. The delay amount is corrected by using a multi-bubbler, and the corrected synchronizing signal is added to the analog video signal output from the D / A converter 12.

FIG. 5 is a block diagram showing a synchronizing signal delay circuit 5 using a monostable multivibrator, and its operation will be described with reference to the waveform diagram of FIG.

When a negative horizontal synchronizing signal shown in FIG. 6A is input to the input section of the first monostable multivibrator 22 from the input terminal 27, the first monostable multivibrator 22 rises to the input signal. A pulse having a time T2 determined by the time constant of the variable resistor 26 and the capacitor 21 which starts from the downward edge, that is, the signal having the waveform shown in FIG. 6B is output.

The signal having the waveform shown in FIG. 6B is the second
Is input to the input unit of the monostable multivibrator 25. The second monostable multivibrator 25 outputs a negative pulse corresponding to the horizontal synchronizing signal width determined by the resistor 23 and the capacitor 24, that is, a signal having a waveform shown in FIG. 6C. As a result, it is possible to generate a horizontal synchronizing signal that is delayed by the delay amount T2 from the input synchronizing signal. The time of the delay amount T2 can be freely set by adjusting the variable resistor 26.

[0012]

Since the conventional image recording apparatus is constructed as described above, for example, the change over time and the temperature of the variable resistor and the capacitor used as a time constant for determining the delay amount. There is a problem that the delay time changes due to drift or the like.

Further, R. G. When inputting and switching various kinds of signals such as B signal or Y / C separated signal, each signal processing circuit is different, so the synchronization delay time must be set individually, and a changeover switch is used. Therefore, there is a problem that an extra circuit element for switching the time constant is required.

The invention of claim 1 has been made to solve the above-mentioned problems, and the delay of the synchronizing signal is digitally performed in clock units using a counter, and is constant without drift. The purpose is to be able to obtain the amount of time delay.

According to a second aspect of the present invention, the initial set value of the counter can be set for each mode, and the third aspect of the present invention facilitates fine adjustment of the initial set value from the outside by using an external operation key. An object is to obtain an image recording device that can be performed.

[0016]

According to another aspect of the present invention, there is provided an image recording apparatus comprising a sync signal delay circuit arranged at an input portion of the PLL circuit for correcting a delay amount of an analog video signal. An A / D converter that converts the analog video signal into a digital video signal, a first D-flip-flop that latches with a sampling clock of the D / A converter that converts the digital video signal into an analog video signal, and The counter is composed of a counter that counts the amount of delay with the sampling clock, and a second D-flip-flop that generates a delayed synchronization signal based on the signal delayed by the counter.

The invention of claim 2 makes it possible to control the initial set value of the counter, and the invention of claim 3 makes it possible to finely adjust the initial set value from the outside.

[0018]

According to the first aspect of the present invention, the delay amount of the synchronizing signal is determined by the digital circuit by counting the sampling clock generated by the PLL circuit by the counter and controlling the sampling clock by the clock unit. It is possible to obtain a stable delay amount without any drift or radial drift.

According to the invention of claim 2, the delay amount can be arbitrarily set and controlled by controlling the initial set value of the counter. According to the invention of claim 3, the above-mentioned initial value is set. Since the set value can be changed from the outside, the position of the screen can be adjusted while watching the output screen.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1 in which the same parts as those of the conventional device shown in FIG. 4 are designated by the same reference numerals and duplicate description is omitted, the oscillation frequency of the VCO 9 in the PLL circuit 16 is 910 fH = 4f.
sc is used. The output signal of the PLL circuit 16 is also used as the sampling clock of the A / D converter 3 and the D / A converter 12, and the video signal digitally converted by the A / D converter 3 is stored in the recording medium 30. To do. The sync signal generation circuit 10 generates various sync signals such as a subcarrier signal, a horizontal signal, and a vertical signal based on the 4fsc signal using the delayed horizontal sync signal as a reset signal.

Further, D / read from the recording medium 30
The analog signal converted by the A converter 12 passes through the sync signal adding circuit 13, and the sync signal generated by the sync signal generating circuit 10 is added to the image BLK portion of the luminance signal,
After being converted into a composite video signal by the color modulation circuit 14, it is output from the signal output terminal 15.

Here, the composite video signal input to the signal input terminal 1 is separated in horizontal and vertical sync by the sync separation circuit 4, and only the horizontal sync signal is input to the sync signal delay circuit 5.

FIG. 2 is a block diagram showing an example of the synchronizing signal delay circuit 5, and FIG. 3 is a signal waveform diagram of each part of FIG.
2 and 3, the first D-flip-flop 17
3 input from the data input part 28 of FIG.
The negative sync signal shown in (A) is first latched by the clock of 4 fsc. Then, the first D-flip-flop 17 outputs from the terminal Q a positive pulse having substantially the same width as the input. This pulse is the second D-
It is input to the flip-flop 18 and the programmable counter 19 as a counter. The programmable counter 19 counts from the value initially set by the CPU 11 as the initial setting means based on the clock of 4 fsc, and when the programmable counter 19 completes the set number of counts, the negative electrode shown in FIG. 1 clock width pulse is generated. By inputting this signal to the clock input terminal of the second D-flip-flop 18, the inverted Q output terminal of the second D-flip-flop 18 is changed from High to Low in synchronization with its rising edge.
Change to. After this, the first D-flip-flop 17
By changing the signal of the Q output terminal of the above from High to Low, the inverting Q output terminal of the second D-flip-flop 18 changes from Low to High again. As a result, the inverted Q output terminal generates a signal having the waveform shown in FIG. The signal having the waveform shown in FIG. 3C is a signal obtained by delaying the falling edge of the input signal by the time T1.

The signal having the waveform shown in FIG. 3 (C) is designed to generate an error signal by comparing the falling edges with the phase comparator 7 of the PLL circuit 16 at the next stage.
It becomes possible to add a synchronization signal including a delay amount of T1 to the output signal.

Here, the delay time T1 is based on a value initially set by the CPU 11 and is programmable counter 19
Therefore, the delay time can be freely set in units of one clock width by changing the initial setting value of the CPU 11.

Further, by connecting an external operation key input section 31 as an externally operable operation means to the CPU 11, the user can externally set the delay amount of the horizontal synchronizing signal arbitrarily. The horizontal position can be changed while monitoring the output signal.

Although the 4 fsc signal synchronized with the input signal is used as a clock in the above embodiment, the count number in the programmable counter circuit and the movement amount of 1 clock are arbitrarily set by changing the frequency. be able to.

[0028]

As described above, according to the first aspect of the invention, the synchronizing signal for adjusting the delay amount of the video signal is digitally performed in clock units, and the delay amount can be set arbitrarily. With this configuration, it is possible to remove the temperature drift and the radial drift that occur in the delay circuit and to easily set and adjust the delay amount.

According to the second aspect of the invention, since the count number is initialized in the counter for counting the sampling clock, the delay amount can be arbitrarily set and controlled. According to the invention of claim 3, the initial setting can be changed from the outside, so that there is an effect that the position of the angle of view can be adjusted while observing the output screen.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image recording apparatus according to an embodiment of the present invention.

2 is a block diagram of a synchronization signal delay circuit in the image recording apparatus of FIG.

FIG. 3 is a signal waveform diagram of each part of the circuit of FIG.

FIG. 4 is a block diagram showing a conventional image recording apparatus.

5 is a block diagram of a synchronization signal delay circuit in the image recording apparatus of FIG.

6 is a signal waveform diagram of each part of the circuit of FIG.

[Explanation of symbols]

 3 A / D converter 5 Synchronous signal delay circuit 11 CPU 14 D / A converter 16 PLL circuit 17 First D-flip flop 18 Second D-flip flop 19 Programmable counter 31 External operation key input section

Claims (3)

[Claims] 1. An A / D converter for converting an analog video signal, which is an input signal, into a digital video signal, a recording medium for storing the digital video signal, and the digital video signal for storage in the recording medium as the analog signal. An image recording apparatus having a D / A converter for converting into an image signal, and a PLL circuit for synchronizing the sampling clock of the A / D converter and the D / A converter with the input signal, A synchronization signal delay circuit provided in the input part of the PLL circuit for correcting the delay amount, a first D-flip-flop for latching the synchronization signal at the sampling clock, and the delay amount by the D / A A counter that counts with a sampling clock of the converter and the A / D converter, and a delay synchronization signal is generated based on the signal delayed by the counter. An image recording apparatus comprising a second D-flip-flop and digitally delaying the synchronizing signal. 2. An A / D converter for converting an analog video signal as an input signal into a digital video signal, a recording medium for storing the digital video signal, and the digital video signal stored in the recording medium for the analog signal. An image recording apparatus comprising a D / A converter for converting into a video signal and outputting the image signal, and a PLL circuit for synchronizing a sampling clock of the A / D converter and the D / A converter with the input signal. A synchronization signal delay circuit arranged at the input of the PLL circuit for correcting the delay amount of the video signal;
First to latch a synchronization signal with the sampling clock
Second D-flip-flop, a counter that counts the delay amount with the sampling clock, and a delay synchronization signal that is generated based on the signal delayed by the counter.
2. An image recording apparatus comprising: the D-flip flop and the initial setting means for initially setting the count number in the counter and arbitrarily setting and controlling the delay amount. 3. An A / D converter for converting an analog video signal which is an input signal into a digital video signal, a recording medium for storing the digital video signal, and the digital signal stored in the recording medium for the analog video. D / A converter for converting into a signal and outputting the signal, the A / D converter and the D / A converter
In an image recording apparatus having a PLL circuit for synchronizing a sampling clock of an A converter with the input signal, the PL for correcting the delay amount of the analog video signal.
A first D- circuit for latching a synchronization signal with the sampling clock by a synchronization signal delay circuit provided at the input part of the L circuit.
A flip-flop, a counter that counts the delay amount with the sampling clock, and a second D- that generates a delay synchronization signal based on the signal delayed by the counter.
An image characterized by comprising a flip-flop, initial setting means for initially setting the count number in the counter, and operating means capable of externally operating the initial setting means to arbitrarily set and control the delay amount. Recording device.