JPH05259383A - Semiconductor capacity device - Google Patents

Abstract

PURPOSE:To form a small capacitor of an integrated circuit with high accuracy. CONSTITUTION:An N<+> diffusion layer 4 is formed on the surface of an N-type epitaxial layer 5 where an insulation film 3 is formed on the surface. Electrodes 1 and 2 are further formed on the surface. Assuming that the capacitances of capacitive elements C1 and C2 are identical, the combined capacitance of the capacitors connected in serial is half of the capacitance of each capacitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive element formed in an integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 is a plan view of a conventional example of an insulating film capacitor in which a metal film serving as one electrode of a capacitor is formed on the surface of the integrated circuit via an insulating film. FIG. 4 is a schematic cross-sectional view of the integrated circuit including the BB ′ cross section of the capacitive element shown in FIG.

As shown in FIGS. 3 and 4, N ⁺ is formed in, for example, an N type epitaxial layer 5 isolated from the surroundings.
The diffusion layer 4 is formed, and the insulating film 3 is formed on the surface thereof. A hole is opened in this insulating film 3 and one terminal 6 of the capacitive element is taken out from the N ⁺ diffusion layer 4. Then, the other terminal of the capacitive element is taken out from the electrode 1 on which the metal is vapor-deposited via the insulating film 3. The capacitive element is formed by the electrode 1, the N ⁺ diffusion layer 4 corresponding to the electrode 1, and the insulating film 3 sandwiched therebetween. The capacitance value is roughly determined by the film thickness of the insulating film 3, its dielectric constant and the area of the electrode 1. Since the film thickness and the dielectric constant of the insulating film 3 are substantially determined by the semiconductor process used, in the pattern design, it is designed to a desired value by setting the area of the electrode 1.

[0004]

In the conventional capacitive element as described above, an extremely small capacitance, for example, 1 pF.
When attempting to form the following capacitance, it is necessary to set the area of the electrode 1 to be extremely small. A metal film to be an electrode formed in an integrated circuit is usually formed by vapor deposition and is formed into a predetermined shape by etching, but its area is varied due to variations in etching. If an electrode having a sufficiently large area is used against the variation in etching, this variation in etching does not pose a problem, but in order to form a capacitance of 1 pF or less, the area of the electrode needs to be set to be extremely small. Therefore, a large variation occurs.

[0005]

In the present invention, two or more capacitive elements are connected in series on a semiconductor substrate to form a desired capacitance value. In addition, a plurality of electrodes are provided above the same diffusion region via an insulating film to connect these capacitive elements in series.

[0006]

According to the present invention, when forming a very small insulating film capacitance, by connecting two or more capacitive elements in series, the area of each metal vapor deposition film can be increased, and Variation in capacitance value due to variation during etching of a vapor deposition film is reduced. Also, by providing multiple metal evaporated film electrodes on top of the same diffusion region and connecting them in series, the same diffusion region becomes a common electrode, so avoid increasing the area of the capacitive element more than necessary and increase the capacitance value. It is possible to reduce variations.

[0007]

1 is a plan view of an embodiment of the present invention, and FIG. 2 is a schematic cross sectional view of an integrated circuit including a cross section AA 'of the capacitive element shown in FIG.

In FIGS. 1 and 2, N ⁺ is formed on the surface of the N type epitaxial layer 5 which is separated from the surroundings as in the conventional example.
The diffusion layer 4 is formed. An insulating film 3 is formed on the surface, and electrodes 1 and 2 are further formed on the surface. First
The capacitive element C1 is formed between the electrode 1 and the N ⁺ diffusion layer 4 with the insulating film 3 interposed therebetween. Similarly, the second capacitive element C2 is also formed between the electrode 2 and the N ⁺ diffusion layer 4 with the insulating film 3 interposed therebetween. Since the two capacitive elements C1 and C2 share the N ⁺ diffusion layer 4, the wiring is taken out from the respective electrodes 1 and 2 of the capacitive elements C1 and C2, so that the capacitive elements C1 and C2 are automatically Capacitive elements connected in series are formed.

Let C be the capacitance value connected in series, and C1
When the capacitance values of C2 and C2 are c1 and c2, respectively, c = (c1 * c2) / (c1 + c2) ... (1)

For example, if c1 = c2, then c = c1 × 1/2 (2)

As described above, the capacitance value is determined by the electrodes 1 and 2.
Is mainly determined by the area of the electrode, and the smaller the area of the electrode, the greater the variation due to etching of the electrode. Therefore, in this embodiment of the present invention, in the case of the formula (2), a half capacitance value can be realized with the same variation.

Further, the area of the electrode of each capacitance element can be set large by connecting a plurality of capacitance elements not only in the same diffusion region but in different diffusion regions in series. Variation in capacitance value can be reduced as compared with a capacitive element to be formed. Moreover, when two capacitive elements are formed in the same diffusion region, the terminal 6 of one electrode taken out from the N ⁺ diffusion layer 4 is not required, so that there is no large area loss.

[0013]

As described above, according to the present invention, in a capacitive element using an insulating film in an integrated circuit, a plurality of capacitors are connected in series to set a large electrode area,
It is possible to reduce variations due to etching of the metal vapor deposition film during electrode formation. Further, by forming two capacitive elements in the same diffusion region and making one terminal of the electrode of each capacitive element common to the same diffusion region, it is possible to prevent the area expansion more than necessary.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention.

FIG. 3 is a plan view of a conventional example.

FIG. 4 is a schematic cross-sectional view of a conventional example.

[Explanation of symbols]

1, 2 electrodes 3 insulating film 4 N ⁺ diffusion layer 5 N type epitaxial layer

Claims (2)

[Claims] 1. A semiconductor capacitor element, comprising: connecting two or more capacitors having electrodes formed on the surface of a semiconductor substrate via an insulating film in series to form a desired capacitance value. 2. The semiconductor capacitive element according to claim 1, wherein a plurality of electrodes are provided above the same diffusion region on the surface of the semiconductor substrate via an insulating film.