JPH05259336A - Resin-sealed semiconductor device - Google Patents

Abstract

PURPOSE:To provide a low-cost resin-sealed semiconductor device in which parasitic inductance and parasitic capacitance are reduced. CONSTITUTION:A resin-sealed semiconductor device includes a semiconductor chip 2, and leads 1 connected with the chip through bonding wires 3. The lead receives the chip at its portion 1c, and it is connected through the wire with the chip surface at their bonding points at substantially the same level. The surface of the chip is coated with fluororesin 4, whose dielectric constant is lower than the molding epoxy resin 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device, and more particularly to a resin-encapsulated semiconductor device used in a high frequency band from the quasi-microwave band to the microwave band or higher.

[0002]

2. Description of the Related Art Generally, when a FET (field effect transistor) semiconductor chip as a semiconductor chip used in a high frequency band such as a microwave band is packaged, the material surrounding the chip and the shape of the container housing the chip. As a result, the parasitic inductance and parasitic capacitance to the chip change significantly. Therefore, the material used for the package and the shape of the package have a great influence on the high frequency performance of the chip. Therefore, in order to bring out the performance of the FET semiconductor chip sufficiently, it is necessary to use a package in which the parasitic inductance and the parasitic capacitance are as small as possible.

In order to suppress the above parasitic inductance and parasitic capacitance, a semiconductor device employing a ceramic package shown in FIG. 2 is usually used. As shown in FIG. 2, in the ceramic package, the conductive leads 31 are connected to the ceramic substrate 36, and the semiconductor chip 3
2 through the metallized layer 34 to the ceramic substrate 3
6 is bonded to the semiconductor chip 32 with the gold wire 33.
The lead terminal 31 and the ceramic substrate 36.
Has a hollow sealing structure in which the upper end of is sealed with a metal cap 38.

In the above ceramic package, since the dielectric constant and the dielectric loss of the ceramic substrate 36 made of ceramic are smaller than that of the resin used in the usual resin package and the hollow structure is formed, the parasitic impedance is low. This is advantageous for improving the high frequency characteristics of the semiconductor chip 32. That is, the semiconductor device employing the ceramic package has advantages such as a reduced noise figure, improved power gain, and suppressed phase rotation of input / output impedance. However, the above ceramic package
It has the drawback of being very expensive compared to resin packages.

Therefore, conventionally, in order to suppress the package price, a semiconductor device using a package sealed with an epoxy resin, which is significantly cheaper than the above ceramic package, has been used. FIG. 3 is a plan view showing the structure of an epoxy resin-sealed semiconductor device that employs the epoxy resin-sealed package. In FIG. 3, 41
Reference numerals a, 41b and 41c are lead terminals, 42 is an FET semiconductor chip, 43 is a gold wire, and 45 is an epoxy sealing resin.
A manufacturing process of the resin-sealed package of the epoxy resin-sealed semiconductor device will be described with reference to FIGS. 4A to 4D which are cross-sectional views. First, as shown in FIG. 4A, the FET semiconductor chip 52 is placed at a predetermined position on the lead terminal 51 by Ag.
Bond (die bond) with paste. Next, as shown in FIG. 4B, each electrode of the chip 52 and the lead terminal 51 are electrically connected by a gold wire 53.

Next, the lead terminal 51 to which the chip 52 and the gold wire 53 are attached is put into a mold having a desired shape,
This mold is filled with epoxy sealing resin to form a package outer shape as shown in FIG. 4 (C).
5 is formed. Next, as shown in FIG. 4D, the lead terminals 51 are cut and processed into a predetermined shape to complete an epoxy resin-sealed semiconductor device.

[0007]

By the way, the conventional epoxy resin-encapsulated semiconductor device shown in FIG. 4 (D) has excellent mechanical strength and airtightness, and is much cheaper than ceramics. Since epoxy resin is used, the material cost is low, but since the epoxy encapsulation resin 55, which has a higher dielectric constant (about 4.0) than ceramics, directly covers the semiconductor chip 52, a ceramic package was adopted. There is a problem that the parasitic capacitance becomes significantly larger than that of the semiconductor device.

Further, since the lower surface of the semiconductor chip 52 is adhered onto the flat lead terminal 51 and the upper surface of the semiconductor chip 52 and the flat lead terminal 51 are connected by the gold wire 53, the semiconductor chip. There is also a problem that the thicker the thickness between the upper surface and the lower surface of 52, the longer the gold wire 53 and the larger the parasitic inductance.

Therefore, in the conventional resin-encapsulated semiconductor device described above, the noise figure and the power gain are significantly deteriorated in the high frequency region, and the phase rotation of the input / output impedance of the in-chip element is greatly increased. There is a drawback that the performance of can not be fully brought out.

Therefore, an object of the present invention is to provide a resin-sealed semiconductor device capable of suppressing parasitic inductance and parasitic capacitance.

[0011]

In order to achieve the above object, the present invention provides a semiconductor chip, a lead terminal to which the semiconductor chip is die-bonded, and a bonding wire connecting the semiconductor chip and the lead terminal. In the resin-sealed semiconductor device sealed with resin, the upper surface of the semiconductor chip to which one end of the bonding wire is connected and the wire connection surface of the lead terminal to which the other end of the bonding wire is connected are substantially on the same plane. To be located in
It is characterized in that a semiconductor chip accommodating step portion is formed on the lead terminal.

Further, it is desirable that the surface of the semiconductor chip is coated with a resin having a lower dielectric constant than the resin used for the resin sealing.

[0013]

Operation: The lower surface of the semiconductor chip is die-bonded to the semiconductor chip housing step formed on the lead terminal, and the upper surface of the semiconductor chip to which one end of the bonding wire is connected and the lead to which the other end of the bonding wire is connected. The wire connection surface of the terminal was located on substantially the same plane. Therefore, no matter what value the thickness of the semiconductor chip is, the step between the upper surface of the semiconductor chip and the wire connection surface of the lead terminal can be substantially eliminated, and the length of the bonding wire can be reduced. Be minimized. Therefore,
Parasitic inductance to the semiconductor chip is suppressed,
The noise figure and power gain of the semiconductor chip in the high frequency region are improved, and the phase rotation of the input / output impedance of the semiconductor chip in the high frequency region is reduced. That is, according to the present invention, a resin-encapsulated semiconductor device with improved high frequency characteristics is realized.

When the surface of the semiconductor chip is coated with a resin having a dielectric constant lower than that of the resin used for the resin encapsulation, parasitic capacitance to the semiconductor chip is suppressed and high frequency characteristics of the semiconductor chip are improved. , Further improved.

[0015]

Embodiments of the present invention will be described in detail below with reference to the embodiments shown in the drawings.

A process of manufacturing an epoxy resin-sealed semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1 (A), a lead terminal 1 to which a semiconductor chip is die-bonded is taken as A- in FIG. 1 (A).
Cut at the A side. Next, as shown in FIG. 1B, one side 1b of the cut lead terminal 1 is bent by a forming die to form a semiconductor chip housing step 1c. During the bending process, the semiconductor chip accommodation step 1c is processed so that the depth of the semiconductor chip accommodation step 1c is approximately the same as the thickness of the semiconductor chip die-bonded to the accommodation step 1c.
For example, when the thickness of the semiconductor chip is 0.15 mm, the depth of the semiconductor chip housing step 1c is 0.14 to
Bending is performed so that it becomes about 0.16 mm.

Next, as shown in FIG. 1C, the lower surface of the microwave band FET semiconductor chip 2 is die-bonded to the semiconductor chip housing step 1c with Ag paste, and then the upper surface of the semiconductor chip 2 is covered. A gold wire 3 connects between each electrode and the lead terminals 1a and 1b.

Next, as shown in FIG. 1D, a resin 4 having a low dielectric constant is coated on the upper surface of the semiconductor chip 2.
As the resin 4, polyimide, fluorine resin, or the like having a dielectric constant of about 2 to 3 and a dielectric constant lower than that of an epoxy resin used for resin sealing is used.

Next, as shown in FIG. 1 (E), an epoxy encapsulation resin that forms an outer shape of the resin encapsulation package by a transfer molding method using an epoxy resin having excellent mechanical strength and reliability as an encapsulation material. 5 is formed. After this,
As shown in FIG. 1 (F), the epoxy encapsulation resin 5 forming the resin encapsulation package is inverted, and the lead terminals 1a and 1b protruding from the package are cut and bent into a desired shape.

In the thus manufactured epoxy resin-sealed semiconductor device, the depth of the semiconductor chip accommodating step portion 1c of the lead terminal 1 is set to be approximately the same as the thickness of the semiconductor chip 2. The upper surface of the wire 2 and the wire connecting surface of the lead terminal 1 to which the gold wire 3 is connected can be positioned substantially on the same surface. Therefore, the step between the upper surface of the semiconductor chip 2 and the wire connection surface of the lead terminal 1 can be substantially eliminated, and the length of the gold wire can be minimized. Therefore, the parasitic inductance to the semiconductor chip 2 can be suppressed, the noise figure and power gain of the semiconductor chip 2 in the high frequency region can be improved, and the phase rotation of the input / output impedance of the semiconductor chip 2 in the high frequency region can be reduced. be able to. That is, according to the above-described embodiment, it is possible to realize an inexpensive resin-sealed semiconductor device having excellent high frequency characteristics.

Further, since the upper surface of the semiconductor chip 2 is coated with the resin 4 having a low dielectric constant such as polyimide or fluorine resin having a lower dielectric constant than the epoxy sealing resin 5 used for resin sealing, the semiconductor chip 2 is The parasitic capacitance to the semiconductor chip 2 can be suppressed, and the high frequency characteristics of the semiconductor chip 2 can be further improved.

In the above embodiment, the FE for microwave band is used.
The resin-encapsulated semiconductor device including the T semiconductor chip has been described. However, the present invention is directed to a diode, MMIC (microwave monolithic device) used in the quasi-microwave band or higher.
It can also be applied to a semiconductor device including a semiconductor chip having an integrated circuit).

[0024]

As is apparent from the above description, in the resin-sealed semiconductor device of the present invention, a semiconductor chip, a lead terminal to which the semiconductor chip is die-bonded, and the semiconductor chip and the lead terminal are connected. In the resin-sealed semiconductor device in which the bonding wire and
A wire of a lead terminal to which the lower surface of the semiconductor chip is die-bonded to the semiconductor chip housing step formed on the lead terminal, and the upper surface of the semiconductor chip to which one end of the bonding wire is connected and the other end of the bonding wire are connected. The connection surface and the connection surface were located on substantially the same plane. Therefore, no matter what the thickness of the semiconductor chip is,
The step between the upper surface of the semiconductor chip and the wire connection surface of the lead terminal can be substantially eliminated, and the length of the bonding wire can be minimized. Therefore, parasitic inductance to the semiconductor chip can be suppressed, the noise figure of the semiconductor chip in the high frequency region,
The power gain can be improved, and the phase rotation of the input / output impedance of the semiconductor chip in the high frequency region can be reduced. Therefore, according to the present invention, an inexpensive resin-sealed semiconductor device having excellent high frequency characteristics can be realized.

When the surface of the semiconductor chip is coated with a resin having a dielectric constant lower than that of the resin used for the resin encapsulation, the parasitic capacitance to the semiconductor chip is suppressed and the high frequency characteristics of the semiconductor chip are improved. Especially it can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of an embodiment of a resin-sealed semiconductor device of the present invention.

FIG. 2 is a sectional view of a semiconductor device packaged in a ceramic package.

FIG. 3 is a plan view of a conventional epoxy resin-sealed semiconductor device.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the conventional resin-encapsulated semiconductor device.

[Explanation of symbols]

1,1a, 1b Lead terminal 2 FET semiconductor chip 3 Gold wire 4 Low dielectric constant resin 5 Epoxy encapsulation resin

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 23/28 A 8617-4M 23/29 23/31

Claims (2)

[Claims] 1. A resin-sealed semiconductor device in which a semiconductor chip, a lead terminal to which the semiconductor chip is die-bonded, and a bonding wire connecting the semiconductor chip and the lead terminal are resin-sealed, wherein the bonding is performed. The semiconductor chip accommodating step portion is provided on the lead terminal so that the upper surface of the semiconductor chip to which one end of the wire is connected and the wire connecting surface of the lead terminal to which the other end of the bonding wire is connected are located substantially on the same plane. A resin-encapsulated semiconductor device comprising: 2. The resin-encapsulated semiconductor device according to claim 1, wherein the surface of the semiconductor chip is coated with a resin having a dielectric constant lower than that of the resin used for the resin encapsulation.