JPH05259328A - Semiconductor module - Google Patents

Semiconductor module

Info

Publication number
JPH05259328A
JPH05259328A JP2486793A JP2486793A JPH05259328A JP H05259328 A JPH05259328 A JP H05259328A JP 2486793 A JP2486793 A JP 2486793A JP 2486793 A JP2486793 A JP 2486793A JP H05259328 A JPH05259328 A JP H05259328A
Authority
JP
Japan
Prior art keywords
layer
semiconductor module
iso4
heat dissipation
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2486793A
Other languages
Japanese (ja)
Other versions
JP3338495B2 (en
Inventor
Eckhard Wolfgang
ウオルフガング エクハルト
Reinhold Kuhnert
クーネルト ラインホルト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
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Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH05259328A publication Critical patent/JPH05259328A/en
Application granted granted Critical
Publication of JP3338495B2 publication Critical patent/JP3338495B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3732—Diamonds
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
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    • H01L23/4928—Bases or plates or solder therefor characterised by the materials the materials containing carbon
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    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Abstract

PURPOSE: To provide a semiconductor module in which thermal contact resistance between a semiconductor chip and a heat sink is extremely decreased, as compared with that of a conventional semiconductor module by ensuring sufficient insulation between the semiconductor chip and the heat sink. CONSTITUTION: An electrically insulation and thermally conductive crystalline carbon layer ISO2 is provided between a semiconductor chip CHIP2 and a heat sink W2. A semiconductor chip, an insulation layer, an intermediate layer Z2 and the heat sink W2 are bonded by pressure-sintering via bond layers V21,..., V23. An amorphous carbon layer is substituted for the crystalline carbon layer in the case of low-voltage application.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は高い絶縁性と熱伝導性を
示す半導体モジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module having high insulation and thermal conductivity.

【０００２】[0002]

【従来の技術】半導体チップと熱放出装置との間に電気
絶縁性で熱伝導性である層を有する形式の半導体モジュ
ールは例えば１９９０年２月２０日〜２２日フェルバッ
ハで行われた「エレクトロニクスにおける接合技術（Ｖ
ｅｒｂｉｎｄｕｎｇｓｔｅｃｈｎｉｋ ｉｎ Ｅｌｅｋ
ｔｒｏｎｉｋ）」の第５回研究会の資料第２５〜２９頁
から既に公知である。その際例えば絶縁層はその両側面
に銅からなる中間層を施された（直接銅接合）Ａｌ2Ｏ3
層である。半導体チップはろう層を介して一方の中間層
とまた熱放出装置は別のろう層を介して他方の中間層と
接合されている。2. Description of the Related Art Semiconductor modules of the type having an electrically insulating and thermally conductive layer between a semiconductor chip and a heat-dissipating device have been described in "Electronics", Felbach, February 20-22, 1990, for example. Joining Technology (V
erbindungstechnik in Elek
It is already known from the material of the 5th study group of "Tronik)", pages 25-29. In this case, for example, the insulating layer is provided with an intermediate layer made of copper on both sides thereof (direct copper bonding) Al 2 O 3
It is a layer. The semiconductor chip is bonded to one intermediate layer via the brazing layer, and the heat dissipation device is bonded to the other intermediate layer via another brazing layer.

【０００３】[0003]

【発明が解決しようとする課題】本発明は、半導体チッ
プと熱放出装置との間に十分な絶縁性を持たせるととも
に公知の半導体モジュールよりも半導体チップと熱放出
装置との間の熱抵抗が極めて僅かな半導体モジュールを
提供することを課題とする。SUMMARY OF THE INVENTION According to the present invention, a semiconductor chip and a heat dissipation device have sufficient insulation, and a thermal resistance between the semiconductor chip and the heat dissipation device is higher than that of a known semiconductor module. It is an object to provide a very small number of semiconductor modules.

【０００４】[0004]

【課題を解決するための手段】この課題は、本発明によ
りそれぞれ請求項１及び１０の特徴部に記載の半導体モ
ジュールにより解決される。This problem is solved according to the invention by a semiconductor module according to the characterizing parts of claims 1 and 10, respectively.

【０００５】請求項２ないし９は本発明による半導体モ
ジュールの有利な実施態様を示すものである。Claims 2 to 9 show advantageous embodiments of the semiconductor module according to the invention.

【０００６】[0006]

【実施例】本発明を図面に基づき以下に詳述する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

【０００７】図１は公知の半導体モジュールの横断面を
示すものであるが、その際半導体チップＣＨＩＰ１と熱
放出装置Ｗ１との間にＤＣＢ基板（ｄｉｒｅｃｔ ｃｏ
ｐｐｅｒ ｂｏｎｄｉｎｇ）ＤＣＢが存在し、これは銅
製中間層（Ｚ１１及びＺ１２）を両側面に施された絶縁
層ＩＳＯ１からなる。熱放出装置Ｗ１は例えば厚さ３ｍ
ｍの銅板からなる半導体モジュールの底板から構成され
ている。半導体チップＣＨＩＰ１はろう層の形の接合層
Ｖ１１を介して中間層Ｚ１１とまた絶縁層ＩＳＯ１は同
様にろう層又は接着層の形の接合層Ｖ１２を介して熱放
出装置Ｗ１と機械的に接合されている。例えば厚さ５０
μｍのろう層Ｖ１１及び厚さ約１００μｍのろう層又は
接着層Ｖ１２、それぞれ厚さ３００μｍの中間層及び厚
さ約６００μｍのアルミナ又は窒化アルミニウムのよう
な通常のセラミックからなる絶縁層ＩＳＯ１から出発し
た場合、銅の熱伝導率ｋ＝３．８Ｗ／ｃｍＫ及びアルミ
ナの熱伝導率ｋ＝０．３Ｗ／ｃｍＫでは底板の熱抵抗と
共に一次元熱抵抗Ｒth＝約０．３５Ｋｃｍ2 ／Ｗを生じ
る。モジュールの横方向の寸法が熱放出装置に向かって
順次大きくなっていくことによって熱放散を付加的に生
じるが、これは熱抵抗の低下を補償する。[0007] Although FIG. 1 shows a cross-section of a known semiconductor module, DCB substrate (d irect c o between the time the semiconductor chip CHIP1 and heat dissipation device W1
There is pper b onding) DCB, which consists of copper intermediate layer (Z11 and Z12) The insulating layer was applied to both sides ISO1. The heat dissipation device W1 has a thickness of 3 m, for example.
It is composed of a bottom plate of a semiconductor module made of a copper plate of m. The semiconductor chip CHIP1 is mechanically bonded to the intermediate layer Z11 via a bonding layer V11 in the form of a brazing layer, and the insulating layer ISO1 is mechanically bonded to the heat dissipation device W1 via a bonding layer V12 in the form of a brazing layer or an adhesive layer. ing. For example, thickness 50
Starting from a .mu.m brazing layer V11 and a brazing or adhesive layer V12 of about 100 .mu.m thickness, respectively an intermediate layer of 300 .mu.m thickness and an insulating layer ISO1 of a usual ceramic such as alumina or aluminum nitride of about 600 .mu.m thickness. , The thermal conductivity of copper k = 3.8 W / cmK and the thermal conductivity of alumina k = 0.3 W / cmK produce a one-dimensional thermal resistance R th = about 0.35 Kcm 2 / W together with the thermal resistance of the bottom plate. Increasing the lateral dimension of the module towards the heat-dissipating device additionally causes heat dissipation, which compensates for the lowering of the thermal resistance.

【０００８】本発明の基本的な思想は絶縁層の熱抵抗と
接合層の熱抵抗を同時に最適化することにある。本発明
による半導体モジュールの第１の実施例は図２に示され
ているが、この場合半導体モジュールは半導体チップＣ
ＨＩＰ２と底板の形の熱放出装置Ｗ２との間に中間層Ｚ
２及び結晶質炭素（ダイヤモンド）からなる絶縁層ＩＳ
Ｏ２を有する。結晶質炭素からなる層は多結晶質或はま
た単結晶質炭素層と考えてもよいが、その際単結晶質炭
素は例えば結晶核を所定の箇所に置くことにより形成す
ることができ、またこれは粒界をもたないことから多結
晶質炭素層よりも良好な熱伝導率を有する。半導体チッ
プＣＨＩＰ２と中間層Ｚ２（これは例えば銅からなり、
垂直なデバイスでは接触化部となる）との間には本発明
により銀製の接合層Ｖ２１が設けられる。同様にまた中
間層Ｚ２は銀層Ｖ２２を介して絶縁層ＩＳＯ２とまた絶
縁層ＩＳＯ２はその側面で同様に接合層Ｖ２３を介して
熱放出装置Ｗ２の端面領域２と機械的に接合されてい
る。本発明による半導体モジュールを製造するには例え
ば中間層Ｚ２上の接触化面領域内及び熱放出装置Ｗ２の
端面領域２内に例えばスクリーン印刷法により銀ペース
トを塗布し、引続き押圧焼結といわれるそれ自体は公知
の低温接合法により半導体チップＣＨＩＰ２と熱放出装
置Ｗ２との間の機械的接合を行う。その際銀ペーストの
層厚は約１０〜１００μｍであり、銀ペーストは溶剤と
してシクロヘキサノールに懸濁する薄片状の粉末粒子を
有する銀粉末からなる。焼結温度は例えば２３０℃であ
り、約１分間の焼結中に装置全体に垂直方向に少なくと
も９００Ｎ／ｃｍ2 の圧力が作用する。焼結温度は約１
５０℃の下方限界値と約２５０℃の上方限界値を有する
範囲内にある。このことは数秒間の焼結時間で上記部分
の接合が十分に達成され、圧力も１〜２ｔ／ｃｍ2 に上
げることが可能であることを示唆している。半導体チッ
プＣＨＩＰ２にも中間層Ｚ２にも焼結性表面を作るには
例えばチタン、白金及び金の層列を蒸着又はスパッタリ
ングし、熱放出装置Ｗ２の端面領域２は例えばまずニッ
ケルめっきし、次いで銀めっきするか、又は中間層の場
合のようにチタン、白金及び金からなる層列を備えても
よい。例えば接合層Ｖ２１．．．Ｖ２３の厚さをそれぞ
れ１０μｍに、中間層Ｚ２の厚さを３００μｍに、結晶
質炭素層１ＳＯ２の厚さを１００μｍに及び図１のよう
に熱放出装置Ｗ２の厚さを３ｍｍに選択すると、例えば
多結晶質炭素（ダイヤモンド）がｋ＝１２Ｗ／ｃｍＫ及
び銀製接合層がｋ＝４Ｗ／ｃｍＫの熱伝導率を有する場
合底板の熱抵抗値と共に約０．１Ｋｃｍ2 ／Ｗの一次元
熱抵抗Ｒthが生じる。この場合十分な絶縁性とともに約
３倍少ない熱接触抵抗が得られる。The basic idea of the present invention is to simultaneously optimize the thermal resistance of the insulating layer and the thermal resistance of the bonding layer. A first embodiment of a semiconductor module according to the present invention is shown in FIG. 2, where the semiconductor module is a semiconductor chip C.
An intermediate layer Z between the HIP2 and the heat dissipation device W2 in the form of a bottom plate
Insulating layer IS composed of 2 and crystalline carbon (diamond)
Has O2. The layer made of crystalline carbon may be considered as a polycrystalline or monocrystalline carbon layer, in which case the monocrystalline carbon can be formed by, for example, placing crystal nuclei in predetermined places, and It has better thermal conductivity than the polycrystalline carbon layer because it has no grain boundaries. The semiconductor chip CHIP2 and the intermediate layer Z2 (which is made of copper, for example,
According to the present invention, a bonding layer V21 made of silver is provided between the vertical bonding device and the contacting portion). Similarly, the intermediate layer Z2 is mechanically bonded to the insulating layer ISO2 via the silver layer V22, and the insulating layer ISO2 is mechanically bonded to the end surface region 2 of the heat dissipation device W2 on the side surface thereof via the bonding layer V23. In order to manufacture the semiconductor module according to the invention, for example, a silver paste is applied, for example, by a screen printing method in the contact surface area on the intermediate layer Z2 and in the end surface area 2 of the heat dissipation device W2, which is subsequently called pressure sintering. As such, the semiconductor chip CHIP2 and the heat dissipation device W2 are mechanically bonded by a known low-temperature bonding method. The layer thickness of the silver paste is then about 10 to 100 μm and the silver paste consists of silver powder with flaky powder particles suspended in cyclohexanol as solvent. The sintering temperature is, for example, 230 ° C., and a pressure of at least 900 N / cm 2 acts vertically on the entire device during the sintering for about 1 minute. Sintering temperature is about 1
Within the range having a lower limit of 50 ° C and an upper limit of about 250 ° C. This suggests that the joining of the above parts is sufficiently achieved with the sintering time of several seconds and the pressure can be increased to 1 to 2 t / cm 2 . To create a sinterable surface both on the semiconductor chip CHIP2 and on the intermediate layer Z2, a layer sequence of, for example, titanium, platinum and gold is deposited or sputtered, the end face region 2 of the heat-dissipating device W2 is for example first nickel-plated and then silver. It may be plated or provided with a layer sequence of titanium, platinum and gold, as in the case of an intermediate layer. For example, the bonding layer V21. ． ． If the thickness of V23 is 10 μm, the thickness of the intermediate layer Z2 is 300 μm, the thickness of the crystalline carbon layer 1SO2 is 100 μm, and the thickness of the heat dissipation device W2 is 3 mm as shown in FIG. When the polycrystalline carbon (diamond) has a thermal conductivity of k = 12 W / cmK and the silver bonding layer has a thermal conductivity of k = 4 W / cmK, the one-dimensional thermal resistance R th of about 0.1 Kcm 2 / W is obtained together with the thermal resistance of the bottom plate. Occurs. In this case, about 3 times less thermal contact resistance is obtained together with sufficient insulation.

【０００９】図３に示される本発明による半導体モジュ
ールの第２の実施例は半導体チップＣＨＩＰ３、接合層
Ｖ３１．．．Ｖ３３、中間層Ｚ３及び結晶質炭素からな
る絶縁層ＩＳＯ３及び熱放出装置Ｗ３からなるが、その
際図３に基づく半導体モジュールの上部構造は図２に基
づく半導体モジュールの上部構造と熱放出装置Ｗ３を除
いて同じである。底板の形の熱放出装置Ｗ２の代わりに
熱放出装置Ｗ３は例えばアルミニウム又は銅からなる冷
却体からなり、その端面領域３は焼結性表面を備えてい
る。この場合例示した層厚において、一次元的考察では
半導体チップ（ＣＨＩＰ３）と冷却体の端面領域３との
間に約０．０２Ｋ／Ｗｃｍ2 の熱抵抗Ｒthが得られる。The second embodiment of the semiconductor module according to the present invention shown in FIG. 3 is a semiconductor chip CHIP3, a bonding layer V31. ． ． V33, the intermediate layer Z3, the insulating layer ISO3 made of crystalline carbon, and the heat dissipation device W3, in which case the upper structure of the semiconductor module according to FIG. 3 corresponds to the upper structure of the semiconductor module and the heat dissipation device W3 according to FIG. It is the same except. Instead of the heat-dissipating device W2 in the form of a bottom plate, the heat-dissipating device W3 consists of a cooling body, for example of aluminum or copper, whose end face region 3 is provided with a sinterable surface. In the case of the illustrated layer thickness, a thermal resistance R th of about 0.02 K / Wcm 2 is obtained between the semiconductor chip (CHIP3) and the end surface region 3 of the cooling body in a one-dimensional consideration.

【００１０】図４には本発明による半導体モジュールの
第３の実施例が示されているが、ここでは半導体チップ
ＣＨＩＰ４と冷却体の形の熱放出装置Ｗ４との間に接合
層Ｖ４１及びＶ４２、中間層Ｚ４及び結晶質炭素からな
る絶縁層ＩＳＯ４が存在し、その際絶縁層ＩＳＯ４は冷
却体の端面領域４上に成長させられており、また接合層
Ｖ４２は絶縁層ＩＳＯ４を中間層Ｚ４と、接合層Ｖ４１
は半導体チップＣＨＩＰ４を中間層Ｚ４と接合する。図
４に示される実施例は図３に示されている実施例とは、
絶縁層ＩＳＯ４が直接熱放出装置Ｗ４上に成長させられ
ており、絶縁層と熱放出装置との間に全く接合層を施さ
れていない点において異なる。接合層を省略することに
より一層薄い絶縁層、例えば厚さ３０μｍの多結晶質炭
素層（これは直接冷却体上に成長されているために取扱
が一層簡単である）が実現できるので更に熱抵抗を低下
できる。冷却体の端面領域４に絶縁層ＩＳＯ４を成長さ
せる前にこの端面領域に例えばモリブデン又はアルミニ
ウムからなる層を備えてもよい。図２の実施例の層厚を
選択した場合半導体チップＣＨＩＰ４と冷却体の端面領
域４との間の熱接触抵抗Ｒthは約０．０１Ｋ／Ｗｃｍ2
である。１００Ｖ以下の電圧だけが生じる用途では、結
晶質炭素層だけでなく厚さ約１μｍ以下の非晶質炭素
層、いわゆるａ−Ｃ：Ｈ層も使用することができる。し
かしこれは結晶質炭素層よりも絶縁性が僅かであり、熱
伝導率が低い。FIG. 4 shows a third embodiment of the semiconductor module according to the invention, in which the bonding layers V41 and V42 are arranged between the semiconductor chip CHIP4 and the heat dissipation device W4 in the form of a cooling body. There is an intermediate layer Z4 and an insulating layer ISO4 made of crystalline carbon, the insulating layer ISO4 being grown on the end face region 4 of the cooling body, and the bonding layer V42 being the insulating layer ISO4 and the intermediate layer Z4. Bonding layer V41
Connects the semiconductor chip CHIP4 to the intermediate layer Z4. The embodiment shown in FIG. 4 differs from the embodiment shown in FIG.
The difference is that the insulating layer ISO4 is grown directly on the heat dissipation device W4 and there is no bonding layer between the insulation layer and the heat dissipation device. By omitting the bonding layer, a thinner insulating layer, for example, a polycrystalline carbon layer having a thickness of 30 μm (which is easier to handle because it is grown directly on the cooling body), is further provided with a thermal resistance. Can be reduced. Before the insulating layer ISO4 is grown on the end face region 4 of the cooling body, a layer of molybdenum or aluminum, for example, may be provided on this end face region. When the layer thickness of the embodiment of FIG. 2 is selected, the thermal contact resistance R th between the semiconductor chip CHIP4 and the end surface region 4 of the cooling body is about 0.01 K / Wcm 2.
Is. For applications in which only a voltage of 100 V or less is generated, not only a crystalline carbon layer but also an amorphous carbon layer having a thickness of about 1 μm or less, a so-called aC: H layer can be used. However, it has less insulation than the crystalline carbon layer and has a lower thermal conductivity.

【００１１】本発明による半導体モジュールは例えばサ
イリスタのようなパワー半導体、例えばレーザダイオー
ド又は高パワー発光ダイオードのような電力損の高い他
の半導体デバイス並びに良好な熱放出が必要であるマイ
クロ波デバイスや集積回路にも適している。接触化部と
なる銅製中間層は場合によっては省略してもよい。The semiconductor module according to the invention comprises power semiconductors, for example thyristors, other semiconductor devices with high power dissipation, for example laser diodes or high-power light-emitting diodes, as well as microwave devices and integrated circuits in which good heat dissipation is required. Also suitable for circuits. The copper intermediate layer that serves as the contact portion may be omitted in some cases.

【図面の簡単な説明】[Brief description of drawings]

【図１】公知の半導体モジュールの横断面図。FIG. 1 is a cross-sectional view of a known semiconductor module.

【図２】本発明による半導体モジュールの一実施例を示
す横断面図。FIG. 2 is a cross-sectional view showing an embodiment of a semiconductor module according to the present invention.

【図３】本発明による半導体モジュールの別の実施例を
示す横断面図。FIG. 3 is a cross-sectional view showing another embodiment of the semiconductor module according to the present invention.

【図４】本発明による半導体モジュールの更に別の実施
例を示す横断面図。FIG. 4 is a cross-sectional view showing still another embodiment of the semiconductor module according to the present invention.

【符号の説明】 ＣＨＩＰ１．．．ＣＨＩＰ４ 半導体チップ Ｗ１．．．Ｗ４ 熱放出装置 Ｖ１１．．．Ｖ４２ 接合層 Ｚ２．．．Ｚ１２ 中間層 ＩＳＯ１．．．ＩＳＯ４ 電気絶縁性で熱伝導性の層 ２、３、４ 熱放出装置の端面領域[Explanation of Codes] CHIP1. ． ． CHIP4 semiconductor chip W1. ． ． W4 heat release device V11. ． ． V42 Bonding layer Z2. ． ． Z12 intermediate layer ISO1. ． ． ISO4 Electrically insulative and thermally conductive layer 2, 3, 4 End surface area of heat dissipation device

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップ（ＣＨＩＰ１．．．ＣＨＩ
Ｐ４）と熱放出装置（Ｗ１．．．Ｗ４）との間に電気絶
縁性で熱伝導性の層（ＩＳＯ１．．．ＩＳＯ４）を備え
ており、半導体チップ、絶縁層及び熱放出装置間の機械
的接合が接合層（Ｖ１１．．．Ｖ４２）及び少なくとも
１つの中間層（Ｚ２．．．Ｚ１２）を介して行われてい
る半導体モジュールにおいて、電気絶縁性で熱伝導性の
層（ＩＳＯ２．．．ＩＳＯ４）が結晶質炭素からまた接
合層（Ｖ２１．．．Ｖ４２）が銀からなることを特徴と
する半導体モジュール。1. Semiconductor chips (CHIP1 ... CHI)
P4) and the heat dissipation device (W1 ... W4) are provided with electrically insulating and thermally conductive layers (ISO1 ... ISO4), and a machine between the semiconductor chip, the insulating layer and the heat dissipation device. Electrically insulating and thermally conductive layers (ISO2 ...) In a semiconductor module in which the dynamic bonding is carried out via a bonding layer (V11 ... V42) and at least one intermediate layer (Z2 ... Z12). A semiconductor module, characterized in that ISO4) is made of crystalline carbon and the bonding layers (V21 ... V42) are made of silver. 【請求項２】 半導体チップ（ＣＨＩＰ２．．．ＣＨＩ
Ｐ４）と絶縁層（ＩＳＯ２．．．ＩＳＯ４）との間に唯
一の中間層（Ｚ２．．．Ｚ４）を備えており、この中間
層が半導体チップ並びに絶縁層とそれぞれ接合層（Ｖ２
１．．．Ｖ４２）を介して機械的に接合されていること
を特徴とする請求項１記載の半導体モジュール。2. Semiconductor chips (CHIP2 ... CHI)
P4) and the insulating layer (ISO2 ... ISO4) are provided with only one intermediate layer (Z2 ... Z4), and this intermediate layer is connected to the semiconductor chip and the insulating layer, respectively, and the bonding layer (V2).
1. ． ． The semiconductor module according to claim 1, wherein the semiconductor module is mechanically joined via V42). 【請求項３】 半導体チップ（ＣＨＩＰ２．．．ＣＨＩ
Ｐ４）、中間層（Ｚ２．．．Ｚ４）、絶縁層（ＩＳＯ
２．．．ＩＳＯ４）及び熱放出装置（Ｗ２．．．Ｗ４）
の機械的接合が押圧焼結により行われていることを特徴
とする請求項１又は２記載の半導体モジュール。3. Semiconductor chips (CHIP2 ... CHI)
P4), intermediate layers (Z2 ... Z4), insulating layers (ISO
2. ． ． ISO4) and heat dissipation device (W2 ... W4)
3. The semiconductor module according to claim 1 or 2, wherein the mechanical joining of is performed by pressure sintering. 【請求項４】 中間層が銅からなるとともに、順次にニ
ッケルからなる被覆及び銀からなる被覆又は順次にそれ
ぞれチタン、白金及び金からなる被覆を備えていること
を特徴とする請求項１ないし３の１つに記載の半導体モ
ジュール。4. The intermediate layer is made of copper, and is provided with a coating of nickel and a coating of silver, or a coating of titanium, platinum and gold, respectively. The semiconductor module according to any one of 1. 【請求項５】 熱放出装置（Ｗ２）が半導体モジュール
の金属製底板からなり、この底板が焼結可能の端面領域
（２）を備えていることを特徴とする請求項１ないし４
の１つに記載の半導体モジュール。5. The heat-dissipating device (W2) comprises a metal bottom plate of a semiconductor module, which bottom plate is provided with a sinterable end face region (2).
The semiconductor module according to any one of 1. 【請求項６】 熱放出装置（Ｗ３）が冷却体からなり、
この冷却体が焼結可能の端面領域（３）を備えているこ
とを特徴とする請求項１ないし４の１つに記載の半導体
モジュール。6. The heat dissipation device (W3) comprises a cooling body,
5. The semiconductor module as claimed in claim 1, wherein the cooling body has a sinterable end face region (3). 【請求項７】 熱放出装置（Ｗ４）が冷却体からなり、
この冷却体の端面領域（４）上に直接結晶質炭素からな
る絶縁層（ＩＳＯ４）が析出されていることを特徴とす
る請求項１ないし４の１つに記載の半導体モジュール。7. The heat dissipation device (W4) comprises a cooling body,
5. The semiconductor module according to claim 1, wherein an insulating layer (ISO4) made of crystalline carbon is directly deposited on the end face region (4) of the cooling body. 【請求項８】 電気絶縁性で熱伝導性の層（ＩＳＯ
２．．．ＩＳＯ４）が多結晶質炭素からなることを特徴
とする請求項１ないし７の１つに記載の半導体モジュー
ル。8. An electrically insulating and thermally conductive layer (ISO
2. ． ． 8. The semiconductor module according to claim 1, wherein ISO4) is made of polycrystalline carbon. 【請求項９】 電気絶縁性で熱伝導性の層（ＩＳＯ
２．．．ＩＳＯ４）が単結晶質炭素からなることを特徴
とする請求項１ないし７の１つに記載の半導体モジュー
ル。9. An electrically insulating and thermally conductive layer (ISO
2. ． ． 8. The semiconductor module according to claim 1, wherein ISO4) is made of single crystalline carbon. 【請求項１０】 半導体チップ（ＣＨＩＰ１．．．ＣＨ
ＩＰ４）と熱放出装置（Ｗ１．．．Ｗ４）との間に電気
絶縁性で熱伝導性の層（ＩＳＯ１．．．ＩＳＯ４）を備
えており、半導体チップ、絶縁層及び熱放出装置間の機
械的接合が接合層（Ｖ１１．．．Ｖ４２）及び少なくと
も１つの中間層（Ｚ２．．．Ｚ１２）を介して行われて
いる半導体モジュールにおいて、半導体モジュールが低
電圧を供給される限り電気絶縁性で熱伝導性の層（ＩＳ
Ｏ２．．．ＩＳＯ４）が非晶質炭素からなり、接合層が
銀からなることを特徴とする半導体モジュール。10. Semiconductor chips (CHIP1..CH)
An electrically insulating and thermally conductive layer (ISO1 ... ISO4) is provided between the IP4) and the heat dissipation device (W1 ... W4), and a machine between the semiconductor chip, the insulating layer and the heat dissipation device is provided. In a semiconductor module in which a dynamic bonding is performed via a bonding layer (V11 ... V42) and at least one intermediate layer (Z2 ... Z12), it is electrically insulating as long as the semiconductor module is supplied with a low voltage. Thermally conductive layer (IS
O2. ． ． A semiconductor module characterized in that ISO4) is made of amorphous carbon and the bonding layer is made of silver.
JP2486793A 1992-01-23 1993-01-20 Semiconductor module Expired - Lifetime JP3338495B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4201794 1992-01-23
DE4201794.7 1992-01-23

Publications (2)

Publication Number Publication Date
JPH05259328A true JPH05259328A (en) 1993-10-08
JP3338495B2 JP3338495B2 (en) 2002-10-28

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ID=6450111

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Country Link
US (1) US5786633A (en)
EP (1) EP0552475B1 (en)
JP (1) JP3338495B2 (en)
CA (1) CA2087799A1 (en)
DE (1) DE59208893D1 (en)

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DE59208893D1 (en) 1997-10-16
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CA2087799A1 (en) 1993-07-24
US5786633A (en) 1998-07-28
JP3338495B2 (en) 2002-10-28

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