JPH05259165A - Semiconductor device - Google Patents

Abstract

PURPOSE:To elevate a manufacturing yield or reliability by a method wherein a stringer facing to a scribe area is not formed from a metallic wiring layer of a top layer. CONSTITUTION:A step part of a marginal part 21a facing to a scribe area 13 out of interlayer insulating films 21 directly under an Al wiring layer of a top layer is coated with an Al layer 22 patterned from the Al wiring layer of the top layer. Therefore, even if the Al wiring layer of the top layer is patterned by anisotropic etching, a stringer of the Al wiring layer of the top layer is not left in a side-wall-form on a step part in the marginal step 21a of the interlayer insulating film 21. Accordingly, this stringer does not separate or the separated stringer is not scattered on a semiconductor wafer 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of metal wiring layers.

[0002]

2. Description of the Related Art In a semiconductor device, a plurality of metal wiring layers are often used for higher integration and higher speed. Figure 2
In a semiconductor wafer 11 in which a conventional example of a semiconductor device having two Al wiring layers is manufactured, a boundary region 14 between an internal region 12 of a chip and a scribe region 13 and its vicinity are shown. ing.

In this conventional example, a field oxide film 15 is formed in the element isolation region of the internal region 12 of the semiconductor wafer 11 by a selective oxidation method. Several wiring layers of a polycide film, a polycrystalline Si film or the like are formed on the semiconductor wafer 11 in a portion of the internal region 12 which is not shown in the drawing, and the interlayer insulating film 16 such as an AsSG film is used for wiring these layers Covering the layers.

The interlayer insulating film 16 is patterned so that its peripheral portion 16a is located in the boundary region 14.
On the interlayer insulating film 16, a portion of the internal region 12 not shown in the drawing,
A first Al wiring layer is formed. Then, the Al layer 17 which is the same layer as the first Al wiring layer is patterned so as to cover the step portion in the peripheral portion 16 a of the interlayer insulating film 16.

The first-layer Al wiring layer and the Al layer 17 are covered with an interlayer insulating film 21, and this interlayer insulating film 21 is also patterned so that its peripheral edge portion 21 a is located in the boundary region 14. .. The internal region 12 is formed on the interlayer insulating film 21.
The second Al wiring layer is formed in a portion outside the drawing. Then, the Al of the same layer as the second Al wiring layer is formed.
Layer 22 is patterned along the perimeter of interior region 12.

The second Al wiring layer and the Al layer 22 are covered with an overcoat film 23. This overcoat film 2
At the same time as etching for exposing a bonding pad (not shown), 3 is etched for removing a portion on the scribe region 13. Therefore, the peripheral edge of the overcoat film 23 is the boundary between the scribe region 13 and the boundary region 14.

In such a conventional example, a portion of the Al layer 17 which is in direct contact with the semiconductor wafer 11 is combined with the semiconductor wafer 11 to be alloyed, so that from the outside of the chip to the inside region 12. It blocks the entry of hydrogen. Therefore, it is possible to prevent the characteristics of the transistor, the resistance value of the resistance element, and the like from changing due to the penetration of hydrogen.
Further, the Al layer 22 prevents the chip from cracking during scribing.

[0008]

By the way, if isotropic etching is carried out when patterning the Al wiring layer, A
It is impossible to miniaturize the semiconductor device by narrowing the line width of the l wiring layer. For this reason, anisotropic etching is usually performed.

However, when the second Al wiring layer is anisotropically etched, the Al layer 22 patterned from the second Al wiring layer is arranged as in the conventional example. As shown in FIG. 2, the stringer 24 of the second-layer Al wiring layer is likely to remain in a sidewall shape at the step portion in the peripheral edge portion 21a of the interlayer insulating film 21.

Then, the resist (not shown) used for patterning the second Al wiring layer is stripped, pretreatment and heat treatment for sintering, and the bonding pad (not shown) is exposed. The stringer 24 may be peeled off or the peeled stringer 24 may be scattered on the semiconductor wafer 11 by a post-process such as side etching. Therefore, in the conventional semiconductor device shown in FIG. 2, the manufacturing yield and reliability are not necessarily high.

[0011]

In the semiconductor device according to the present invention, patterning is performed so as to cover the step portion of the peripheral edge portion 21a facing the scribe region 13 in the interlayer insulating film 21 immediately below the uppermost metal wiring layer. The uppermost metal wiring layer 22 is provided.

[0012]

In the semiconductor device according to the present invention, since the uppermost metal wiring layer 22 covers the step itself in the peripheral edge portion 21a of the interlayer insulating film 21 immediately thereunder, the uppermost metal wiring layer is anisotropically etched. Even if the patterning is performed, the stringer 24 of the uppermost metal wiring layer does not remain in the side wall shape at the step portion in the peripheral edge portion 21a of the interlayer insulating film 21.

[0013]

EXAMPLE One example of the present invention applied to a semiconductor device having two Al wiring layers will be described below with reference to FIG. The components corresponding to those of the conventional example shown in FIG. 2 are designated by the same reference numerals.

In this embodiment, except that the Al layer 22 patterned from the second Al wiring layer is arranged so as to cover the stepped portion in the peripheral portion 21a of the interlayer insulating film 21, The structure is substantially the same as that of the conventional example shown in FIG.

In this embodiment, since the Al layer 22 also has a portion that is in direct contact with the semiconductor wafer 11, this portion is also compounded and alloyed with the semiconductor wafer 11 like the Al layer 17. In addition, hydrogen is prevented from entering the inside region 12 from outside the chip. Further, the Al layer 22 is
It also has the function of preventing cracks from occurring in the chip during scribing.

In this embodiment, since the Al layer 22 covers the step portion itself in the peripheral edge portion 21a of the interlayer insulating film 21, the Al layer 22 and other Al wiring layers (not shown) are patterned. Therefore, even if the second Al wiring layer is anisotropically etched, the peripheral edge portion 2 of the interlayer insulating film 21 is
The stringer 24 of the second Al wiring layer does not remain like a sidewall at the step portion of 1a.

Therefore, in the subsequent steps, the stringer 24 does not peel off and the peeled stringer 24 does not scatter on the semiconductor wafer 11, and the semiconductor device of this embodiment has a high manufacturing yield and high reliability. ..

[0018]

In the semiconductor device according to the present invention, since the stringer of the uppermost metal wiring layer does not remain on the side wall, the stringer does not peel off or the peeled stringer scatters. High manufacturing yield and reliability of equipment.

[Brief description of drawings]

FIG. 1 is a side sectional view of an embodiment of the present invention.

FIG. 2 is a side sectional view of a conventional example of the present invention.

[Explanation of symbols]

 13 scribe region 17 Al layer 21 interlayer insulating film 21a peripheral portion 22 Al layer

Claims (1)

[Claims] 1. A semiconductor device having a plurality of metal wiring layers, which is patterned so as to cover a step portion of a peripheral portion facing a scribe region in an interlayer insulating film immediately below the uppermost metal wiring layer. And a semiconductor device having the uppermost metal wiring layer.