JPH05259109A - Formation method of metal wiring layer - Google Patents

Abstract

PURPOSE:To provide the formation method, of a metal wiring layer, wherein the aspect ratio of an opening part does not become large after a barrier metal film has been formed or the film thickness of the metal wiring layer as a whole is not increased in the formation method, of the metal wiring layer, wherein, after the opening part has been formed in an interlayer insulating film formed on a semiconductor substrate, the barrier metal layer is formed and the metal wiring layer is then formed by a blanket CVD method. CONSTITUTION:The title formation method is composed of the following: a process wherein a barrier metal layer 22 is formed on the upper surface of an interlayer insulating layer 14 and at the inside of an opening part 16 by using an electron cyclotron resonance CVD method; and a process wherein at least one part of the barrier metal layer 22 formed on the upper surface of the interlayer insulating layer 14 is shaped by a polishing method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring layer in a semiconductor device.

[0002]

2. Description of the Related Art In a multi-layer wiring forming process technology for the next generation and later ULSI, a conductive material is provided in an opening provided in an interlayer insulating layer formed on a semiconductor substrate or a lower layer wiring (hereinafter, also referred to as an underlayer). Embedded, 0.3
A so-called blanket CVD method has been attracting attention as a technique for forming a fine contact hole, a through hole, or a via hole (hereinafter, also simply referred to as a connection hole) of 5 micron rule or less. Specifically, the blanket CVD method is, for example, a CVD method in which a metal wiring layer made of, for example, tungsten is formed on the upper surface of an interlayer insulating layer formed on a base layer and in an opening formed in the interlayer insulating layer. After depositing, the metal wiring layer formed on the upper surface of the interlayer insulating layer is etched back and removed to complete the connection hole having the metal plug formed inside the opening.

When forming a metal wiring layer or a metal plug by the blanket CVD method, it is necessary to form a barrier metal layer under the metal wiring layer or the metal plug. The reason is that although the metal wiring layer formed by the blanket CVD method has excellent step coverage,
This is because the adhesiveness to the interlayer insulating layer is poor due to the difference in internal stress at the interface between different material layers. It is also necessary to prevent the metal fluoride gas, which is the source gas for forming the metal wiring layer, from eroding the underlayer.
Further, since the metal wiring layer is formed by the blanket CVD method at a relatively high temperature, it is necessary to enhance the barrier property with respect to the underlying layer.

As described above, it is necessary to form the barrier metal layer made of titanium nitride (TiN) or the like between the metal wiring layer and the interlayer insulating layer. In addition, a thin film transistor (T
The semiconductor device is subjected to heat treatment in the annealing process at the time of forming FT) and the reflow process process of the interlayer insulating layer made of BPSG or the like. The formation of the barrier metal layer is indispensable also in order to prevent the phenomenon that the underlayer and the metal plug react with each other in this heat treatment step to destroy the junction.

At present, only the method of forming the barrier metal layer by the sputtering method has been put into practical use. However, in general, a film formed by the sputtering method has poor step coverage. In the ULSI process technology of the next generation and thereafter, it is required to form a connection hole of 0.35 μm rule or less. However, it is extremely difficult to form the barrier metal layer with good coverage in the opening formed in the interlayer insulating layer and having a large aspect ratio by the sputtering method. For example, when the aspect ratio is 2, the thickness of the film formed on the bottom surface of the opening is only about 10% of the thickness of the film formed on the upper surface of the interlayer insulating layer. In the barrier metal layer made of TiN formed by the sputtering method, it is difficult to prevent the above-described phenomenon that the metal plug made of tungsten or the like reacts with the base layer in the heat treatment step to destroy the junction. Therefore, using a CVD method with good coverage as an alternative to the sputtering method, Ti
A method of forming a barrier metal layer made of N has been developed.

As one of such CVD methods, there is an electron cyclotron resonance CVD method (hereinafter also referred to as an ECR CVD method) capable of obtaining an anisotropic deposition shape. This EC
In the RCVD method, the active species of the reaction gas have directionality, so that the thin film is hardly formed on the side wall of the opening parallel to the incident direction of the reaction gas, and the upper surface of the interlayer insulating layer and the opening It is characterized in that it is formed at the bottom of the.

[0007]

[Problems to be Solved by the Invention] However, ECR
Even if the barrier metal layer is formed by the CVD method, the film thickness d of the thin film formed on the upper surface of the interlayer insulating layer increases as the diameter of the opening decreases and the aspect ratio increases.
There is a problem that the ratio of the film thickness d _bottom of the thin film formed at the bottom of the opening to the _surface becomes small.
That is, in order to form a barrier metal layer having a desired film thickness on the bottom of the opening, a thick barrier metal layer must be formed on the upper surface of the interlayer insulating layer. As a result, (d
The depth of the opening becomes deeper by the amount of _surface −d _{bot tom} ,
Therefore, the aspect ratio of the opening becomes large, and in the blanket CVD method in the subsequent step, there arises a problem that the filling of the opening with the metal wiring layer becomes poor.

Further, when a part of the barrier metal layer formed on the upper surface of the interlayer insulating layer is left and the barrier metal layer is used as it is as a base of the metal wiring layer, it is formed on the upper surface of the interlayer insulating layer. Since the thickness of the barrier metal layer is large, there is a problem in that the thickness of the entire metal wiring formed in a later step is increased and it becomes difficult to planarize.

Therefore, an object of the present invention is to form a barrier metal layer after forming an opening in an interlayer insulating layer formed on a semiconductor substrate, and then form a metal wiring layer by a blanket CVD method. The present invention provides a method for forming a metal wiring layer which does not increase the aspect ratio of the opening after forming the barrier metal layer or does not increase the thickness of the entire metal wiring. is there.

[0010]

The above-mentioned object is (a) a step of forming a barrier metal layer on the upper surface and in the opening of the interlayer insulating layer by electron cyclotron resonance CVD method; It can be achieved by the method for forming a metal wiring layer of the present invention, which comprises a step of shaving at least a part of the barrier metal layer formed on the upper surface by a polishing method.

The barrier metal layer is made of TiN, Ti / Ti
N, TiSi ₂ / TiN, TiON, Ti / TiON,
It is preferably composed of TiSi ₂ / TiON, TiW, MoSi ₂ , WSi ₂ . A metal wiring layer is formed on TiN, TiON or TiW.

The interlayer insulating layer is made of SiO ₂ , PSG, BS.
G, BPSG, AsSG, PbSG, SbSG, silicon nitride film, SOG, SiON, etc.
Can be formed by the method. Also, the opening is usually formed by photolithography and reactive ion.
It can be formed by an etching method. The metal wiring layer is made of tungsten, nickel, molybdenum, cobalt or the like, and is formed by a so-called blanket CVD method. Alternatively, it is made of aluminum and can be formed by a so-called selective CVD method.

The polishing method is a technique which has been used in recent years in mirror finishing of semiconductor substrates and in SOI (Silicon On Insulator) devices. For example, the document "Trench Insul" is used.
atorby Selective Epi and CVD Oxide Cap '' J. Electr
Ochem SOC, Vol. 137, No. 12, December 1990, it is also applied to planarization of an interlayer insulating layer. FIG. 4 shows an outline of the polishing apparatus 100 used in the polishing method. The polishing apparatus 100 includes a polishing plate 10
2. A substrate support 110 and a slurry supply system 116. The polishing plate 102 is supported by a rotating polishing plate rotating shaft 106, and a polishing pad 104 is provided on the surface thereof. The substrate support 110 is the polishing plate 1
02, and is supported by the substrate support base rotation shaft 112. The substrate 108 to be polished is the substrate support 110.
Placed on. The substrate support base rotation shaft 112 is attached to a polishing pressure adjusting mechanism 114 that pushes the substrate support base toward the polishing pad. The slurry 120 containing the abrasive is
The slurry is supplied from the slurry supply system 116 to the polishing pad 104 through the slurry supply port 118.

The polishing method uses such a polishing apparatus 100.
To use. Then, the polishing plate 102 is rotated while the slurry 120 containing the polishing agent is supplied to the polishing pad 104. At the same time, while rotating the substrate 108 placed on the substrate support 110, the polishing pressure adjusting mechanism 114 adjusts the polishing pressure of the substrate 108 to the polishing pad 104. In this way, the surface of the substrate 108 can be polished.

Alternatively, as described in Japanese Utility Model Laid-Open No. 63-754, the slurry is treated with a polishing plate rotating shaft 1
It is also possible to supply the slurry from the slurry supply port 118 provided in the polishing pad 104 via 06 and the inside of the polishing plate 102 (see FIG. 5).

In a preferred embodiment of the present invention, all of the barrier metal layer formed on the upper surface of the interlayer insulating layer is ground by a polishing method, and then an adhesion layer is formed on the exposed interlayer insulating layer. This method is suitable when it is difficult to remove a part of the barrier metal layer by the polishing method. The exposed interlayer insulating layer is generally
Although the adhesion to the metal wiring layer deposited by the blanket CVD method is not good, the adhesion layer can improve the adhesion between the interlayer insulating layer and the metal wiring layer. The adhesion layer is made of TiN and TiON. Since this adhesion layer does not require coverage, it can be formed by the CVD method or the sputtering method. Alternatively, tungsten or TiW formed by a sputtering method can be used.

[0017]

In the method of the present invention, the barrier metal layer is made E
Since it is formed by the CR CVD method, a thick barrier metal layer can be formed at the bottom of the opening. Further, since at least a part of the barrier metal layer formed on the upper surface of the interlayer insulating layer is ground by the polishing method, the aspect ratio of the opening after forming the barrier metal layer does not increase, or the barrier metal layer is formed in a later step. The thickness of the entire metal wiring is not increased.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of the present invention will now be described based on embodiments with reference to the drawings. In the examples, the method of the present invention is applied to the so-called blanket tungsten CVD method. The apparatus used for forming the barrier metal layer is an ECR CVD apparatus.

Example 1 [Step-100] After an interlayer insulating layer 14 made of SiO ₂ and having a thickness of about 800 nm is formed on a silicon substrate 10 by a CVD method, a conventional method such as a photolithography method and The opening 16 is formed in the interlayer insulating layer 14 by the reactive ion etching method (see FIG. 1A). The silicon substrate 10 has an impurity diffusion region 12
Are formed.

[Step-110] A barrier metal layer 22 made of Ti / TiN is formed at 20/150 nm on the upper surface of the interlayer insulating layer 14 and in the opening 16 by ECR CVD method (FIG. 1 (B)). reference). Incidentally, FIG. 1 (B)
Among them, 18 is a Ti layer and 20 is a TiN layer. Ti layer 18
The formation conditions of are as follows. TiCl ₄ / H ₂ / Ar = 10/50/5 sccm Microwave power 3 kW Temperature 600 ° C Pressure 0.1 Pa Note that H ₂ and Ar are plasmatized by electron cyclotron resonance. Subsequently, the TiN layer 20 is formed under the following conditions. TiCl ₄ / N ₂ / H ₂ / Ar = 10/15/50 / 5scc
m Microwave power 3 kW Temperature 600 ° C Pressure 0.1 Pa Note that N ₂ , H ₂ and Ar are turned into plasma by electron cyclotron resonance.

[Step-120] Next, a part of the barrier metal layer 22 formed on the interlayer insulating layer 14 is removed by the polishing method (see FIG. 1C). The conditions for removal are as follows. The polishing apparatus shown in FIG. 4 was used as the polishing apparatus. Polishing pressure = 5.0 PSI Polishing plate / Substrate support rotation number = 12/26 RPM At this time, the TiN layer 20 forming the barrier metal layer 22 on the interlayer insulating layer 14 is blanket tungsten CVD in the next step. About 50 nm is left as an adhesion layer of tungsten in the method.

[Step-130] After that, the metal wiring layer 24 is formed by the blanket tungsten CVD method. The inside of the opening 16 is filled with a metal wiring layer (see FIG. 2). The metal wiring was completed by patterning this metal wiring layer 24 by a usual method. Alternatively, the metal wiring layer 24 and the barrier metal layer 22 formed on the upper surface of the interlayer insulating layer may be etched back to complete the connection hole having the metal plug formed in the opening.

(Embodiment 2) In Embodiment 2, the barrier metal layer formed on the upper surface of the interlayer insulating layer is completely removed by the polishing method, and the adhesion layer is formed on the exposed upper surface of the interlayer insulating layer. [Step-200] This step corresponds to [Step-10 in Example 1].
0] and [Step-110], the description thereof will be omitted.

[Step-210] Next, the entire barrier metal layer 22 formed on the upper surface of the interlayer insulating layer 14 is removed by the polishing method (see FIG. 3A). The conditions for removal are as follows. The polishing apparatus shown in FIG. 4 was used as the polishing apparatus. Polishing pressure = 5.0 PSI Polishing plate / Substrate support rotation speed = 12/26 RPM

[Step-220] Next, an adhesion layer 30 made of TiN and having a thickness of about 50 nm was deposited by the ECR CVD method (see FIG. 3B). The conditions for forming the adhesion layer 30 are as follows. TiCl ₄ / N ₂ / H ₂ / Ar = 10/15/50 / 5scc
m Microwave power 3 kW Temperature 600 ° C Pressure 0.1 Pa Note that N ₂ , H ₂ and Ar are turned into plasma by electron cyclotron resonance. Since the adhesion layer 30 may be formed on the upper surface of the interlayer insulating layer 14 exposed by the polishing method, a method with good coverage is preferable, but good adhesion is not necessarily required for the adhesion layer. Therefore, the adhesion layer 30 can be formed by another CVD method or sputtering method.

[Step-230] After that, a metal wiring layer is formed by a blanket tungsten CVD method. The inside of the opening is filled with a metal wiring layer. The metal wiring layer is completed by patterning this metal wiring layer by a normal method, or the metal wiring layer and the adhesion layer formed on the upper surface of the interlayer insulating layer are etched back to form a metal plug in the opening. The formed connection hole is completed.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. Although the interlayer insulating layer is formed on the semiconductor substrate in which the impurity diffusion region is formed in the embodiment, it is also possible to form the interlayer insulating layer on the semiconductor substrate in which the lower wiring layer is formed. Are included in the method of forming.

[0028]

According to the method of the present invention, since a thick barrier metal layer can be formed at the bottom of the opening and the thickness of the barrier metal layer on the upper surface of the interlayer insulating layer can be reduced, the barrier property is improved. High, and in the blanket CVD method of the subsequent process, the aspect ratio of the opening is increased, or
There is no problem such as an increase in the thickness of the entire metal wiring. The effect of the present invention becomes more remarkable as the semiconductor device becomes finer.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor device for explaining each step of a preferred embodiment of the method of the present invention.

FIG. 2 is a schematic partial cross-sectional view of a semiconductor element for explaining the process following FIG.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor device for explaining a part of the process of another preferred embodiment of the method of the present invention.

FIG. 4 is a diagram showing an outline of a polishing apparatus suitable for the polishing method.

FIG. 5 is a diagram showing a part of another polishing apparatus suitable for the polishing method.

[Explanation of symbols]

 10 Silicon Substrate 12 Impurity Diffusion Region 14 Interlayer Insulating Layer 16 Opening 18 Ti Layer 20 TiN Layer 22 Barrier Metal Layer 24 Metal Wiring Layer 30 Adhesion Layer 100 Polishing Device 102 Polishing Plate 104 Polishing Pad 106 Polishing Plate Rotating Axis 108 Substrate 110 Substrate Support Table 112 Substrate support table Rotation shaft 114 Polishing pressure adjusting mechanism 116 Slurry supply system 118 Slurry supply port 120 Slurry

Claims (2)

[Claims] 1. A method for forming a metal wiring layer, comprising forming an opening in an interlayer insulating layer formed on a semiconductor substrate, forming a barrier metal layer, and then forming a metal wiring layer by a blanket CVD method. A) forming a barrier metal layer on the upper surface of the interlayer insulating layer and in the opening by an electron cyclotron resonance CVD method; and (b) at least a part of the barrier metal layer formed on the upper surface of the interlayer insulating layer. Process of polishing by polishing method,
A method of forming a metal wiring layer comprising: 2. The barrier metal layer formed on the upper surface of the interlayer insulating layer is entirely ground by a polishing method, and then an adhesion layer is formed on the exposed interlayer insulating layer. A method for forming a metal wiring layer as described above.