JPH06326099A - Method for forming wiring of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a novel method for forming wiring of a semiconductor device which eliminates the need for performing the patterning of a metal wiring layer using a photolithography technology and a dry etching technology for forming wiring and completely flattening the insulation layer including wiring without polishing the insulation layer formed on the wiring. CONSTITUTION:The title method includes steps of forming an insulation layer 12 on a substrate 10 and then a groove part 14 on the insulation layer, forming a metal wiring layer 20 on the insulation layer 12 including the groove part 14, eliminating the metal wiring layer 20 on the insulation layer 12, and leaving the metal wiring layer inside the groove part 14 as a wiring 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming wiring in a semiconductor device by a so-called high temperature aluminum sputtering method or a CVD method of refractory metal or refractory metal compound.

[0002]

2. Description of the Related Art As semiconductor devices have become highly integrated, the dimensional rules of the semiconductor device manufacturing process have become finer, and the wiring widths of semiconductor devices have also become finer.
Usually, pure aluminum or aluminum alloy (hereinafter collectively referred to as Al-based alloy) or refractory metal is mainly used as the wiring material. And
For example, after forming a metal wiring layer made of an Al-based alloy by a so-called high-temperature aluminum sputtering method on a base made of an insulating layer, the metal wiring layer is formed into a desired pattern shape by a photolithography technique and an etching technique. A wiring made of a system alloy is formed.
After that, an insulating film is formed over the wiring, and the insulating film is planarized.

In order to form a resist pattern on the metal wiring layer by photolithography,
It is necessary to suppress irregular reflection of light by the metal wiring layer. When irregular reflection of light cannot be suppressed during exposure, halation occurs due to the influence of irregular reflection of light, and defects such as step breakage of the resist occur in the formed resist pattern. Therefore, normally
For example, after forming an antireflection film made of TiON on the metal wiring layer, resist patterning is performed.

Hereinafter, an example of a conventional semiconductor device manufacturing process based on the high temperature aluminum sputtering method will be described with reference to FIGS. 6 and 7.

[Step-10] Base 1 made of semiconductor substrate
An element isolation region 30 and a gate region 32 are formed at 0.
After that, LDD ion implantation is performed to form the gate sidewall 34, and ion implantation is performed to form the source / drain regions 36 (see FIG. 6A).

[Step-20] After that, an interlayer insulating layer 38 is formed on the entire surface, and then an opening 40 is formed in the interlayer insulating layer 38 (see FIG. 6B).

[Step-30] Next, Ti / TiN / T is formed on the entire surface of the interlayer insulating layer 38 including the opening 40 by the sputtering method.
After forming the barrier layer 50 composed of i, an Al-based alloy (for example, Al-1w) is formed by a high temperature aluminum sputtering method.
A metal wiring layer 52 made of t% Si) is deposited on the entire surface. After that, an antireflection film 54 made of TiON is formed on the entire surface. Then, the antireflection film 54 and the metal wiring layer 52
Are patterned by photolithography and dry etching techniques to form wirings 56 (see FIG. 6C).

[Step-40] Next, a flattening process is performed. That is, the entire surface including the wiring is Si by the plasma CVD method.
A first insulating film 60 made of O ₂ is formed, a stopper layer 62 made of SiN is formed on the first insulating film 60 by plasma CVD, and a second insulating film 64 made of thick SiO ₂ is further formed thereon by the CVD method. Formed (see FIG. 7A).

[Step-50] Second insulating film 64 from the top
To polish. Then, polishing is performed until the stopper layer 62 appears as a polishing surface (see FIG. 7B). Thus
A planarized first insulating film 60 is formed on the wiring 56.

Alternatively, instead of [Step-40] and [Step-50] using a stopper layer made of SiN, an insulating film which has been planarized by the following steps can be formed.

[Step-40 '] S by plasma CVD method
forming an insulating film 70 made of iO _2.

[Step-50 '] After that, a resist 72 is formed on the insulating film 70, and the resist 72 is patterned so that the convex portions of the insulating film 70 are exposed (see FIG. 8A).

[Step-60 '] Next, the insulating film 70 is etched to remove the resist (see FIG. 8B).

[Step-70 '] After that, a portion 70A of the insulating film 70 that remains without being etched is polished to planarize the insulating film 70.

[0015]

[Problems to be Solved by the Invention]

When the wiring 56 is miniaturized, it becomes difficult to form a target wiring width with good controllability. This is because the surface of the metal wiring layer 52 becomes uneven due to the effect of the unevenness of the underlying interlayer insulating layer 38, and thus the coverage of the antireflection film in the concave portion of the metal wiring layer 52 is reduced. As a result, the reflectance of the light at that portion is lowered, so that the light is diffusely reflected, and as a result, the desired patterning shape cannot be formed on the metal wiring layer due to the influence of halation or the like.

The wiring structure after resist patterning is an antireflection film / metal wiring layer made of TiON from above. After patterning the resist, the metal wiring layer is patterned by dry etching. In this case, BCl ₃ gas is usually used as the etching gas. However, the etching with the BCl ₃ -based gas is only a chemical reaction, and it is impossible to etch the antireflection film made of TiON with the BCl ₃ -based gas. Therefore, it is necessary to etch the antireflection film by a physical sputtering action.

Therefore, when etching the metal wiring layer made of an Al-based alloy, it is necessary to change the etching conditions having a sputtering action to the chemical etching conditions. However, when the film thickness of the antireflection film / metal wiring layer is non-uniform, there is a problem in that the etching is non-uniform due to such changes in etching conditions.

Furthermore, the method described in [Step-40] and [Step-50] using the stopper layer 62 made of SiN has the following problems. That is, although using the stopper layer 62 at the time of polishing the second insulating film 64 made of SiO _2, the selection ratio with respect to the polishing of the SiO ₂ and SiN 3
Only ~ 6 can be obtained. Therefore, the stopper layer 62 made of SiN does not function as a stopper to determine the polishing end point, and the first insulating film 60 may be excessively polished. That is, the second insulating film 64 cannot be polished with good controllability. As a result, there is a problem in that complete planarization of the first insulating film 60 cannot be achieved.

Moreover, when the wiring is filled with the first insulating film 60 made of SiO ₂ or SOG by the CVD method or the like, if the distance between the wirings is small, the filling of the first insulating film 60 becomes insufficient, and the space between the wirings becomes insufficient. There is also a problem that "voids" 60A are generated in the first insulating film 60 (see FIG. 9).

On the other hand, in the method described in [Step-40 '] to [Step-70'] which does not use the stopper layer made of SiN, the end point of the polishing of the insulating film 70 is judged when the insulating film 70 is polished. Not not. Therefore, there is a problem that the insulating film 70 is excessively polished.

In the manufacture of such a fine semiconductor device, the conventional method of forming the wiring and then forming the flat insulating film thereon has various problems as described above.
There is still no way to effectively solve these problems.

Therefore, an object of the present invention is to eliminate the need for performing the patterning process of the metal wiring layer by the photolithography technique and the dry etching technique for forming the wiring, and moreover, the insulation formed on the wiring as in the conventional case. It is an object of the present invention to provide a novel wiring forming method for a semiconductor device, which enables complete flattening of an insulating layer including wiring without polishing the film.

[0024]

In order to achieve the above object, a method of forming a wiring of a semiconductor device according to the present invention comprises a step of forming an insulating layer on a substrate and then forming a groove portion in the insulating layer, and a groove portion. And a step of forming a metal wiring layer on the insulating layer including the inside, and a step of removing the metal wiring layer on the insulating layer and leaving the metal wiring layer in the groove as wiring.

In the method for forming a wiring of a semiconductor device of the present invention, the method further comprises the step of forming a trench in the insulating layer and then forming a sidewall made of an insulating material on the sidewall of the trench. It is preferable that the method comprises a step of sputtering aluminum or an aluminum alloy while the substrate is heated to a high temperature.

Alternatively, in the wiring forming method for a semiconductor device of the present invention, the step of forming the metal wiring layer is preferably a CVD method of a refractory metal or a refractory metal compound.

Further, the step of removing the metal wiring layer on the insulating layer preferably comprises a step of etching back the metal wiring layer or a step of chemical mechanical polishing of the metal wiring layer.

In these preferred embodiments, the method further includes the step of forming an interlayer insulating layer on the base before forming the insulating layer on the base, and the step of forming a groove in the insulating layer comprises:
The step of forming an opening in the interlayer insulating layer is included, the width of the groove is larger than the diameter of the opening, and in the step of forming the metal wiring layer on the insulating layer including the inside of the groove, the metal wiring is also formed in the opening. It is desirable to form layers.

Alternatively, in these preferred embodiments, before forming the insulating layer on the substrate, an interlayer insulating layer is formed on the substrate, an opening is formed in the interlayer insulating layer, and then the opening is formed. It is preferable that the width of the groove portion is larger than the diameter of the opening portion, further including a step of filling with a metal wiring material and forming a connection hole. In this case, the step of filling the opening with the metal wiring material includes a step of sputtering aluminum or an aluminum-based alloy while the substrate is heated to a high temperature, or a CVD method of refractory metal or refractory metal compound. Is desirable.

[0030]

In the present invention, since the metal wiring layer on the insulating layer is removed and the metal wiring layer is left in the groove to form the wiring, it is formed on the insulating layer by the photolithography technique and the dry etching technique as in the prior art. It is not necessary to pattern the formed metal wiring layer. Further, since the flattening process is performed by removing the metal wiring layer on the insulating layer, it is not necessary to perform the flattening process of the insulating film formed on the wiring as in the conventional technique.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The wiring forming method of the present invention will be described below with reference to the drawings based on the embodiments.

(Example 1) In Example 1, a groove portion 14 is formed in an insulating layer 12 on a substrate 10 made of a semiconductor substrate, and a metal wiring layer 20 is formed on the insulating layer 12 including the groove portion 14.
After forming, the metal wiring layer 20 on the insulating layer 14 is removed by an etch back method, and the wiring 22 is formed while leaving the metal wiring layer only in the groove portion 14. Sidewalls 16 made of SiN are formed on the sides of the groove 14. Further, Al-1 wt% Si is used as the metal wiring material forming the metal wiring layer, and the barrier layer 18 made of Ti is formed as a base when the metal wiring layer is formed by the high temperature sputtering method. Hereinafter, with reference to FIG. 1, which is a schematic partial cross-sectional view of a semiconductor device or the like,
The method of Example 1 will be specifically described.

[Step-100] An insulating layer 12 made of SiO ₂ is formed on a substrate 10 made of, for example, a semiconductor substrate. The insulating layer 12 can be formed under the following conditions, for example. Gas used: SiH ₄ / O ₂ / N ₂ = 250/250/1
00sccm Temperature: 420 ° C Pressure: 13.3Pa Film thickness: 0.8 μm

[Step-110] After that, the insulating layer 1 is formed by the photolithography technique and the dry etching technique.
The groove 14 is formed in the groove 2 (see FIG. 1A). The conditions of dry etching can be set as follows, for example. Gas used: C ₄ F ₈ = 50 sccm RF power: 1200 W Pressure: 2 Pa

[Step-120] After that, a SiN layer is formed on the entire surface by plasma CVD. The conditions for forming the SiN layer can be set as follows, for example. Gas used: SiH ₄ / NH ₃ / N ₂ = 180/500
/ 720 sccm Temperature: 200 ° C. Pressure: 40 Pa Film thickness: 100 nm Next, the SiN layer is entirely etched back under the following conditions. Gas used: CHF ₃ = 50 sccm RF power: 300 W Pressure: 2 Pa As a result, the sidewall 16 made of SiN is formed on the sidewall of the groove 14 (see FIG. 1B). By forming the sidewalls 16, T
When the barrier layer is formed from i, it is possible to prevent the barrier layer from being oxidized by the insulating layer 12. Further, it is possible to prevent the problem that the barrier property of the barrier layer becomes weak at the bottom corner portion of the groove portion 14 and the metal wiring layer formed later penetrates through this portion.

[Step-130] Next, after forming the barrier layer 18 made of Ti on the insulating layer 12 including the groove portion 14 by the sputtering method, the metal wiring material made of Al-1 wt% Si is subjected to the high temperature sputtering method. Then, the metal wiring layer 20 made of Al-based alloy is used to fill the groove 14 (see FIG. 1C). The barrier layer 18 can be formed, for example, under the following conditions. Gas used: Ar = 100 sccm Power: 4 kW Pressure: 0.47 Pa Film formation temperature: 150 ° C. Film thickness: 50 nm Further, the deposition conditions of the metal wiring material by the high temperature sputtering method can be set as follows, for example. Gas used: Ar = 40 sccm Power: 22.5 kW Pressure: 0.47 Pa Film formation temperature: 500 ° C Film thickness: 500 nm

[Step-140] After that, the metal wiring layer 20 is formed.
And the barrier layer 18 is etched back by the dry etching method. As a result, the metal wiring layer 2 is formed only in the groove portion 14.
0 and the barrier layer 18 are left, and the metal wiring layer 2 is formed in the groove portion 14.
0 and the wiring 22 composed of the barrier layer 18 are formed (see FIG.
(D)). The conditions of dry etching can be set as follows, for example. Gas used: BCl ₃ / Cl ₂ = 60/90 sccm Microwave power: 1000W RF power: 50W Pressure: 0.016Pa

Thus, the wiring 22 embedded in the flat insulating layer 12 is formed. In the first embodiment, the formation of an antireflection film, the resist patterning process of the metal wiring layer 20 and the like and the dry etching process as in the conventional method are not necessary, and the problem of light scattering at the time of resist patterning,
The problem of non-uniform etching can be avoided. Further, it is not necessary to form an insulating film on the wiring and to flatten the insulating film.

(Embodiment 2) In Embodiment 2 as well, the groove portion 14 is formed in the insulating layer 12 on the substrate 10 made of a semiconductor substrate, and the metal wiring layer 20 is formed on the insulating layer 12 including the groove portion 14.
After forming, the metal wiring layer 20 on the insulating layer 14 is removed, and the wiring 22 is formed while leaving the metal wiring layer only in the groove portion 14. Sidewalls 16 made of SiN are formed on the sides of the groove 14. Further, Al-1 wt% Si is used as the metal wiring material forming the metal wiring layer, and the barrier layer 18 made of Ti is formed as a base when the metal wiring layer is formed by the high temperature sputtering method.

The second embodiment is different from the first embodiment in that the metal wiring layer 20 other than the groove portion 14 is removed by the chemical mechanical polishing method. In this case, by causing the insulating layer 12 made of SiO ₂ to function as a stopper,
Metal wiring layer 20 for chemical mechanical polishing
It is possible to set the selection ratio of the insulating layer 12 to infinity. Hereinafter, the method of Example 2 will be specifically described.

[Step-200] to [Step-230] For example, the insulating layer 12 made of SiO ₂ is formed on the base 10 made of a semiconductor substrate. After that, the groove portion 14 is formed in the insulating layer 12 by the photolithography technique and the dry etching technique. Then, a SiN layer is formed on the entire surface by a plasma CVD method, and then the SiN layer is entirely etched back to form a groove 1
A side wall 16 made of SiN is formed on the side wall of No. 4. Next, after forming a barrier layer 18 made of Ti on the insulating layer 12 including the groove portion 14 by a sputtering method, Al-1w
A metal wiring material made of t% Si is deposited on the entire surface by a high temperature sputtering method, and the groove portion 14 is filled with the metal wiring layer 20. The above steps may be the same as those in [Step-100] to [Step-130] of the first embodiment.

[Step-240] This step is different from [Step-140] of the first embodiment in that the metal wiring layer 20 and the barrier layer 18 on the insulating layer 12 are removed by the chemical mechanical polishing method and the groove 14 is formed. The wiring 22 is formed while leaving the metal wiring layer 20 and the barrier layer 18. The polishing apparatus shown in FIG. 2 is used for the chemical mechanical polish.
The conditions of the chemical mechanical polish can be as follows, for example. Polishing plate rotation speed: 37 rpm Wafer holding sample table rotation speed: 17 rpm Polishing pressure: 5.5 × 10 ⁸ Pa Pad temperature: 40 ° C. H ₃ PO ₄ + HNO ₃ + CH ₃ COOH solution is used for chemical mechanical polishing. The flow rate of this solution was 225 ml / min.

[0043] When polishing the conventional SiO ₂ using a slurry (SiO ₂ based abrasives + KOH + water) but, when polishing the SiO ₂ in the slurry, because the slurry is not uniformly distributed in the plane to be polished, the polishing There is a problem in that the flattening of the polished surface in the wafer varies due to excessive processing. When polishing a metal wiring layer and a barrier layer made of Al-Si, slurry is not required, and H ₃ PO ₄ + HNO _{3 is used.}
By polishing the metal wiring layer with a + CH ₃ COOH solution or the like, only the metal wiring layer and the barrier layer can be etched back, and there is an advantage that there is little variation in flattening the polished surface in the wafer.

As a result, the wiring 22 embedded in the flat insulating layer 12 is formed. In the second embodiment, unlike the conventional method, the resist patterning process and the dry etching process of the metal wiring layer 20 are unnecessary, and the problem of light scattering at the time of resist patterning and the problem of nonuniform etching can be avoided. it can. Further, it is not necessary to form an insulating film on the wiring and to flatten the insulating film.

(Third Embodiment) The third embodiment is different from the first embodiment in that the interlayer insulating layer 3 is formed on the substrate 10 made of a semiconductor substrate in advance.
8 and the groove 14 is formed in the insulating layer 12 formed on the interlayer insulating layer 38, and then Al-1 wt%
A metal wiring layer 20 made of Si is used as the metal wiring layer 20 made of an Al-based alloy for the opening 40 and the groove 14.
And the metal wiring layer 20 and the barrier layer 18 on the insulating layer 14 are removed by etching back.

In this case, the side wall of the opening 40 and the groove 14 are formed.
By forming the sidewalls 16 made of SiN on the side portions of, the stable high temperature aluminum sputtering method can be performed. By embedding the opening 40 with the metal wiring layer 20, the lower conductor layer and the wiring 22 in the groove 14 are electrically connected. Hereinafter, the method of Example 3 will be described with reference to FIGS. 3 and 4 which are schematic partial cross-sectional views of a semiconductor device and the like.

[Step-300] An element isolation region 30 and a gate region 32 are formed on a substrate 10 made of a semiconductor substrate made of Si (100) by a usual method. Then L
After performing the DD ion implantation, a SiO ₂ film is deposited on the entire surface to form the gate sidewall 34. Si
The conditions for depositing the O ₂ film can be set as follows, for example. Gas used: SiH ₄ / O ₂ / N ₂ = 250/250 /
100 sccm Temperature: 420 ° C Pressure: 13.3 Pa Film thickness: 0.25 μm Further, the entire surface of the SiO ₂ film is etched back to form a gate sidewall 34 on the gate sidewall. The entire surface etchback can be performed, for example, under the following conditions. Gas used: C ₄ F ₈ = 50 sccm RF power: 1200 W Pressure: 2 Pa After that, in order to form the source / drain regions 36, impurity ion implantation is performed under the following conditions, for example. Formation of N-type channel As 20 KeV, 5 × 10 ¹⁵ / cm ² Formation of P-type channel BF _{2 20} KeV, 3 × 10 ¹⁵ / cm ² Thus, the structure shown in FIG. Can be obtained.

[Step-310] After that, SiO ₂ and B
An interlayer insulating layer 38 composed of two PSG layers is formed on the entire surface by, for example, a CVD method under the following conditions. Formation of SiO ₂ layer Gas used: TEOS 50 sccm Pressure: 40 Pa Temperature: 720 ° C Film thickness: 400 nm Formation of BPSG layer Gas used: SiH ₄ / PH ₃ / B ₂ H ₆ / O ₂ / N ₂ = 8
0/7/7/1000/32000 sccm Temperature: 400 ° C Pressure: 1.0 × 10 ⁵ Pa Film thickness: 500 nm Further, a reflow process at 900 ° C. for 20 minutes is performed to planarize the interlayer insulating layer 38.

[Step-320] Next, the insulating layer 12 made of SiO ₂ is formed on the entire surface. The insulating layer 12 can be formed, for example, under the following conditions. Gas used: SiH ₄ / O ₂ / N ₂ = 250/250 /
100 sccm Temperature: 420 ° C Pressure: 13.3 Pa Film thickness: 0.8 μm

[Step-330] After that, similarly to [Step-110] of Example 1, the groove portion 14 is formed in the insulating layer 12 by the photolithography technique and the dry etching technique (see FIG. 3B). .

[Step-340] Next, by performing resist patterning and dry etching, an opening 40 is formed in the interlayer insulating layer 38 (see FIG. 3C). Here, the width of the groove 14 is made larger than the diameter of the opening 40. The conditions of dry etching can be set as follows, for example. Gas used: C ₄ F ₈ 50 sccm RF power: 1200 W Pressure: 2 Pa Further, a junction region is formed by ion implantation into the opening. The following examples can be given as conditions for ion implantation. Formation of N-type channel As 20 KeV, 5 × 10 ¹⁵ / cm ² Formation of P-type channel BF _{2 20} KeV, 3 × 10 ¹⁵ / cm ² After that, activation annealing is performed at 1100 ° C. for 10 seconds.

[Step-350] Then, as in [Step-120] of Example 1, the entire surface was subjected to S by plasma CVD.
An iN layer is formed, and then the SiN layer is entirely etched back to form sidewalls 16 made of SiN on the sidewalls of the opening 40 and the trenches 14 (see FIG. 4A).

[Step-360] Next, Ti / TiN / T
After forming the barrier layer 18 made of i on the insulating layer 12 including the opening 40 and the groove 14 by the sputtering method, Al-S
A metal wiring material made of i is deposited on the entire surface by a high temperature sputtering method, and the opening 40 and the groove 14 are filled with the metal wiring layer 20 (see FIG. 4B). The barrier layer 18 can be formed, for example, under the following conditions. The barrier layer 1
8 is composed of three layers, but in FIG. 4, it is represented by one layer in order to simplify the drawing. The same applies to other drawings. Ti film forming conditions Working gas: Ar = 100 sccm Power: 4 kW Pressure: 0.47 Pa Film forming temperature: 150 ° C Film thickness: 30 nm TiN film forming conditions Working gas: Ar / N ₂ = 40/70 sccm Power: 5 kW Pressure: 0 .47 Pa film thickness: 100 nm Further, the deposition conditions of the metal wiring material by the high temperature sputtering method can be set as follows, for example. Gas used: Ar = 40 sccm Power: 22.5 kW Pressure: 0.47 Pa Film formation temperature: 500 ° C Film thickness: 500 nm

[Step-370] Then, as in [Step-140] of Example 1, the metal wiring layer 20 and the barrier layer 1 were formed.
8 is etched back by the dry etching method. Thereby, the metal wiring layer 20 and the barrier layer 18 are left only in the opening 40 and the groove 14, and the wiring 22 made of the metal wiring layer and the barrier layer is formed in the groove 14 (see FIG. 4C). . The conditions of dry etching can be the same as those in [Step-140] of Example 1, for example. Further, a so-called contact hole in which the metal wiring layer 20 is embedded is formed in the opening 40.

Instead of etching back the metal wiring layer 20 and the barrier layer 18 by the dry etching method, the metal wiring on the insulating layer 12 is formed by the chemical mechanical polishing method as in [Step-240] of the second embodiment. The layer 20 and the barrier layer 18 are removed, and the metal wiring layer 20 is formed in the groove portion 14.
And the wiring 22 is formed while leaving the barrier layer 18, and
A so-called contact hole in which the metal wiring layer 20 is embedded may be formed in the opening 40.

(Embodiment 4) Embodiment 4 is a modification of Embodiment 3. The difference between the fourth embodiment and the third embodiment is that the opening 4 is
After embedding 0 with a metal wiring material, an insulating layer 12 is formed thereon.
Is formed, and the groove 14 is formed in the insulating layer 12, and the second metal wiring layer 20A on the insulating layer 12 is removed by the chemical mechanical polishing method. In Example 4, [Step-30 of Example 3]
0], [Step-310], and [Step-340] are the same steps, and other steps are different. Hereinafter, the method of the fourth embodiment will be described with reference to FIG.

[Step-400] to [Step-420] The element isolation region 30 and the gate region 32 are formed on the substrate 10 made of a semiconductor substrate of Si (100) by a usual method. Next, after performing LDD ion implantation, a gate sidewall 34 is formed and impurity ion implantation is performed for forming source / drain regions. After that, SiO ₂
And an interlayer insulating layer 38 composed of two layers of BPSG are formed on the entire surface by, for example, a CVD method, and a reflow process is performed to planarize the interlayer insulating layer 38. Then, the interlayer insulating layer 38
After the resist patterning, the opening 40 is formed by dry etching, and ions are implanted into the opening to form a junction region, and then activation annealing is performed.
These steps can be the same as [Step-300], [Step-310] and [Step-340] of the third embodiment. Incidentally, next, a sidewall made of SiN may be formed on the sidewall of the opening 40.

[Step-430] After [Step-420], a first barrier layer 42 made of Ti / TiN / Ti is formed on the entire surface, and then Al is formed on the entire surface.
A metal wiring material made of -1 wt% Si is formed into a film by a high temperature sputtering method to form a first metal wiring layer 44. The film forming conditions of the first barrier layer 42 and the conditions of the high temperature sputtering method can be the same as in [Step-360] of the third embodiment.

[Step-440] After that, etch back is performed by a dry etching method to form a first film only in the opening 40.
The metal wiring layer 44 and the first barrier layer 42 of FIG.
(A)). The dry etching conditions are those of Example 1.
[Step-140] of the above. As a result, a so-called contact hole in which the first metal wiring layer 44 is embedded in the opening 40 is formed. Instead of etching back by the dry etching method, the first metal wiring layer 44 and the first barrier layer 42 may be left only in the opening 40 by the chemical mechanical polishing method.

[Step-450] Next, SiO ₂ is formed on the entire surface.
An insulating layer 12 made of is formed. The insulating layer 12 can be formed, for example, under the same conditions as in [Step-320] of the third embodiment.

[Step-460] Thereafter, similar to [Step-330] of the third embodiment, the groove 14 is formed in the insulating layer 12 by the photolithography technique and the dry etching technique.

[Step-470] Then, as in [Step-350] of Example 3, the entire surface was subjected to S by plasma CVD.
An iN layer is formed, and then the SiN layer is entirely etched back to form a sidewall 16 of SiN on the sidewall of the groove 14 (see FIG. 5B).

[Step-480] Then, a second barrier layer 18A made of Ti and having a thickness of 30 nm is sputtered on the insulating layer 12 including the groove 14 in the same manner as in [Step-130] of the first embodiment. Then, a metal wiring material made of Al-1 wt% Si is deposited on the entire surface by high temperature sputtering to fill the groove 14 with the second metal wiring layer 20A.

[Step-490] Then, the second metal wiring layer 20A and the second barrier layer 18A on the insulating layer 12 are removed by the chemical mechanical polishing method, and the groove portion 1 is formed.
The second metal wiring layer 20A and the second barrier layer 18
The wiring 22 is formed while leaving A (see FIG. 5C).
The conditions of the chemical mechanical polishing can be the same as those in [Step-240] of Example 2.

Instead of removing the second metal wiring layer 20A and the second barrier layer 18A on the insulating layer 12 by the chemical mechanical polishing method, the second step is performed in the same manner as in [Step-140] of the first embodiment. Second metal wiring layer 20A and second
The barrier layer 18A may be etched back by a dry etching method to leave the second metal wiring layer 20A and the second barrier layer 18A only in the groove 14 and form the wiring 22 in the groove 14. it can.

(Embodiment 5) Embodiment 5 is a modification of Embodiment 4. The fifth embodiment is different from the fourth embodiment in that a tungsten plug is previously formed in the opening 40 by the CVD method and that the second metal wiring layer 44 and the like are removed by dry etching.

[Step-500] to [Step-520] These steps are
The same process as [Step-400] to [Step-420] of Example 4 can be performed.

[Step-530] After [Step-520], a first barrier layer 42 made of Ti / TiN is formed on the entire surface by a sputtering method, and then a metal wiring material made of tungsten is formed on the entire surface by a CVD method. To form a film. The film forming conditions of TiN and Ti can be set as follows, for example. TiN film forming conditions Working gas: Ar / N ₂ = 40/70 sccm power: 5 kW Pressure: 0.47 Pa Film forming temperature: 150 ° C Film thickness: 100 nm Ti film forming conditions Working gas: Ar = 100 sccm power: 4 kW pressure : 0.47 Pa Film forming temperature: 150 ° C. Film thickness: 50 nm Moreover, the film forming conditions of tungsten by the CVD method are illustrated below. Gas used: WF ₆ / H ₂ = 95/550 sccm Film formation temperature: 450 ° C Pressure: 1.1 × 10 ⁴ Pa Film thickness: 0.4 μm

[Step-540] After that, etching back is performed by a dry etching method to leave the first metal wiring layer 44 and the first barrier layer 42 made of tungsten only in the opening 40. The conditions of dry etching can be set as follows, for example. Gas used: SF ₆ = 50 sccm Microwave power: 850 W RF power: 150 W Pressure: 1.33 Pa This forms a contact hole made of a so-called tungsten plug in which the first metal wiring layer 44 is embedded in the opening 40. . Instead of the etch back by the dry etching method, the first metal wiring layer 44 and the first barrier layer 42 made of tungsten may be left only in the opening 40 by the chemical mechanical polishing method.

[Step-550] Next, SiO ₂ is formed on the entire surface.
An insulating layer 12 made of is formed. The insulating layer 12 can be formed, for example, under the same conditions as in [Step-450] of the fourth embodiment. Thereafter, similar to [Step-460] of Example 4, the groove portion 14 is formed in the insulating layer 12 by the photolithography technique and the dry etching technique, and further, the entire surface is formed in the same manner as [Step-470] of Example 4. Plasma C
A SiN layer is formed by the VD method, and then the SiN layer is entirely etched back, whereby Si is formed on the sidewall of the groove portion 14.
A sidewall 16 made of N is formed. The groove 1
The width of 4 is larger than the diameter of the opening 40.

[Step-560] Next, a second barrier layer 18A made of Ti and having a thickness of 30 nm is sputtered on the insulating layer 12 including the groove portion 14 by the same method as in [Step-480] of the fourth embodiment. Then, a metal wiring material made of Al-1 wt% Si is deposited on the entire surface by high temperature sputtering to fill the groove 14 with the second metal wiring layer 20A.

[Step-570] After that, in the same manner as in [Step-140] of Example 1, the second metal wiring layer 20A is formed.
Then, the second barrier layer 18A is etched back by the dry etching method. As a result, the second groove is formed only in the groove 14.
Leaving the metal wiring layer 20A and the second barrier layer 18A of
The wiring 22 including the second metal wiring layer and the second barrier layer is formed in the groove portion 14.

Instead of etching back the metal wiring layer 20 and the barrier layer 18 by the dry etching method, the metal wiring on the insulating layer 12 is formed by the chemical mechanical polishing method as in [Step-240] of the second embodiment. The layer 20 and the barrier layer 18 are removed, and the metal wiring layer 20 is formed in the groove portion 14.
Alternatively, the wiring 22 may be formed while leaving the barrier layer 18.

(Embodiment 6) Embodiment 6 is a modification of Embodiment 1, and also in Embodiment 6, the groove portion 14 is formed in the insulating layer 12, and the metal wiring layer 2 is formed on the insulating layer 12 including the groove portion 14.
After forming 0, the metal wiring layer 20 on the insulating layer 14 is removed by an etch back method, and the wiring 22 is formed only in the groove portion 14. In Example 6, tungsten (W) is used as the metal wiring material forming the metal wiring layer 20.

[Step-600] For example, the insulating layer 12 made of SiO ₂ is formed on the substrate 10 made of a semiconductor substrate. The conditions for forming the insulating layer 12 made of SiO ₂ can be the same as in [Step-100] of the first embodiment.

[Step-610] After that, the insulating layer 1 is formed by the photolithography technique and the dry etching technique.
The groove portion 14 is formed in 2. Dry etching conditions
For example, it can be the same as [Step-110] of the first embodiment.

[Step-620] Next, the barrier layer 18 made of TiN and Ti is formed on the insulating layer 12 including the groove 14 by the sputtering method. The barrier layer 18 can be formed, for example, under the following conditions. TiN film forming conditions Working gas: Ar / N ₂ = 40/70 sccm Power: 5 kW Pressure: 0.47 Pa Film thickness: 100 nm Ti film forming conditions Working gas: Ar = 100 sccm Power: 4 kW Film forming temperature: 150 ° C Pressure: 0.47Pa film thickness: 50nm

[Step-630] Next, a metal wiring material made of tungsten is deposited on the entire surface by the CVD method to fill the groove portion 14 with the metal wiring layer 20. The tungsten film forming conditions can be set as follows, for example. Gas used: WF ₆ / H ₂ = 95/550 sccm Temperature: 450 ° C Pressure: 1.1 × 10 ⁴ Pa Film thickness: 0.4 μm

[Step-640] After that, the metal wiring layer 20 is formed.
Then, the entire barrier layer 18 is etched back, and the metal wiring layer 20 and the barrier layer 18 are left only in the groove portion 14 to form the wiring 22 including the metal wiring layer and the barrier layer. The conditions for the etch back can be set as follows, for example. Gas used: SF ₆ = 50 sccm Microwave power: 850W RF power: 150W Pressure: 1.33Pa

As a result, the wiring 22 embedded in the flat insulating layer 12 is formed. Also in the sixth embodiment, unlike the conventional method, the resist patterning process and the dry etching process of the metal wiring layer 20 are not necessary, and the problem of light scattering at the time of resist patterning and the problem of uneven etching can be avoided. it can. Further, it is not necessary to form an insulating film on the wiring and to flatten the insulating film.

(Embodiment 7) Embodiment 7 is a modification of Embodiment 6. Example 7 is different from Example 6 in that insulating layer 14
The removal of the upper metal wiring layer 20 and the barrier layer 18 is carried out by the chemical mechanical polishing method. Example 7
In the above, the steps up to [Step-630] of Example 6 are the same steps, and the subsequent steps are different.

[Step-700] to [Step-730] For example, the insulating layer 12 made of SiO ₂ is formed on the substrate 10 made of a semiconductor substrate, and then the groove portion 14 is formed in the insulating layer 12 by the photolithography technique and the dry etching technique. And then CV with a metal wiring material made of tungsten over the entire surface.
The groove portion 14 is deposited on the entire surface by the D method to form the groove 14 in the metal wiring layer 20.
Embed with. The above steps are the same as those in [Step-60 of Example 6].
0] to [Step-630].

[Step-740] Next, the metal wiring layer 2 on the insulating layer 12 is formed by the chemical mechanical polishing method.
0 and the barrier layer 18 are removed, and the metal wiring layer 20 and the barrier layer 18 are left in the groove portion 14 to form the wiring 22. This step can be the same as [Step-240] of Example 2. In this case, hydrogen peroxide solution (1% by weight) +
The chemical mechanical polishing method may be performed using a solution of (NH ₂ ) (CH ₂ ) ₂ (NH ₂ ) (1 wt%) + H ₂ O.

The method of forming the metal wiring layer made of tungsten in the groove portion 14 described in the sixth and seventh embodiments can be applied to the third, fourth and fifth embodiments. In this case, removal of the metal wiring layer 20 or the like on the insulating layer 12, removal of the first metal wiring layer 44 or the like on the interlayer insulating layer 38, or removal of the second metal wiring layer 20A or the like on the insulating layer 12 is not performed. Alternatively, it may be removed by an etch back method or a chemical mechanical polishing method.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The various materials and conditions used in the examples are examples,
It can be changed appropriately.

As the metal wiring material, for example, Cu, M
refractory metal such as o, Ni, Co, or TiW, Zr
W, WN, W, WC, TiC, other MoSi ₂ , WS
Silicide (high melting point metal compound) such as i ₂ and TiSi ₂ can be used. The film forming method of the metal wiring material is not limited to the embodiment, and other methods may be used. Further, as the Al-based alloy, pure Al, Al-Si-Cu, A
Al alloys such as l-Cu and Al-Ge can be mentioned.

Although the insulating layer 12 has been described as being made of SiO ₂ exclusively, BPSG, PS instead of SiO ₂ is used.
G, BSG, AsSG, PbSG, SbSG, SOG,
It can be composed of a known insulating material such as SiON or SiN, or a laminate of these interlayer insulating layers.

Further, TiON or TiW may be used instead of TiN forming the barrier layer. Further, the order of the groove formation, the sidewall formation, and the barrier layer formation may be changed to form the groove formation, the barrier layer formation, and the sidewall formation.

When the barrier layer has a structure of Ti layer / TiN, TiON or TiW layer / Ti layer, and when the order and process of forming the groove portion, forming the barrier layer, and forming the sidewall are changed, Instead of forming the side wall 16 made of SiN on the side wall of the groove portion 14, a side wall made of various insulating materials such as SiO ₂ may be formed in some cases. The fact that the Ti layer on the outermost surface of the barrier layer is oxidized by the insulating layer is described as TiN, TiON or T
This is because it can be avoided by the iW layer. In this case, the purpose of forming the sidewall on the sidewall of the groove is
This is to prevent the problem that the barrier property of the barrier layer becomes weak at the corners at the bottom of the groove portion 14 and the metal wiring layer formed later penetrates through this portion.

For example, Si formed by the TEOS method
When O ₂ is used, the conditions for forming the SiO ₂ layer and the etchback conditions can be set as follows. (In case of thermal CVD method) Used gas: TEOS = 50 sccm Pressure: 40 Pa Growth temperature: 720 ° C. Growth rate: 11 nm / min (In case of plasma CVD method) Used gas: TEOS = 50 sccm Pressure: 1300 Pa RF power : 350W Growth temperature: 250 ° C (SiO ₂ layer etch back) Working gas: CHF ₃ / O ₂ = 75/8 sccm Pressure: 5Pa power: 850W

As the substrate, in addition to a silicon semiconductor substrate or a semiconductor substrate having source / drain regions formed, a MgO substrate, a GaAs substrate, a superconducting transistor substrate, an insulating layer having a lower wiring layer formed, and a connection hole. (Contact holes, via holes, through holes), various element parts such as gate electrodes that need to form electrical connections, silicon layers formed on various substrates for manufacturing thin film transistors, and the like. it can.

In Example 5, the so-called blanket tungsten CVD method was used to form the tungsten plug in the opening 40. Instead, however, the so-called tungsten selective CVD method was used to form the tungsten plug in the opening 40. Good. The conditions in this case can be set as follows, for example. Gas used: WF ₆ / SiH ₄ / H ₂ / Ar = 10/7
/ 1000/10 sccm Temperature: 260 ° C Pressure: 26Pa

The method of the present invention is applicable to semiconductor devices other than MOS semiconductor devices (eg, bipolar transistor, C
It can also be applied to CD). Further, the metal layer or the metal compound layer forming the barrier layer of Ti, TiN or the like can be formed by a film forming method such as CVD.

The sputtering method can be performed by various sputtering devices such as a magnetron sputtering device, a DC sputtering device, an RF sputtering device, an ECR sputtering device, and a bias sputtering device for applying a substrate bias.

[0095]

According to the present invention, the patterning process of the metal wiring layer by the photolithography technique and the dry etching technique for forming the wiring is unnecessary. Therefore, it is possible to avoid irregular reflection of light in the conventional photolithography technique or nonuniformity of etching in dry etching.

Further, in the fabrication of a semiconductor device having fine wiring, the insulating layer including the wiring is completely formed without forming an insulating film formed on the wiring or polishing the insulating film as in the conventional case. Flattening is possible. Conventional Si
The O ₂ -based insulating film has poor selectivity in polishing because it has poor selectivity, but polishing of the metal wiring layer has high selectivity with respect to the insulating layer, so that the controllability of polishing is significantly improved.

Further, in order to leave the metal wiring layer only in the groove portion, by adopting the etch back by the chemical mechanical polishing method or the dry etching method, the conventional technique can be basically used as it is. There is no increase in manufacturing cost.

By forming a sidewall made of an insulating material in the groove, the groove can be stably filled by the high temperature aluminum sputtering method.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor device or the like for explaining each step of the method of Example 1.

FIG. 2 is a schematic view of a polishing apparatus suitable for carrying out the present invention.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor device or the like for explaining each step of the method of Example 3;

FIG. 4 is a schematic partial cross-sectional view of a semiconductor device or the like for explaining each step of the method of the third embodiment, following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of a semiconductor device or the like for explaining each step of the method of Example 4.

FIG. 6 is a schematic partial cross-sectional view of a semiconductor device or the like for explaining each step in a conventional manufacturing process example of a semiconductor element.

FIG. 7 is a schematic partial cross-sectional view of the semiconductor device or the like for explaining each step in the conventional manufacturing process example of the semiconductor element, following FIG. 6;

FIG. 8 is a schematic partial cross-sectional view of a semiconductor device or the like for explaining each step in another example of the conventional semiconductor element manufacturing process.

FIG. 9 is a diagram for explaining a problem in a conventional semiconductor element manufacturing process.

[Explanation of symbols]

 10 Base 12 Insulation Layer 14 Groove 16 Sidewall 18 Barrier Layer 18A Second Barrier Layer 20 Metal Wiring Layer 20A Second Metal Wiring Layer 22 Wiring 30 Element Isolation Region 32 Gate Region 34 Gate Sidewall 36 Source / Drain Region 38 Interlayer Insulating layer 40 Opening 42 First barrier layer 44 First metal wiring layer 50 Barrier layer 52 Metal wiring layer 54 Antireflection film 56 Wiring 60 First insulating layer 62 Stopper layer 64 Second insulating layer 70 Insulating layer 72 Resist

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 21/302 F 21/90 P 7514-4M

Claims (9)

[Claims] 1. A step of forming a groove in the insulating layer after forming an insulating layer on a substrate, a step of forming a metal wiring layer on the insulating layer including the inside of the groove, and a metal wiring on the insulating layer. A method of forming a wiring of a semiconductor device, comprising the step of removing the layer and leaving the metal wiring layer in the groove as wiring. 2. The method further comprises the step of forming a side wall made of an insulating material on the side wall of the groove after the groove is formed in the insulating layer, and the step of forming the metal wiring layer includes aluminum or aluminum while the substrate is heated to a high temperature. The method for forming a wiring of a semiconductor device according to claim 1, comprising a step of sputtering an aluminum alloy. 3. The method for forming a wiring of a semiconductor device according to claim 1, wherein the step of forming the metal wiring layer comprises a CVD method of a refractory metal or a refractory metal compound. 4. The step of removing the metal wiring layer on the insulating layer comprises:
4. The method for forming a wiring of a semiconductor device according to claim 1, comprising a step of etching back the metal wiring layer. 5. The step of removing the metal wiring layer on the insulating layer comprises:
4. The method according to claim 1, comprising a chemical mechanical polishing step of the metal wiring layer.
Item 5. A method for forming wiring of a semiconductor device according to item. 6. The method further comprises the step of forming an interlayer insulating layer on the substrate before forming the insulating layer on the substrate, wherein the step of forming a groove in the insulating layer forms an opening in the interlayer insulating layer. And the width of the groove is larger than the diameter of the opening, and in the step of forming the metal wiring layer on the insulating layer including the inside of the groove, forming the metal wiring layer also inside the opening. The wiring forming method for a semiconductor device according to claim 1, wherein the wiring is formed. 7. An interlayer insulating layer is formed on a substrate before forming an insulating layer on the substrate, an opening is formed in the interlayer insulating layer, and then the opening is filled with a metal wiring material to make connection. The method for forming a wiring of a semiconductor device according to claim 1, further comprising a step of forming a hole, wherein a width of the groove is larger than a diameter of the opening. 8. The step of filling the opening with a metal wiring material comprises:
8. The method for forming a wiring of a semiconductor device according to claim 7, comprising the step of sputtering aluminum or an aluminum-based alloy while the substrate is heated to a high temperature. 9. The step of filling the opening with a metal wiring material comprises:
8. The method for forming a wiring of a semiconductor device according to claim 7, comprising a CVD method of a high melting point metal or a high melting point metal compound.