JP3380923B2 - Method of forming wiring structure in semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring structure in a semiconductor device.

[0002]

2. Description of the Related Art With the progress of high integration of semiconductor devices, the demand for fine processing technology is becoming more and more severe. The dry etching technology in the manufacturing process of semiconductor devices is no exception, and various studies are being carried out with the aim of highly accurate processing.

In a semiconductor device composed of MOS transistors, a large number of contact holes, via holes or through holes (hereinafter also collectively referred to as connection holes) are formed. For example, the contact hole is formed through the following steps.

First, a gate electrode and source / drain regions are formed on a silicon semiconductor substrate, and then an insulating layer made of silicon dioxide is formed on the entire surface. Then, after forming an opening in the insulating layer by using a photolithography technique and a dry etching technique, a wiring layer is formed in the opening and on the insulating layer, and then the wiring layer is patterned into a desired pattern shape. As a result, wiring is formed on the insulating layer. Further, a contact hole in which the wiring layer is embedded is formed in the opening. The source / drain region and the wiring on the insulating layer are electrically connected by a contact hole.

When forming a fine opening, the exposure light may be reflected on the surface of the insulating layer during the exposure of the resist layer in the photolithography technique, so that an accurate opening forming pattern may not be formed in the resist layer. is there. In recent years, attention has been paid to a technique of forming an antireflection film in order to prevent such exposure light from being reflected on the surface of the insulating layer.
That is, for example, after forming an antireflection film made of SiON having a thickness of 30 nm on the surface of the insulating layer, a resist layer is formed on the antireflection film, and an opening is formed in the insulating layer by using photolithography technology and dry etching technology. Form. As a result, a fine resist pattern can be formed with high accuracy.

[0006]

SiON itself has a Si-rich composition, and its withstand voltage is not very high. Therefore, if the antireflection film left on the surface of the insulating layer is not removed after the opening is formed, current leakage may occur due to the antireflection film left on the surface of the insulating layer after the connection hole is completed. . Therefore, it is usually necessary to remove the antireflection film left on the surface of the insulating layer after forming the opening and before forming the wiring layer. However, an appropriate method for removing the antireflection film made of SiON from the surface of the insulating layer has not been established at present.

Even if an appropriate method of removing the antireflection film made of SiON from the surface of the insulating layer is established, after forming the opening 24 as shown in FIG.
When removing the antireflection film 22 left on the surface of the insulating layer 20, the silicon semiconductor substrate 1 is formed at the bottom of the opening 24.
The source / drain regions (impurity diffusion regions) 18 formed at 0 are exposed. Therefore, when the antireflection film 22 is removed by etching, the source / drain regions 18 are also etched, and the reliability of the semiconductor device is lowered.

Therefore, an object of the present invention is to reliably remove the antireflection film left on the surface of the insulating layer without damaging, for example, the source / drain regions (impurity diffusion regions) existing at the bottom of the opening. Another object of the present invention is to provide a method of forming a wiring structure which can be realized.

[0009]

A method for forming a wiring structure in a semiconductor device according to a first aspect of the present invention for achieving the above object is as follows: (a) An insulating layer on a substrate made of silicon as a constituent material. And then forming an antireflection film made of SiON on the insulating layer, (b) forming an opening in the antireflection film and the insulating layer, and (c) forming a metal plug in the opening. And (d) a step of removing the antireflection film on the insulating layer, and (e) a step of forming a wiring layer on the insulating layer including the opening.

In the semiconductor device according to the first aspect of the present invention, the antireflection film can be removed by a dry etching method using chlorine gas or a gas containing chlorine. The metal plug is preferably made of tungsten. In this case, the metal plug can be formed by the selective tungsten CVD method or the blanket tungsten CVD method.

A second aspect of the present invention for achieving the above object.
A method of forming a wiring structure in a semiconductor device according to the aspect of (1) includes a step of: (a) forming an insulating layer on a substrate made of silicon and then forming an antireflection film made of SiON on the insulating layer; (B) a step of forming an opening in the antireflection film and the insulating layer, (c) a step of forming a wiring layer in the opening and on the antireflection film, and (d) a wiring layer and an antireflection film on the insulating layer. And a step of forming a wiring by selectively removing the wiring.

In the semiconductor device according to the second aspect of the present invention, the antireflection film can be removed by a dry etching method using chlorine gas or a gas containing chlorine. Further, the wiring layer can be formed of an aluminum alloy, a laminated structure of tungsten and an aluminum alloy, or tungsten.

[0013]

In the present invention, at the time of removing the antireflection film, the bottom of the opening is covered with the metal plug or the wiring layer, and the state where the substrate made of silicon as a constituent material is exposed at the bottom of the opening is avoided. be able to. Therefore, when removing the antireflection film, it is possible to reliably prevent the source / drain regions (impurity diffusion regions) existing at the bottom of the opening from being damaged by the etching gas.

[0014]

EXAMPLES A method of forming a wiring structure in a semiconductor device of the present invention will be described below based on examples.

Example 1 Example 1 relates to a method for forming a wiring structure according to the first aspect of the present invention. The metal plug is made of tungsten, so-called selective tungsten CVD
Is formed by the method. Example 1 will be described below with reference to FIGS. 1, 2 and 3 which are schematic partial cross-sectional views of a semiconductor element.

[Step-100] First, a gate oxide film 12 made of silicon dioxide (SiO ₂ ) and having a thickness of 10 nm is formed on the surface of a silicon semiconductor substrate 10 which is a base body made of silicon by a thermal oxidation method, for example. After that, a gate electrode 14 made of n ⁺ polysilicon 14A and tungsten silicide 14B is formed on the gate oxide film 12 by a conventional method. Next, after performing the LDD ion implantation, the gate sidewalls 16 made of silicon dioxide are formed on the sidewalls of the gate electrode 14 by the conventional method, and then the impurity ion implantation is performed to form the source / drain regions 1.
8 is formed. After that, an insulating layer 20 made of silicon dioxide is formed on the entire surface by a conventional CVD method (see FIG. 1A). The conditions for forming the insulating layer 20 are exemplified below. Gas used: SiH ₄ / O ₂ / N ₂ = 250/250
/ 100sccm Substrate temperature: 420 ° C Pressure: 13.3Pa Film thickness: 0.8μm

[Step-110] Next, an antireflection film 22 made of SiON having a thickness of 30 nm is formed on the insulating layer 20 by the plasma CVD method (see FIG. 1B). S
The film forming conditions of iON can be set as follows, for example. Gas used: SiH ₄ / N ₂ O = 50/40 sccm Substrate temperature: 360 ° C Pressure: 3.3 × 10 ² Pa Film thickness: 30 nm

[Step-120] After that, the opening 24 is formed in the antireflection film 22 and the insulating layer 20 by using the photolithography technique and the dry etching technique (see FIG. 1C). To form the opening 24, for example, E
The antireflection film 22 and the insulating layer 20 are dry-etched using a CR plasma etching device, and the conditions thereof can be set as follows, for example. Gas used: C ₄ F ₈ / CH ₂ F ₂ = 60 / 20sc
cm Substrate temperature: -50 ° C Microwave power: 80W RF bias: 300W (800KHz)

Since the antireflection film 22 made of SiON has a composition rich in Si, the etching rate is slower by about 1/2 as compared with silicon dioxide. Therefore, (C) of FIG.
As shown in FIG. 5, the sidewall of the antireflection film 22 after etching is slightly inclined, but the opening 24 is formed under the above dry etching conditions. In this state, the source / drain region 18 is exposed at the bottom of the opening 24.

[Step-130] Next, the metal plug 26 is formed in the opening 24 (see FIG. 2A). The metal plug 26 is made of tungsten and is formed by the so-called selective tungsten CVD method. Select tungsten CV
The conditions for forming the metal plug 26 by the D method are illustrated below. Gas used: WF ₆ / SiH ₄ / H ₂ = 10/6/1
000sccm Substrate temperature: 260 ° C Pressure: 10Pa

As shown in FIG. 2A, the metal plug 26 may be formed so that the bottom of the opening 24 is surely covered. A metal plug may be formed so as to almost fill the opening 24. As a result, the opening 2
The bottom of 4 is completely covered with the metal plug 26, and the source / drain region 18 is not exposed.

Instead of the selective tungsten CVD method, the metal plug 26 is replaced by a so-called blanket tungsten CVD method.
It may be formed by a method. In this case, first, a tungsten layer is formed on the entire surface of the insulating layer 20 including the opening 24 by the CVD method, and then the tungsten layer is entirely etched back to leave a metal plug made of tungsten in the opening 24. In this case, the antireflection film 22 may be left on the insulating layer 20.

[Step-140] Next, the antireflection film 22 on the insulating layer 20 is removed (see FIG. 2B). Si
The dry etching conditions for the antireflection film 22 made of ON are exemplified below. Gas used: Cl ₂ = 80 sccm Substrate temperature: 20 ° C Pressure: 0.4 Pa Microwave power: 850 W RF bias: 300 W (800 KHz)

Since Cl ₂ is used as an etching gas, the insulating layer 20 made of silicon dioxide and the metal plug 26 made of tungsten are hardly etched, and the antireflection film 22 made of SiON having a Si-rich composition is insulated. Removed from above layer 20.

[0025] As etching gas, in place of Cl _2, it is also possible to use a mixed gas of Cl ₂ and C ₄ F _8.
Since Si—O bonds are present in the antireflection film 22, C
The etching rate of SiON with l ₂ gas is slow, and the throughput is reduced. On the other hand, by using a mixed gas of Cl ₂ and C ₄ F ₈ , formation of CO molecules can be promoted,
The etching rate of the antireflection film 22 made of SiON can be improved. The dry etching conditions with such a mixed gas are exemplified below. Gas used: Cl ₂ / C ₄ F ₈ = 75 / 5sccm Substrate temperature: 20 ° C Pressure: 0.4Pa Microwave power: 850W RF bias: 300W (800KHz)

[Step-150] After that, for example, Al-
A wiring layer 28 is formed on the insulating layer 20 including the openings 24 by a sputtering method using an aluminum alloy containing 1% Si (see FIG. 2C). Then, the wiring layer 28 made of an aluminum-based alloy is selectively etched,
The wiring 30 is formed on the insulating layer 20 (see FIG. 3). Thus, the insulating layer 20 is formed with the connection hole (contact hole) 32 in which the metal plug 26 and the wiring layer 28 made of an aluminum alloy are embedded. Further, the wiring 30 made of an aluminum alloy is formed on the insulating layer 20 including the opening 24. When most of the openings 24 are filled with the metal plugs 26, a connection hole (contact hole) 32 in which the metal plugs 26 are embedded is formed in the insulating layer 20, while the openings 24 are formed. A wiring 30 made of an aluminum-based alloy is formed on the insulating layer 20 including the wiring 30.

Example 2 Example 2 relates to a method for forming a wiring structure according to the second aspect of the present invention. The wiring layer is made of an aluminum alloy and is formed by a so-called high temperature aluminum sputtering method. Example 2 will be described below with reference to FIG. 4, which is a schematic partial cross-sectional view of a semiconductor element.

[Step-200] First, as in [Step-100] of the first embodiment, the surface of the silicon semiconductor substrate 10 which is a substrate whose constituent material is silicon is made of silicon dioxide by, for example, a thermal oxidation method. After forming the gate oxide film 12 having a thickness of 10 nm, the gate electrode 14 is formed on the gate oxide film 12 by a conventional method. Next, after performing LDD ion implantation, a gate sidewall 16 made of silicon dioxide is formed on the sidewall of the gate electrode 14 by a conventional method, and then impurity ion implantation is performed to form source / drain regions 18. . After that, an insulating layer 20 made of silicon dioxide is formed on the entire surface by a conventional CVD method.

[Step-210] Then, in the same manner as in [Step-110] of Example 1, a thickness of 3 is formed on the insulating layer 20.
The antireflection film 22 made of 0 nm SiON is used for plasma C
It is formed by the VD method.

[Step-220] After that, the opening 24 is formed in the antireflection film 22 and the insulating layer 20 by the photolithography technique and the dry etching technique in the same manner as in [Step-120] of the first embodiment. (See FIG. 4A). In this state, the source / drain region 18 is exposed at the bottom of the opening 24.

[Step-230] Next, the wiring layer 42 is formed in the opening 24 and on the antireflection film 22 (see FIG. 4B). The wiring layer 42 is made of an aluminum alloy and can be formed by a so-called high temperature aluminum sputtering method. The wiring layer 42 made of an aluminum alloy
The Ti layer / TiN layer / Ti layer before opening 2
4 and on the antireflection film 22.
The lowermost Ti layer is formed for the purpose of reducing the contact resistance between the aluminum-based alloy in the opening and the source / drain region 18. The TiN layer functions as a barrier layer for preventing the aluminum-based alloy in the opening from penetrating into the source / drain region 18. Also,
The uppermost Ti layer is formed for the purpose of improving wettability when forming an aluminum-based alloy film. In addition, in FIG. 4B, these three layers are collectively represented by one layer and a reference numeral 40 is attached to simplify the drawing. In addition, hereinafter, these three layers are collectively referred to as a base layer 40. The film forming conditions for each of these layers by the sputtering method are illustrated below. Ti layer forming target: Ti process gas: Ar = 100 sccm Power: 4 kW Pressure: 0.47 Pa Film forming temperature: 150 ° C Film thickness: 50 nm TiN layer forming target: Ti process gas: Ar / N ₂ = 40/70 sccm Power: 5 kW Pressure: 0.47 Pa Film thickness: 70 nm Target for forming wiring layer 42 made of aluminum alloy: Al-1% Si process gas: Ar = 100 sccm DC power: 10 kW Sputtering pressure: 0.4 Pa Substrate heating temperature: 500 ° C Deposition rate: 600 nm / min

The wiring layer can be formed by a so-called aluminum reflow method instead of the high temperature aluminum sputtering method. In this case, the wiring layer 42 made of the above aluminum-based alloy may be formed under the following conditions. Process gas: Ar = 100 sccm DC power: 20 kW Sputtering pressure: 0.4 Pa Substrate heating temperature: 150 ° C. Deposition rate: 1200 nm / min After that, the substrate temperature is heated to about 500 ° C. As a result, the aluminum-based alloy deposited on the underlayer 40 becomes fluid and flows into the opening 24, and the opening 24 is reliably filled with the aluminum-based alloy. The heating conditions can be set as follows, for example. Heating method: Substrate backside gas heating Heating temperature: 500 ° C Heating time: 2 minutes Process gas: Ar = 100 sccm Process gas pressure: 1.1 × 10 ³ Pa Here, the substrate backside gas heating method is arranged on the backside of the substrate. In this system, the heater block is heated to a predetermined temperature (heating temperature) and the process gas is introduced between the heater block and the back surface of the substrate to heat the substrate. As the heating method, other than this method, a lamp heating method or the like can be used.

[Step-240] After that, the wiring layer 42, the underlayer 40 and the antireflection film 22 on the insulating layer 20 are selectively removed (see FIG. 4C). Thus, the underlayer 40
And a connection hole (contact hole) in which the wiring layer 42 made of aluminum-based alloy is buried is formed in the insulating layer 20. On the other hand, the patterned wiring layer 42 and the underlying layer 4
A wiring including 0 and the antireflection film 22 is formed on the insulating layer 20. Wiring layer 42, base layer 40 and antireflection film 2
The dry etching conditions of No. 2 can be set as follows, for example. Gas used: BCl ₃ / Cl ₂ = 30 / 50sccm Substrate temperature: 20 ° C Pressure: 1Pa Microwave power: 850W RF bias: 40W (2MHz)

At the time of dry etching the antireflection film 22, the bottom of the opening 24 is already covered with an aluminum alloy or the like, and the source / drain region 18 is surely prevented from coming into contact with the etching gas. can do.

In the [Step-240], the wiring layer 42 is formed by the high temperature aluminum sputtering method, but instead, the wiring layer can be formed by the so-called blanket tungsten CVD method. In this case, a barrier layer composed of a Ti layer / TiN layer is previously formed from below on the opening 24 and the insulating layer 20 by a sputtering method, and a tungsten layer is deposited on the entire surface of the barrier layer by a CVD method. The conditions for forming the tungsten layer can be set as follows, for example. First step (nucleation stage) Gas used: WF ₆ / SiH ₄ / Ar = 5/3/200
0 sccm pressure: 4 × 10 ² Pa (3 Torr) substrate temperature: 450 ° C. second step (high speed growth stage) working gas: WF ₆ / H ₂ / Ar = 40/400/22
50 sccm pressure: 1.1 × 10 ⁴ Pa (80 Torr) substrate temperature: 450 ° C

Next, the wiring layer made of tungsten, the barrier layer and the antireflection film 22 on the insulating layer 20 are selectively removed. As a result, similarly to the structure shown in FIG. 4C, a connection hole (contact hole) in which the barrier layer and tungsten are buried is formed in the insulating layer 20, and at the same time, the patterned tungsten, barrier layer, and Wiring made of an antireflection film is formed on the insulating layer 20. Wiring layer, barrier layer and antireflection film 2 made of tungsten
The dry etching conditions of No. 2 can be set as follows, for example. Gas used: SF ₆ = 100sccm Substrate temperature: 0 ° C Pressure: 1Pa Microwave power: 850W

The wiring layer made of tungsten is entirely etched back, the barrier layer and the antireflection film 22 on the insulating layer 20 are removed at the same time, and a metal plug made of tungsten and the barrier layer is formed in the opening 24. After that, a wiring layer made of an aluminum-based alloy may be formed on the insulating layer 20 and the metal plug by, for example, a sputtering method.

Alternatively, after a second wiring layer made of an aluminum alloy is formed on the wiring layer made of tungsten by, for example, a sputtering method, a wiring layer made of aluminum and tungsten, a barrier layer, and an antireflection film on the insulating layer 20 are formed. The film 22 may be selectively removed. by this,
The wiring layer can be formed of a laminated structure of an aluminum alloy and tungsten.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The film forming conditions and numerical values in each example are merely examples, and can be changed as appropriate. The insulating layer 20 is SiO
Other than ₂ , BPSG, PSG, BSG, AsSG, P
It can be made of a known insulating material such as bSG, SbSG, or SiN. For aluminum alloys,
Pure Al, or Al-Si-Cu, Al-Cu, Al
Aluminum alloys such as Ge are included.

As the substrate made of silicon as a constituent material,
Not only the silicon semiconductor substrate but also a lower wiring layer made of polysilicon formed on an insulating layer, various electrodes, and the like can be mentioned. The underlayer and barrier layer used when forming the aluminum-based alloy or tungsten are the examples (Ti layer / TiN layer / Ti layer or Ti layer / Ti) described in the examples.
The number of layers is not limited to (N layer) and can be changed as appropriate. Further, these underlayer and barrier layer can be formed not only by the sputtering method but also by the CVD method. Furthermore, although the aluminum-based alloy and tungsten have been described as examples of the material forming the wiring layer, the present invention is not limited to these materials, and various metal materials such as copper and refractory metal materials can be used.

The formation of various layers by the sputtering method can be performed by various sputtering devices such as a magnetron sputtering device, a DC sputtering device, an RF sputtering device, an ECR sputtering device, and a bias sputtering device for applying a substrate bias.

[0042]

According to the method of forming a wiring structure of the present invention,
After forming the opening in the insulating layer, remove the antireflection film left on the surface of the insulating layer without damaging, for example, the source / drain region (impurity diffusion region) or the lower wiring layer existing at the bottom of the opening. It can be reliably removed. Therefore,
It is possible to form a wiring structure having high reliability.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of a method for forming a wiring structure of Example 1.

2 is a schematic partial cross-sectional view of the semiconductor element, for explaining each step of the method for forming the wiring structure of Example 1, following FIG. 1; FIG.

FIG. 3 is a schematic partial cross-sectional view of the semiconductor element for explaining each step of the method for forming the wiring structure of Example 1, following FIG.

FIG. 4 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of the method for forming a wiring structure of Example 2.

FIG. 5 is a schematic partial cross-sectional view of a semiconductor element for explaining problems in a conventional wiring structure forming method.

[Explanation of symbols]

10 Semiconductor substrate 12 Gate oxide film 14 Gate electrode 16 gate sidewall 18 Source / Drain region 20 insulating layer 22 Anti-reflection film 24 opening 26 Metal plug 28 wiring layers 30 wiring 32 connection hole 40 Underlayer 42 wiring layer

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (9)

(57) [Claims] 1. A (a) forming an insulating layer on a substrate a silicon constituent materials, an antireflection film made of SiON is formed on the insulating layer, (ii) Then, the antireflection film and the insulating Forming an opening in a layer
And, (c) Thereafter, the metal plug is formed in the opening portion, (d) then removing the antireflection film on the insulating layer, (e) then forming a wiring layer on an insulating layer comprising an opening to to a method for forming a wiring structure in a semiconductor device comprising a call. 2. The method for forming a wiring structure in a semiconductor device according to claim 1, wherein the antireflection film is removed by a dry etching method using chlorine gas or a gas containing chlorine. 3. The method for forming a wiring structure in a semiconductor device according to claim 1, wherein the metal plug is made of tungsten. 4. The metal plug is selected tungsten CVD
The method for forming a wiring structure in a semiconductor device according to claim 3, wherein the wiring structure is formed by a method. 5. The method for forming a wiring structure in a semiconductor device according to claim 3, wherein the metal plug is formed by a blanket tungsten CVD method. 6. (a) forming an insulating layer on a substrate a silicon constituent materials, an antireflection film made of SiON is formed on the insulating layer, (ii) Then, the antireflection film and the insulating Forming an opening in a layer
And, (c) Thereafter, a wiring layer is formed to the opening portion and the anti-reflection film to form a wiring by selectively removing the (d) Then, the wiring layer and the antireflection film on the insulating layer, this And a method for forming a wiring structure in a semiconductor device. 7. The method for forming a wiring structure in a semiconductor device according to claim 6, wherein the antireflection film is removed by a dry etching method using chlorine gas or a gas containing chlorine. 8. The method for forming a wiring structure in a semiconductor device according to claim 6, wherein the wiring layer is made of an aluminum alloy or a laminated structure of tungsten and an aluminum alloy. 9. The method for forming a wiring structure in a semiconductor device according to claim 6, wherein the wiring layer is made of tungsten.