JPH05258475A - Data detecting device - Google Patents

Abstract

PURPOSE:To correct the phase deviation component of a reproducing clock with one bit unit of data and to realize a highly precise decoding in the case of reproducing digital signals. CONSTITUTION:Based on the signal level of a sampling point by means of the reproducing clock with one bit unit of data that is generated by PLL circuits 6a, 6b and a reproducing clock with data twice as much as the above clock, the phase deviation component of the clock is detected through a phase deviation detector 24 and a phase deviation compensator 25; and the reproducing signal level is corrected in accordance with this phase deviation component thus detected. Only for the phase deviation component that is highly liable to appear comparatively regularly, such correcting process is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data detecting apparatus used in a magnetic recording / reproducing apparatus for recording / reproducing a digital signal and converting the reproduced signal into a digital signal having an original value level.

[0002]

2. Description of the Related Art As a conventional magnetic recording / reproducing apparatus of this type, recording is performed by combining a partial response CLASS IV method (hereinafter referred to as PR 4 method) and a Viterbi decoding method in recording / reproduction of a digital VTR (hereinafter referred to as D-VTR). There is an example to improve the density. This example makes use of the band-pass type frequency characteristic of the PR 4 system and the high error correction capability of the Viterbi decoding method. In such an example as well, like the other digital magnetic recording / reproducing apparatus, the reproduction signal data is detected from the reproduction signal by the reproduction clock generated by the PLL circuit or the like.

FIG. 1 is a block diagram showing the configuration of a conventional magnetic recording / reproducing apparatus for a D-VTR disclosed in, for example, Japanese Patent Laid-Open No. 3-16063. In the figure, 50 is a magnetic tape as a magnetic recording medium, and 2 is a rotary head for recording and reproducing signals on the magnetic tape. Further, in the figure, 3,20 to 23 indicate constituent members of the recording system, and 1,4 to 19 indicate constituent members of the reproducing system.

The recording system includes an A / D converter 20 for digitizing an input analog video signal and a data compression circuit 21 for compressing the digitized video data by DCT (discrete cosine transform) or the like. , ECC with error correction code
It has an (error correction code) circuit 22, a pre-code circuit 23 for band limiting the recording signal in accordance with the PR 4 system, and an amplifier 3 for amplifying the recording signal.

In the reproducing system, 1 is an amplifier for amplifying the reproduced signal reproduced from the magnetic tape 50 by the rotary head 2, and the amplifier 1 outputs the amplified reproduced signal to the equalizer circuit 4. The equalizer circuit 4 performs waveform equalization processing on the reproduced signal and outputs the processed reproduced signal to a PLL (Phase Locked).
Loop) circuit 6a, arithmetic processing circuit 5, envelope detection circuit
Output to 11. The PLL circuit 6a generates and outputs a reproduction clock based on the input reproduction signal. The arithmetic processing circuit 5 performs (1 + D) (D: 1-bit delay operator) processing on the reproduction signal to create a PR 4 type detection signal, which is then processed by the A / D converter 7 and the envelope detection circuit 12 Output to.
The A / D converter 7 converts the reproduced signal after the arithmetic processing into digital data and outputs it to the selection circuit 8. The selection circuit 8 is A /
The output of the D converter 7 is divided into an even number column and an odd number column and output to the Viterbi decoding circuits 9 and 10, respectively.

The envelope detection circuit 11 envelope-detects the reproduction signal output from the equalizer circuit 4, and outputs the envelope detection signal to the comparison circuit 13. The comparison circuit 13 compares the input envelope detection signal with a predetermined reference level, and outputs the comparison result to the exclusive OR circuit 15a and the exclusive OR circuit 15b. On the other hand, the envelope detection circuit 12 envelope-detects the reproduction signal after the arithmetic processing from the arithmetic processing circuit 5, and outputs the envelope detection signal to the comparison circuit 14. The comparison circuit 14 compares the input envelope detection signal with a predetermined reference level and outputs the comparison result to the exclusive OR circuit 15a. Exclusive OR circuit 15
a obtains the exclusive OR of both comparison results and outputs it to the exclusive OR circuit 15b and the PLL circuit 6a. The PLL circuit 6a generates the reproduction clock as described above in synchronization with the output from the exclusive OR circuit 15a. The exclusive OR circuit 15b obtains the exclusive OR of the output of the exclusive OR circuit 15a and the comparison result from the comparison circuit 13 and outputs it to the Viterbi decoding circuits 9 and 10.

The selection circuit 16 selects the reproduced data of the even columns from the Viterbi decoding circuit 9 and the reproduced data of the odd columns from the Viterbi decoding circuit 10 and combines them, and the combined reproduced data is an error detection / correction circuit. Output to 17. Error detection / correction circuit
The error decompression circuit 17 performs error detection, error correction, correction, etc., and the data decompression circuit 18 performs decompression processing for restoring the compressed data to the original state. Output to the A converter 19. The D / A converter 19 converts the digital reproduction data into an analog signal and outputs the original video signal.

Next, the operation will be described. First, the operation during recording will be described. After the video signal input to the A / D converter 20 is quantized, the data compression circuit 21 performs time axis compression, and the ECC circuit 22 adds a code for correcting errors on the transmission path. And output to the precoding circuit 23. The video signal to be recorded which has been precoded by the precoding circuit 23 is recorded on the magnetic tape 50 from the amplifier 3 via the rotary head 2.

Next, the operation during reproduction will be described. The digital data recorded on the magnetic tape 50 is read out to the amplifier 1 through the rotary head 2. The output of the amplifier 1 is equalized in waveform by the equalizer circuit 4, and then the output of the arithmetic processing circuit 5 and PL
It is output to the L circuit 6a. The PLL circuit 6a generates a reproduction clock in bit units of data according to the reproduction signal. In the arithmetic processing circuit 5, the output of the equalizer circuit 4 is (1 + D) processed by the reproduction clock generated by the PLL circuit 6a and output to the A / D converter 7. The data quantized by the A / D converter 7 based on the reproduction clock is divided into even and odd columns by the selection circuit 8, and the Viterbi decoding circuits 9 and 10 in the envelope detection circuit 1
Decoding is carried out on the basis of the control signals obtained by 1, 12 and the comparison circuits 13, 14 and the reproduced clock. Note that the differential characteristic 1 / (1-D) by the electromagnetic conversion system added when reproducing from the magnetic tape 50 and 1 / (1 + D) added by the analog 1-bit delay / addition process in the arithmetic processing circuit 5 By the above characteristic, the characteristic (1-D ² ) added at the time of pre-coding is canceled, so that the decoded data is in the form of the recording code as it is.

The Viterbi decoding function by the Ferguson algorithm used in the Viterbi decoding circuits 9 and 10 will be described. The Viterbi decoding circuits 9 and 10 utilize the fact that even-numbered columns and odd-numbered columns of the signal sequence can be treated independently as a characteristic of the PR 4 type reproduction signal, and this reproduction signal is divided into even and odd-numbered columns. Are independently decoded. Also,
By doing so, the data rate can be doubled in the decoded signal processing that requires high-speed processing.

FIG. 2 is a diagram showing the level of the reproduced signal and the zero-cross points included in the reproduced signal. In Figure 2, "
+1 "," - 1 "represents the signal level, a, b, c are the sampling _{points, V a, V b, V} c is the received level at each sampling point, A, B, C are Zerokukurosu The reproduced signal is a signal of three levels as shown in Fig. 2. The initial value of "probability data" is 0.
The value of "probability data" at each time point is sequentially determined by the calculation described below. ΔK _J-1 −Y _J ΔK _J-1 : “Probability data” at time point (J-1) Y _J : Received data at time point J ΔK _J-1 −Y _J is a parameter that determines the state parameter S _J , Determine S _J as follows:

S _J = 1 (ΔK _J-1 −Y _J > 1) S _J = 0 (−1 <ΔK _J−1 −Y _J <1) S _J = −1 (ΔK _J−1 −Y _J < -1)

The "probability data" ΔK _J at time _{J according} to the state parameter S _J is ΔK _J = Y _J-1 +1 (S _J = 1) ΔK _J = ΔK _J-1 (S _J = 0) ΔK _J = = Y _J-1 -1 (S _J = -1), and the state parameter S _J is sequentially determined by repeating such processing. By the series of state parameters S _J thus determined, as shown in FIG. 3A, the state transition of 1 → 1 or 1 → 0 for reception (S _J = 1) 0 → 0 or 1 for reception → 1 state transition (S _J = 0) Receiving is judged as a 0 → 0 or 0 → 1 state transition (S _J = −1) and the surviving path is determined. Then, as shown in FIG. 3 (b), one of the two surviving paths is selected as the surviving path from these continuous connected states on the trellis diagram, and the decoded data = 0 (transition of S _J is 1 → 1 or 0 → 0) Decoded data = 1 (when S _J transition is 1 → 0) Decoded data = −1 (when S _J transition is 0 → 1) Decoding is performed.

According to the above-mentioned algorithm, the reproduction signals are independently decoded in the Viterbi decoding circuits 9 and 10 for the even and odd columns, and the reproduction data of the even and odd columns are combined in the selection circuit 16 to obtain the data before division. Is returned to the original array of. The combined reproduction data is subjected to signal processing by the error detection / correction circuit 17 and the data expansion circuit 18, and the original analog video signal is output from the D / A converter 19.

[0015]

The conventional magnetic recording / reproducing apparatus is constructed as described above, and the reproduction signal is sampled and processed based on the reproduction clock generated by the PLL circuit to have a high error correction capability. By adopting the Viterbi decoding method which has, high density magnetic recording is achieved. In addition,
The Viterbi decoding method is the maximum likelihood decoding of the received reproduced signal based on the state of the received signal at a time point before that time point.
This method is effective for random noises such as white noise, but the waveform distortion and PLL peculiar to electromagnetic conversion systems
It has little effect on steady phase error such as. FIG. 4 shows the result of simulating the relationship between sampling points and decoding errors. As can be seen from FIG. 4, in the Viterbi decoding method based on Ferguson's algorithm, the bit error rate rapidly increases as the deviation from the sampling point increases. Need to be decrypted by This is because the "probability data" for determining the state parameter S _J depends on the received signal level, and steady phase deviation directly affects the "probability data". In particular, the influence of the phase shift is doubled when the received signal level is inverted in polarity.

The present invention has been made in view of such circumstances, and a magnetic recording capable of performing accurate decoding by detecting a phase shift of a data detection point due to a reproduction clock generated by a PLL circuit. An object of the present invention is to provide a data detection device in a reproducing device.

[0017]

A data detecting apparatus according to the present invention comprises a PLL means for generating a reproduction clock of a multiple of the reproduction data rate and an integral multiple of the reproduction data rate, and the reproduction data is sampled and quantized by the reproduction clock. It is characterized by comprising A / D conversion means and means for detecting a phase shift from the ideal sampling point with respect to the reproduced data and predicting the signal level at the ideal sampling point.

[0018]

In the data detecting apparatus of the present invention, the reproduction clock generated by the reproduction clock generating means and the signal level at the sampling point by the reproduction clock having a cycle of an integral multiple of this reproduction clock are used. The phase shift component is detected, and the decoded signal level is corrected according to the detected phase shift component. This way,
When decoding is performed based on this corrected signal level by, for example, the Viterbi decoding method, highly accurate decoding is performed in an ideal reception state, and the error rate at the time of decoding is low.

Further, if a random phase shift having a short fluctuation period such as white noise or jitter is cut and a steady phase shift is detected, the drawback of the phase shift correction in the Viterbi decoding method can be solved. The steady phase shift such as the waveform distortion peculiar to the electromagnetic conversion system is corrected.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments thereof.

FIG. 5 is a block diagram showing the structure on the reproducing side of a magnetic recording / reproducing device incorporating the data detecting device according to the present invention. The magnetic tape, the magnetic head, and the recording system are the same as those in the conventional example, and therefore these are not shown. Note that, in FIG. 5, the same reference numerals as those in FIG. 1 denote the same parts.

In the figure, 6a and 6b are equalizer circuits 4 respectively.
A PLL circuit that generates a reproduction clock in 1-bit units of data (that is, 1 times the data rate) according to the output of
A reproduction clock (1/2 of this reproduction clock)
This is a PLL circuit that generates the recovered clock. The A / D converter 7 is based on the 1/2 reproduction clock from the PLL circuit 6b,
The output of the arithmetic processing circuit 5 is quantized, and the phase shift detector 24
Output to. The phase shift detector 24 detects the phase shift data from the quantized data from the A / D converter 7, and outputs the detected phase shift data to the phase shift corrector 25. The phase shift corrector 25 corrects the quantized data from the A / D converter 7 based on the phase shift data, and outputs the corrected data to the selection circuit 8. The selection circuit 7 divides the corrected data into even and odd columns and outputs them to the Viterbi decoding circuits 9 and 10. Since other configurations are the same as those of the conventional example shown in FIG. 1, corresponding parts are designated by the same reference numerals and the description thereof will be omitted.

FIG. 6 is a block diagram showing the internal structure of the phase shift detector 24 shown in FIG. Phase shift detector 24
Is for sampling the reproduced digital data output from the A / D converter 7 at 1/2 the data rate and outputting the sampling data at the three points at the middle point and both ends of the data rate to the comparison circuits 28a and 28b. Sampling data distributor 27
And a comparison circuit 28 for detecting the waveform of the reproduced digital data.
a, 28b, sampling data distributor 27, comparison circuit 28a,
It has a NAND gate circuit 29 which receives three outputs of 28b and a low pass filter (LPF) 30 which outputs phase shift data.

FIG. 7 is a block diagram showing the internal structure of the sampling data distributor 27 in FIG. The sampling data distributor 27 is a delay device that delays the input data by Tb / 2 according to the recovered clock that is 1/2 the data rate.
31a, 31b and latch circuits 32a, 32b, which latch sampling data at the middle point and both ends of the data rate, respectively.
It consists of 32c and.

Further, FIG. 8 is a block diagram showing the internal structure of the LPF 30 in FIG. The LPF 30 latches the output (b) of the sampling data distributor 27 (latch circuit 32b) (sampling data at the intermediate point of the data rate) of the sampling data distributor 27 according to the reproduction clock and the sampling data (output (output ( b)) 1/128 arithmetic operation 1/128
Arithmetic unit 33b, 1-bit delay unit 34, adder circuits 35a, 35b
It consists of and.

FIG. 9 is a block diagram showing the internal structure of the phase shift compensator 25 shown in FIG. Phase shift compensator 25
Is a comparison circuit that distinguishes the waveform of the reproduction signal to be corrected according to the reproduction digital data output from the A / D converter 7.
36 and an arithmetic processing circuit 37 for converting the phase shift data input from the phase shift detector 24 into data used for correction 37
And a waveform selection circuit (decoder) 38 that controls the correction processing of the reproduced signal waveform based on the comparison result of the comparison circuit 36, and the A / D converter according to the outputs from the waveform selection circuit 38 and the arithmetic processing circuit
The output from the converter 7 is provided with an arithmetic processing circuit 39 for correcting the phase shift.

Next, the operation will be described. Since the operation at the time of recording is the same as the conventional example, the description thereof will be omitted.

The operation during reproduction will be described below. The digital signal recorded on the magnetic tape is reproduced from the rotary head through the amplifier 1. The reproduced signal is an analog ternary signal, and the ternary signal is waveform equalized by the equalizer circuit 4 and input to the post-processing circuit 5 and the PLL circuits 6a and 6b. In the arithmetic processing circuit 5 consisting of an analog delay element and an analog adder, this ternary signal is PR
4 Converted to a detection type signal. In addition, in accordance with the ternary signal, the PLL circuits 6a and 6b generate a reproduction clock and a 1/2 reproduction clock, respectively. PR 4 type signal is A / D converter 7
Is input to and is quantized into 4- to 8-bit digital data based on the 1/2 reproduction clock output from the PLL circuit 6b. This digital data is the phase shift detector 24
To the phase corrector 25
Is output to. In the phase corrector 25, the phase shift correction is performed on the input from the A / D converter 7 based on the phase shift data, and the corrected data is divided into even and odd columns through the selection circuit 8 and then the Viterbi signal is output. It is output to the decoding circuits 9 and 10. The data decoded by the Viterbi decoding circuits 9 and 10 is combined by the selection circuit 16 with the signals of even and odd columns and output to the error detection / correction circuit 17 as decoded data. Error detection / correction circuit 17
In, the decoded data is subjected to error detection, correction processing, etc., and is output to the data expansion circuit 18 after processing such as deshuffling and demodulation. The data decompression circuit 18 decompresses the compressed data to the original data amount, and the D / A converter
It is output to 19. In the D / A converter 19, the data expansion circuit 18
Is converted into an analog signal and an analog video signal is output. Note that the decoding operation in the Viterbi decoding circuits 9 and 10 is the same as in the conventional example, and therefore its description is omitted.

The operation of phase shift detection and phase shift correction, which is a feature of the present invention, will be described below.

First, the phase shift detection will be described. The reproduction signal that has passed through the equalizer circuit 4 has a signal level at the sampling point as shown in FIG. 2 as an example due to the analog 1-bit delay and addition processing in the arithmetic processing circuit 5.
Only at the point where the level changes from +1 "level to" -1 "level or from" -1 "level to" +1 "level, the zero cross point is provided at the midpoint of the data rate (FIGS. 2B and C). , Zero noise does not occur exactly at the midpoint due to phase shift due to white noise, waveform distortion of electromagnetic conversion system, etc. Therefore, the playback clock generated according to the playback signal is necessarily out of phase with the ideal signal state. It becomes a form that includes.

When the decoding is performed by the Viterbi decoding method based on the Ferguson algorithm, the phase shift of the white system can be absorbed if the magnitude thereof is to some extent. However, there is not much absorption effect for a relatively stationary phase shift that is not white like the waveform distortion peculiar to the electromagnetic conversion system, and the steady phase shift causes a decoding error. / N (S / N) improvement effect decreases. In order to solve such a problem, the following phase shift compensation method is used.

FIG. 10 (a) shows the relationship between the phase shift and the signal level shift when the phase shift is included in the reproduced waveform, and FIG. 10 (b) shows the signal level difference due to the difference in the reproduced waveform. Shows. Data detection is performed at a data rate and an integral fraction of the data rate (for example, ½), the signal level at the intermediate point is detected, and how much this value deviates from the zero level is detected. This signal level is used as phase shift data. This is because, as shown in the enlarged view near the zero-crossing point in Fig. 10 (a) or Fig. 2, the change in signal level in the minute interval near the zero-crossing point can be treated as almost linear. This is because the phase shift amount can be determined by a proportional relationship with the shift amount. In addition, since it is possible to similarly establish a proportional relationship between the signal level and the amount of phase shift even in a minute section near the sampling point, the signal level at the ideal sampling point and the actual The deviation from the signal level at the sampling point including the phase deviation component is estimated, and this is updated to the summed data. However, the LPF is used to cancel the phase shift component of the white system, and only the shift amount for a change larger than a certain time constant is treated to determine the phase shift amount.

In the phase shift detector 24 shown in FIG.
The data quantized with the 1/2 reproduction clock from the D converter 7 is sequentially output to the sampling data distributor 27. In the sampling data distributor 27 shown in FIG. 7, the output of the A / D converter 7 is delayed by 1/2 reproduction clock by the delay devices 31a and 31b, and the data at the sampling points shifted by 1/2 reproduction clock are It is output to the latch circuits 32a, 32b, 32c.
The latch circuits 32a, 32b, 32c take in data by the reproduction clock, and as a result, each latch circuit 32a, 32b, 32c
, The data at the sampling point at the beginning of the data rate is output (a), the data at the midpoint of the data rate is output (b), and the data at the sampling point at the end of the data rate is output (c). ) Are output respectively. The output data (a) and the output (b) are compared by the comparison circuit 28a and the output (b) and the output (c) are compared by the comparison circuit 28b.
When the signal changes to the -1 "level, the comparator circuits 28a and 28b detect the NA change.
The control signal is output from the ND gate 29 to the LPF 30. LPF 30
When this control signal is input, the data of output (b) is latched by the latch circuit 33a in the LPF 30 shown in FIG. 8 and the 1/128 arithmetic unit 33 and the adder circuits 35a and 35b are delayed by 1 bit. The signal processing circuit including the device 34 limits the band, passes only the relatively stationary phase shift component such as the waveform distortion of the electromagnetic conversion system, and outputs the phase shift data to the phase shift corrector 25.

Next, the operation of correcting the phase shift will be described. In the phase shift compensator 25 shown in FIG. 8, the arithmetic processing circuit 37 calculates the absolute value of the level difference between the input phase shift data and the zero level and sends the absolute value data to the arithmetic processing circuit 39 together with the code data. Output. Outputs (a), (b), (c) from the sampling data distributor 27 to the comparison circuit 36.
Is input, the input signal waveform of the comparison circuit 36 is (a) in FIG.
It is determined which one of (1) to (h) is applicable, and the determination result is output to the waveform selection circuit 38. The waveform selection circuit 38 "+ corrects" the phase shift based on the input judgment result.
Or "-correction" is determined, and the determination data is output to the arithmetic processing circuit 39. The arithmetic processing circuit 39 outputs the output (c) from the sampling data distributor 27 based on the input code data, the absolute value data of the level difference, and the correction determination data.
After the correction is performed, the corrected data is selected by the selection circuit 8
Output to.

The corrected data input to the selection circuit 8 is divided into even and odd columns and input to the Viterbi decoding circuits 9 and 10, respectively. Since the decoding operation in the Viterbi decoding circuits 9 and 10 and the operation of each circuit thereafter are the same as those in the conventional example, the description thereof will be omitted.

Embodiment 2 In the above embodiment, the case of sampling at a cycle of 1/2 times the data rate has been described, but the same applies to the case of sampling at a cycle of 1/3 times or more of an integral number. Can be done.

Third Embodiment In the above embodiment, the phase shift data is detected based on the signal level fluctuation at the midpoint of the data rate. However, a waveform for performing a specific level change, for example, the same data rate is used. It is also possible to detect the phase shift data based on the shift of the signal level of the "+" level of the waveform having the zero cross point inside.

Fourth Embodiment Further, although the case where the Viterbi decoding method using the Ferguson algorithm is used has been described in the above embodiment,
The present invention is also applicable to the case where a Viterbi decoding method of another algorithm or a decoding method other than the Viterbi decoding method is used.

[0039]

As described above, according to the present invention, the phase shift of the zero cross point when the signal changes in a specific pattern is calculated from the reproduced actual signal level, and the original phase shift is calculated based on the calculated value. Since the reception level at the ideal sampling point is predicted, the sampled reproduction data can be detected more accurately, and the decoding accuracy can be improved.

Further, an LPF is provided on the output side in the phase shift detector to cut a random phase shift having a short fluctuation period to detect a steady phase shift, so that the phase in the Viterbi decoding method is detected. It is possible to eliminate the drawbacks of the shift correction and correct the steady phase shift such as the waveform distortion peculiar to the electromagnetic conversion system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional magnetic recording / reproducing apparatus.

FIG. 2 is a diagram showing a level of a reproduced signal and a zero-cross point included in the reproduced signal.

FIG. 3 is a diagram showing a state transition, a survival path, and a decoding result for a state parameter in a Viterbi decoding method using the Ferguson algorithm.

FIG. 4 is a graph showing a simulation result of a relationship between a phase shift from a sampling point and a bit error rate in a magnetic recording / reproducing apparatus.

FIG. 5 is a block diagram showing the configuration of a magnetic recording / reproducing device incorporating the data detection device according to the present invention.

6 is a block diagram showing a configuration of a phase shift detector in FIG.

7 is a block diagram showing a configuration of a sampling data distributor in FIG.

8 is a block diagram showing a configuration of an LPF in FIG.

9 is a block diagram showing a configuration of a phase shift corrector in FIG.

FIG. 10 is a diagram showing a relationship between a signal level shift and a phase shift when the reproduced waveform has a phase shift, and a signal level difference depending on the waveform of the reproduced waveform.

FIG. 11 is a diagram showing various waveform shapes of reproduced waveforms.

[Explanation of symbols]

 5 Arithmetic processing circuit 6a, PLL circuit (Tb) 6b PLL circuit (1/2 Tb) 7 A / D converter 9, Viterbi decoding circuit (even number column) 10 Viterbi decoding circuit (odd number column) 24 Phase shift detector 25 phase Deviation corrector 30 LPF 37 Arithmetic processing circuit 39 Arithmetic processing circuit

Claims (3)

[Claims] 1. A data detection device used in a magnetic recording / reproducing device for recording / reproducing a digital signal, and a reproduction clock generating means for generating a reproduction clock of a multiple of a reproduction data rate and an integral multiple of the reproduction data rate. A means for sampling the reproduced data in accordance with the A / D conversion and a digital data after the A / D conversion are operated to calculate the phase shift of the reproduced data from the ideal sampling point of the A / D conversion. A detection means for detecting only the zero-cross point when the subsequent digital data changes from the "+1" level to the "-1" level is provided, and the data detection is performed by predicting the digital data at the ideal sampling point. A data detection device having the above-mentioned configuration. 2. When the A / D-converted digital data changes from the "+1" level to the "-1" level by the reproduction clock generated by the reproduction clock generation means, reproduction is performed at a reproduction data rate of 1 time. Means for detecting a signal level at an intermediate point between sampling points of "+1" and "-1" level digital data sampled by a clock by using a reproduction clock having an integral multiple of a reproduction data rate, and the detected signal level Means for calculating the phase shift component of the received signal based on the calculated phase shift component, and means for predicting and correcting the fluctuation of the signal level due to the phase shift at the sampling point of the digital data based on the calculated phase shift component. The data detection device according to claim 1, wherein 3. The data detecting apparatus according to claim 1, wherein the detecting means is configured to cut a phase shift having a short fluctuation period and detect a steady phase shift.