JPH05257856A - Channel device - Google Patents

Abstract

PURPOSE:To decrease conflicts on a data bus and improve the efficiency by gaining no access to a main storage device with performance higher than required. CONSTITUTION:This channel device 20 controls data transfer between the main storage device 109 and an input/output device 30 and data to be transferred from the main storage device 10 to the input/output device are prefetched by a data prefetch circuit 23 and stored in a data buffer 21 temporarily. The amount of data in the data buffer 21 is monitored to decide whether the amount of data is larger than a previously set value, and consequently variation in the prefetch period is indicated to the prefetch circuit 23. Main storage access from a channel is made fast by a certain starting amount at the start of the transfer by the channel device 20 and then data are fetched thereafter corresponding to the amount of data sent out to the input/output device 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel device, and more particularly to a channel device for controlling data transfer between a main memory device and an input / output device.

[0002]

2. Description of the Related Art Conventionally, in a channel device for controlling data transfer between a main memory device and an input / output device, data read from the main memory device is stored in order to smoothly perform data transfer with the input / output device. It is general that the data is once stored in a large-capacity data buffer and then retrieved and used according to a request from the input / output device.

In such a channel device, during data transfer, regardless of the state of the input / output device, data is fetched from the main memory as long as there is a free space in the data buffer.

Further, in order to enable data transfer with a large number of input / output devices, it is a common practice to connect a large number of channel devices to the main storage device and control them independently.

[0005]

Therefore, when a large number of channel devices are simultaneously activated, all of the activated channel devices request data fetch to the main storage device until the data buffer becomes full. Are continuously generated, and the requests are temporarily concentrated in the main storage device.

As a result, competition occurs in the data fetch operation between the channels, which influence each other. Similarly, it was working until then,
It may have affected the data fetch operation of other channels.

Further, this operation is carried out regardless of the type of channel device (high speed / low speed), and a large amount of data is prefetched even in a low speed channel which does not require prefetch data, which disturbs the operation of the high speed channel. I decided to do it.

[0008]

A channel device of the present invention comprises a data prefetch circuit for prefetching data to be transferred from a main memory device to an input / output device, a data buffer for temporarily storing the fetched data, and a data buffer Means for sending the data to the input / output device, and a comparison circuit for monitoring the data amount in the data buffer and determining whether or not the data amount is larger than a preset value.

Another channel device of the present invention is a channel device for controlling data transfer between a main memory device and an input / output device, and a data prefetch circuit for prefetching data to be transferred from the main memory device to the input / output device. , A data buffer for temporarily storing the fetched data, and means for sending the data in the data buffer to the input / output device,
Comparison for holding the type of channel device, means for generating a specified value according to the type of channel device, and monitoring the amount of data in the data buffer and determining whether the amount of data is greater than the specified value And a circuit.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. Figure 1
In the first embodiment of the present invention, the main storage device 10 is provided between the main storage device 10 and the input / output device 30, and the main storage device 10 and the input / output device 30 control data transfer. A data prefetch circuit 23 that fetches data to be transferred from the storage device 10 to the input / output device 30 in advance.
And a data buffer 21 for temporarily storing the fetched data and the input / output device 3 for storing the data in the data buffer 21.
It includes a transfer circuit 25 for sending data to 0 and a comparison circuit 22 for monitoring the amount of data in the data buffer 21 and determining whether the amount of data is larger than a preset value.

The channel device 20 has means for instructing the data prefetch circuit 23 to change the prefetch cycle in response to an instruction from the comparison circuit 22.

The channel device 20 generally controls the data transfer from the main memory device 10 to the input / output device 30 and the bidirectional transfer from the input / output device 30 to the main memory device 10. Data transfer from the device 10 to the input / output device 30 will be described.

The channel device 20 includes a data bus 101,
It is connected to the main storage device 10 via 102. here,
The data buses 101 and 102 are managed by general priority logic.

Data prefetch circuit 23 of channel device 20
Is a circuit that requests the main storage device 10 to read the transfer data to the input / output device 30 via the data bus 101. The data buffer 21 receives the data read from the main storage device 10 via the data bus 102. And a buffer that stores this. The transfer circuit 25 is a circuit that reads out the data stored in the data buffer 21 and sends it to the input / output device 30. The comparison circuit 22 that holds a predetermined value (a value smaller than the capacity of the data buffer 21) in the specified value register 24 is the data buffer 2
This is a circuit for comparing the data amount stored in 1 with the value of the specified value register 24.

The operation of these circuits is shown in FIG.

In FIG. 2, when the channel device 20 has an empty area in the state of the data buffer 21 in response to a data transfer start request, the comparison circuit 22 causes the data buffer 21 to operate.
Compare the amount of data stored in and the value of the specified value register,
The result is displayed on the data prefetch circuit 23 through the signal line 221.

In the data prefetch circuit 23, the comparison circuit 22
When the comparison result shows that the data amount of the data buffer 21 is smaller, the main memory device 10 is requested to read the transfer data via the data bus 101, and the comparison result of the comparison circuit 22 indicates the data amount of the data buffer 21. If is larger, after waiting for a certain period of time, the main memory device 10 is requested to read the transfer data.

In response to a read request from the data bus 101, the main memory 10 reads the transfer data and sends this data to the data buffer 21 via the data bus. The data buffer 21 receives the transfer data via the data bus 102 and stores it. Transfer circuit 25
Reads the data stored in the data buffer 21,
This is output to the input / output device 30.

In this way, the channel device 20 fetches at a high speed at the beginning of transfer, such as main memory access from the channel, and thereafter fetches data in accordance with the amount of data sent to the input / output device 30.

FIG. 3 shows a second embodiment of the present invention. Figure 3
In, the channel device 2 which is the second embodiment of the present invention
Reference numeral 0a denotes a data prefetch circuit 23 for prefetching data to be transferred from the main memory device 10 to the input / output device 30.
A data buffer 21 for temporarily storing the fetched data, a transfer circuit 25 for sending the data in the data buffer to the input / output device 30, a channel type register 26 for holding the type of the channel device 20a, and a channel device 2
A specified value generation circuit 2 that generates a specified value according to the type of 0a
7 and a comparison circuit 22 that monitors the amount of data in the data buffer and determines whether the amount of data is greater than the specified value.
And have.

The channel device 20a includes a comparison circuit 22.
The data prefetch circuit 23 is instructed to change the prefetch cycle.

The channel device 20a includes the data bus 10
1, 102 are connected to the main storage device 10. Here, the data buses 101 and 102 are generally managed by priority logic.

Data prefetch circuit 23 of channel device 20
Is a circuit that requests the main storage device 10 to read the transfer data to the input / output device 30 via the data bus 101. The data buffer 21 receives the data read from the main storage device 10 via the data bus 102. And a buffer that stores this. The transfer circuit 25 is a circuit that reads out the data stored in the data buffer 21 and sends it to the input / output device. The channel type register 26 is a register that holds the channel type of the channel device, and the specified value generation circuit 27 is a circuit that generates a specified value from the contents of the channel type register. The comparison circuit 22 is a circuit that compares the amount of data stored in the data buffer 21 with the generated value of the specified value generation circuit 27.

In this embodiment, the same operation as that shown in FIG. 2 is performed, so that the description thereof is omitted. However, the specified value generated by the specified value generation circuit 27 is high in the channel type held in the channel type register 26. If it indicates a channel, a larger value is set as compared to the case of indicating a low speed channel.

The comparison circuit 22 compares the amount of data in the buffer with the set specified value, and instructs the data prefetch circuit 23 to change the prefetch cycle based on the result.

[0027]

As described above, according to the present invention, at the time of starting the transfer of the channel device, a fixed amount such as the main memory access from the channel is fast, and thereafter, according to the amount of data sent to the input / output device. By fetching the data in the memory, it is possible to prevent the main memory device from being accessed with an unnecessarily high performance, reduce contention on the data bus, and obtain an efficient device.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation of each circuit.

FIG. 3 is a diagram showing a second embodiment of the present invention.

[Explanation of symbols]

10 main storage device 20 channel device 30 input / output device 101, 102, 201, 211, 212, 221, 2
61, 271 Signal line 201 Input / output interface 21 Data buffer 22 Comparison circuit 23 Data prefetch circuit 24 Specified value register 25 Transfer circuit 26 Channel type register 27 Specified value generation circuit

Claims (2)

[Claims] 1. A channel device for controlling data transfer between a main memory device and an input / output device, a data prefetch circuit for prefetching data to be transferred from the main memory device to the input / output device, and temporarily storing the fetched data. Includes a data buffer, means for sending the data in the data buffer to the input / output device, and a comparator circuit for monitoring the amount of data in the data buffer and determining whether the amount of data is greater than a preset value. The data prefetching circuit is instructed to change the prefetching cycle by an instruction from the comparison circuit. 2. A channel device for controlling data transfer between a main memory device and an input / output device, a data prefetch circuit for previously fetching data to be transferred from the main memory device to the input / output device, and temporarily storing the fetched data. A data buffer, a means for sending the data in the data buffer to the input / output device, a means for holding the type of the channel device, a means for generating a specified value according to the type of the channel device, and an amount of data in the data buffer And a comparison circuit for determining whether or not the data amount is larger than the specified value, and instructing the data prefetch circuit to change the prefetch cycle by an instruction of the comparison circuit. apparatus.