JPH03142549A - Data processor - Google Patents

Abstract

PURPOSE:To decrease overrun by reducing data transfer width currently under execution and receiving another data transfer request when the number of effective data in a data buffer gets smaller than a rated value. CONSTITUTION:A data buffer register 16 holds the number of the effective data in data buffers 151 and 15n and a set data buffer amount register 17 stores the rated value for the amount of the data in the data buffers 151 and 15n determined in advance. In a comparator 18, the data buffer register 16 is compared with the set data buffer amount register 17 and according to a compared result, the transfer width change of interruption sent out from an interruption transmission part 19 is selected by a selector 20. In a data buffer control part 22, according to a transfer width change instruction sent from another channel through a signal line 25, the current addresses of the data buffers 151 and 15n are memorized and it is instructed to use the data buffers 151 and 15n corresponding to the transfer width change.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a data processing device, and more particularly, to a data processing device, which has a plurality of channels, a channel control section, and a transfer control section, and has a storage device and a plurality of channels connected to each of the channels. The present invention relates to a data processing device that controls data transfer between input and output devices.

[Conventional technology]

Conventionally, in this type of data processing device, when data transfer requests are received from a plurality of channels to a channel control unit, the requests are accepted in order of priority.

This will be explained using a block diagram of a conventional channel shown in FIG. 5 and a block diagram of a conventional channel control section shown in FIG.

As a result of comparing the contents of the data buffer 42゜data buffer 42n and the set data buffer amount register 43 with the contents of the data buffer 42゜data buffer 42n and the set data buffer amount register 43 in the case where the transfer is being performed on the channel with a high priority, the data buffer 42
．． When the data buffer 42n becomes smaller, the signal line 4
7, the interrupt request is sent to the channel controller of FIG. In that case, an interrupt request is sent to the selection condition determining unit 50 via the signal line 52n, but since the currently underway transfer has a high priority, interrupts for that channel are not accepted.

[Problem to be solved by the invention]

In the conventional data processing device described above, when data transfer requests are made to the channel control unit from multiple channels,
Since requests are accepted in order of priority, requests with lower priority have to wait for a long time before being accepted.In order to reduce the incidence of data overruns, more data buffers than necessary are provided for each channel. This has the disadvantage of increasing the amount of hardware required.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to enable requests with low priority to be accepted in a short time, to eliminate the need to prepare more data buffers than necessary for each channel, and to process data without increasing the amount of hardware. The goal is to provide equipment.

[Means to solve the problem]

The device of the present invention includes a plurality of channels, a channel control section, and a transfer control section, and is a data processing device that controls data transfer between a storage device and a plurality of input/output devices connected to each of the channels. a display means for displaying valid data in the data buffer of the channel; a holding means for holding a rewritable constant value; and a valid data value indicated by the display means; a comparison means for comparing the constant value held by the holding means; and an output of the comparison means to reduce the data transfer width between the channel currently transferring data and the transfer control unit so that the effective data amount of the data buffer is kept at the constant value. The present invention is characterized by comprising a management means for performing data transfer using fewer channels.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a storage device 1 stores data to be sent to peripheral devices 7□ to 7n, and an input/output processing device 2 includes a transfer control unit 3 that controls the transfer of the data, and a plurality of channels 5□ to 7n. 5. , a channel control unit 4 that accepts interrupts from
It is composed of. The plurality of channels 5□-5n have data buffers 61-6n, and serve as data communication paths between the storage device 1 and the peripheral devices 7,-7n. Peripheral devices 71-7n
stores the data sent from the storage device 1.

FIG. 2 is a block diagram of each channel 51-5fl.

The data buffer register 16 includes the data buffer 15
1. Data buffer 15. , the number of valid data within is held, and the set data buffer amount register 17 stores predetermined data buffer 151,
5. , the specified value of the amount of data within is stored. The comparator 18 compares the data buffer register 16 and the set data buffer amount register 17, and based on the comparison result, the selector 20 changes the transfer width of the interrupt sent from one interrupt sending unit.
Select with .

In addition, the data buffer management unit 22 changes the current data buffer 151 data buffer 15 . Remember the address of the data buffer 151. according to the transfer width change. Instructs to use the data buffer 15n.

FIG. 3 is a block diagram of the channel control section 4.

The channel interrupt receiving unit 26 receives interrupts from channels 51 to 5n through signal lines 291 to 29. Accepted via. It takes 4 cycles to accept an interrupt with a transfer width of 4 bytes, but
If an interrupt with a transfer width of 2 bytes is to be accepted, only two cycles are required, and the remaining two cycles can be used to accept interrupts from other channels. Further, the selection condition determining unit 28 instructs the selector 27 to give top priority to the channel for which the data transfer width change instruction has been issued.

FIG. 4 is a block diagram of the transfer control section 3.

In response to the transfer width change instruction, the data buffer management unit 33
Memorize the address of the current data buffer 34.35, selector 37.38 selects the data buffer 34 depending on the transfer direction.
．． Select the data to be sent to 35.

Next, the operation of this embodiment will be explained.

Channel 51 and channel 5n among channels 51 to 5o
makes a transfer request from storage device 1 to peripheral device 701 and peripheral device 7n, the data transfer width of channel 51 is 2 bytes, and the data transfer width of channel 5° is 1 byte. is interrupted with priority, and channel 5° is made to wait until it is accepted.

During the waiting period, the channel 5°, as shown in FIG. The contents of the quantity register 17 are compared by a comparator 18. As a result, when the number of valid data in the data buffer 15 becomes less than the specified value, the selector 20 selects the interrupt request sent from the interrupt sending unit 9, and the signal line 24. Signal line 13. A request for changing the data transfer width during execution is sent to the channel control unit 4 via.

As shown in FIG. 3, the channel control unit 4 receives an ongoing data transfer width request from the selection condition determination unit 28 via the signal line 31, and instructs the transfer control unit 3 to transfer the channel 5n with the highest priority. . As shown in FIG. 4, when the data buffer management section 33 receives an instruction to change the data transfer width of the channel 5n via the signal line 40, the transfer control section 3 changes the signal line 41.
Selector 3 is activated by the transfer direction instruction sent via
7. Monitors the usage status of the data buffer 34 and 35 for the data currently being transferred in the transfer direction selected by 38, and stores the data that has been transferred so far in the data buffer 34 and the channel 5n in the data buffer 35. Instructs an address to send data from.

As described above, in this embodiment, the data buffers 61 to 6n
If the number of valid data becomes smaller than the specified value, the width of the data transfer currently being executed is made smaller so that another data transfer request can be accepted, thereby making it possible to reduce overruns.

〔Effect of the invention〕

As explained above, the present invention enables low-priority requests to be accepted in a short time, eliminates the need to prepare an unnecessarily large number of data buffers for each channel, and eliminates the need to provide data buffers that do not increase the amount of hardware. This has the effect of reducing overruns in data transfer in a processing device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of channels 51 to 5n in FIG. 1, FIG. 3 is a block diagram of channel control unit 4 in FIG. 1, and FIG. 1 is a block diagram of the transfer control section 3 in FIG. 1, FIG. 5 is a block diagram of a conventional channel, and FIG. 6 is a block diagram of a conventional channel control section. 1... Storage device, 2... Input/output processing device, 3...
Transfer control unit, 4...Channel control unit, 51-5o...
・Channel, 61~6n...Data buffer, 71~
7n...Peripheral device, 8-12...Data bus, 15
1 to 15n...Data buffer, 16...Data buffer register, 17...Setting data buffer amount register, 18...Comparator, 19...Interrupt sending unit, 20
...Selector, 22...Data buffer management section, 2
6...Channel interrupt reception unit, 27...Selector, 2
8... Selection condition determination unit, 33... Data buffer management unit, 34... Data buffer, 35... Data buffer, 37... Selector, 38... Selector, 4
2...Data buffer, 42...Data buffer,
43... Setting data buffer amount register, 44...
Comparator, 48...Channel interrupt reception unit, 4...Selector, 50...Selection condition determination unit °
Attorney Atsushi Uchi Atsushi Oto No. 7 Figure 7's @ number thread,~757I Kau Terameikan 0 Shinuga 7qΔ 2q7-29n) 377-317L J J2/
55: f'ii 15J - Figure 353 Figure 1 Issue/Monthly magazine f5 Kau No. ga Strawberry transfer Cloth 1 City ``I V force 1 et al. 1 “1st Part A Diagram

Claims (1)

[Scope of Claims] A data processing device comprising a plurality of channels, a channel control unit, and a transfer control unit, and controlling data transfer between a storage device and a plurality of input/output devices connected to each of the channels, a display means for displaying valid data in the data buffer of the channel; a holding means for holding a rewritable constant value; and a valid data value indicated by the display means; a comparison means for comparing the constant value held by the holding means; and an output of the comparison means to reduce the data transfer width between the channel currently transferring data and the transfer control unit so that the effective data amount of the data buffer is kept at the constant value. 1. A data processing apparatus comprising: a management means for performing data transfer using fewer channels.