JP3211738B2 - Data transfer device and data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a data transfer apparatus and method.
In particular, in a channel control device in which a plurality of channel devices are connected via a bus, the memory reply data to the channel device and the transmission of operation instruction data from the microprogram control unit to the channel device are described above. The present invention relates to a data transfer device and method for performing data sharing using a bus.

[0002]

2. Description of the Related Art As a conventional channel device of this kind, reference is made to, for example, the description of Japanese Patent Application Laid-Open No. Hei 3-36652.
The above publication discloses a channel device connected between a main storage device and an external storage device, capable of performing synchronous transfer, and transmitting a transfer request before transmitting a transfer response signal. Buffer means for temporarily storing transfer data in a channel device supporting an interface capable of predetermining the number of possible transfer request signals, and a stack for storing the number of transfer request signals received and the number of transfer response signals transmitted Means, and monitoring means for monitoring the number of transfer data stored in the buffer means and the number of storages in the stack means, wherein the monitoring means monitors the storage state of the buffer means and the number of storages in the stack means. By controlling data transfer between the main storage device and an external device, the data transfer between the channel device and the main storage device can be performed. Channel device to prevent the occurrence of data overrun due to delay of the transmission and reception of the transfer data has been proposed.

[0003] For example, Japanese Patent Application Laid-Open No. 3-58158 discloses a data processing device for processing data transfer between a main storage device and a peripheral device while giving priority to a request from a channel device. By detecting whether the amount of valid data stored in the data buffer in the device has become equal to or more than a certain amount, the data transfer with the peripheral device via the channel device can be temporarily suspended or resumed. A data transfer device for preventing overrun of preceding data has been proposed.

[0004]

However, the above prior art has the following problems.

That is, a plurality of channel devices are connected to a channel control device via a bus, and memory reply data is sent from the main storage device to the channel device, and a microprogram control unit in the channel control device is sent to the channel device. When the operation instruction is transmitted via the bus, if the memory reply data to the channel device is continuous, the bus is occupied by the data transfer, and the microprogram control unit transmits the operation instruction. If this is the case, the bus cannot be used, so that the bus is kept waiting.

In the above-mentioned conventional technology, the factor for controlling the data transfer does not include this queuing, and interrupts the execution of the microprogram or causes a data overrun or a command overrun.
Has problems.

The reason is that while memory reply data from the main storage device is continuous, an operation instruction cannot be supplied to the channel device, and if another operation instruction is newly generated, the operation instruction cannot be issued. As a result, execution of the microprogram is interrupted, and data overrun and command overrun are caused.

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an update method when an operation instruction to a channel device and data transfer conflict and the operation instruction is waiting. It is an object of the present invention to provide a data transfer apparatus and method which have a small number of waits and a low overrun probability in consideration of the frequency of use of a bus.

[0009]

In order to achieve the above object, the structure of the data transfer device of the present invention is as follows.
Every time a memory request is generated, +1 (one is counted up), and every time a memory request is accepted by the channel control device, -1 (one is counted down)
And a means for sending the value of the counter to the channel control device. The channel control device has an operation instruction to the channel device issued by the microprogram control unit which is down-converted to memory reply data. Waiting display means for displaying that the device is waiting due to contention on the data bus, an adder for summing the values of the counters of the channel devices, and a value of the adder smaller than a predetermined constant. A comparator that outputs a logical "1" when detecting that
A memory request reception inhibiting means for temporarily stopping reception of a memory request from each channel device when the operation instruction is waiting and the output of the comparator is logic "1".

[0010]

Embodiments of the present invention will be described below. Data transfer apparatus of the present invention, in the form of its preferred embodiment, a plurality of channel devices connected via a bus to the main memory (20 ₁ to 20 _n in Fig. 1) (Fig. 1
1) that controls the data transfer with the channel control device (2 in FIG. 1), and stores memory reply data from the main storage device to a plurality of channel devices and operation instruction data from the channel control device to the channel devices. In a data transfer device that transfers data via a bus, each channel device counts up by one each time a memory request is generated, and counts down by one each time a memory request is received by the channel control device (FIG. 1). 23) and means for sending the value of the counter to the channel control device. The channel control device (2 in FIG. 1) transmits the counter value to the channel device issued by the microprogram control unit (3 in FIG. 1). Operation instruction waits due to contention on the down data bus with memory reply data Display means (9 in FIG. 1) for displaying that the synchronization is in progress, an adder (12 in FIG. 1) for summing up the values of the counters of the respective channel devices, and a value of the adder smaller than a constant in advance. A comparator (11 in FIG. 1) that outputs a detection signal as active when detecting that the operation request is awaiting, and when the output of the comparator is active, a memory request from each of the channel devices is output. And a memory request reception inhibiting means (10 in FIG. 1) for temporarily stopping the reception of the request.

In the embodiment of the present invention, when the sum total of the values of the counters of the respective channel devices is smaller than a predetermined constant, when the waiting display means displays the waiting of the operation instruction, the memory request acceptance suppressing means But,
Suppress reception of memory requests from each channel device. When the reception of the memory request is suppressed, the data transfer between the main storage device and each channel device is temporarily suspended,
The memory reply data from the main storage device is also temporarily suspended. When the memory reply is interrupted, the waiting operation instruction is transmitted to the channel device.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing the configuration of one embodiment of the present invention.

Referring to FIG. 1, in one embodiment of the present invention, the channel control unit 2 is connected to the main memory 1, the updater bus 31 to each channel device 20 ₁ to 20 _n, down data bus 32.

[0014] Each channel unit 20 ₁ to 20 _n includes a data transfer control circuit 22, a counter 23, a data output buffer 21, a data receiving buffer 24.

The data transfer control circuit 22 includes a channel control unit 2, a data output buffer 21 is connected to the counter 23, to, when the memory request is generated, via the updater bus use request signal 33 ₁ ~ 33 _n, An update bus use request is sent to the channel control device 2.

[0016] Using the updater bus 31 is granted, the channel control unit 2 via the up data bus grant signal 34 ₁ to 34C _n, is notified to the data transfer control circuit 22.

When the use of the updata bus 31 is permitted, the data transfer control circuit 22 sends the data transmission buffer 2
1 instructs transmission of the memory request data to the updater bus 31.

The data transfer buffer 21 is connected to the data transfer control circuit 22 and the up data bus 31, and sends out memory request data to the up data bus 31 according to an instruction from the data transfer control circuit 22.

The data transfer control circuit 22 notifies the counter 23 of the occurrence of the memory request and the acceptance of the memory request.

The counter 23 includes a data transfer control circuit 22
Is connected to the channel control device 2, and the count value is incremented by one (one count up) every time a memory request is generated, and the count value is decremented by one (one count down) each time a memory request is received.
Values to the channel control device 2, is sent through the counter output signal 35 ₁ to 35 _n.

The data reception buffer 24 is connected to the channel control device 2 via the down data bus 32 and receives memory reply data.

Next, the configuration of the channel control device 2 in one embodiment of the present invention will be described.

The data reception buffer 7 is connected to the up data bus 31 and the main storage device 1 and sends out the memory request data received via the up data bus 31 to the main storage device 1.

The register 5 includes the main storage device 1 and the selector 6
And receives the memory reply data from the main storage device 1 and sends it to the selector 6.

The register 4 is connected to the microprogram controller 3, the selector 5, and the waiting display circuit 9. Register 4 receives an operation instruction sent to each channel device 20 ₁ to 20 _n from the microprogram control unit 3, if there is no memory reply data register 5,
An operation instruction is sent to the selector 6, and if there is memory reply data in the register 5, the operation instruction is held and waiting is performed until there is no more memory reply data in the register 5.

The selector 6 comprises a register 4, a register 5,
If the register 5 has memory reply data, the register 5 is selected, and if there is no memory reply data, the register 4 is selected, and the selected data is transmitted to the down data bus 32.

The waiting display circuit 9 monitors the states of the registers 4 and 5, and if a wait occurs in the register 4, the memory request stop instruction issuing circuit 10
To indicate that a meeting has occurred.

The adder 12 calculates the sum of the counters 23 in each channel device and outputs the result to the comparator 11.

The comparator 11 compares the output value of the adder 12 with a preset specified value (constant) "N", and when the value of the adder 12 is smaller than the constant "N". Output a logic "1" to the memory request stop instruction issuing circuit 10.

Memory request stop instruction issuing circuit 10
When the waiting display circuit 9 displays the waiting of the operation instruction, and the output of the comparator 11 is logic "1", it outputs the memory request acceptance stop instruction to the priority determination circuit 8.

When the priority determining circuit 8 receives the instruction to stop accepting a memory request from the memory request stop instruction issuing circuit 10, the priority order determining circuit 8 temporarily grants the updata bus use permission in response to the updata bus use request from each channel device. Do not put out.

Next, the operation of one embodiment of the present invention will be described.

The channel device 20 ₁ to 20 _n of the counter 23
Is incremented by 1 each time a memory request occurs, and is decremented by 1 when a memory request (memory request) is accepted by the channel device, and its output is sent to the adder 12 of the channel control device 2.

The memory reply data (memory response data) for the memory request data from each channel device is sent from the main storage device 1 via the register 5, selector 6, and down data bus 32 of the channel control device 2 to the channel device. Sent to

An operation instruction to each channel device is sent from the microprogram controller 3 of the channel control device 2 to the channel device via the register 4, the selector 6, and the down data bus 32.

When the microprogram control unit 3 issues an operation instruction to each channel device, if there is valid memory reply data in the register 5, the memory reply data is prioritized. Wait in register 4.

When the queuing display circuit 9 detects that the queuing has occurred, the queuing display circuit 9 notifies the memory request stop instruction issuing circuit 10 to that effect.

The adder 12 calculates the sum of the values of the counters 23 of the respective channel devices, compares the result with a predetermined constant "N" in the comparator 11, and outputs the output value of the adder 12 as a constant " If it is smaller than "N", the output value of the comparator 11 becomes logic "1" and is notified to the memory request stop instruction issuing circuit 10. The memory request stop instruction issuing circuit 10 waits for an operation instruction,
When the output of the comparator 11 is logic "1", it instructs the priority determination circuit 8 to temporarily stop accepting a memory request. As a result, the data transfer between the channel device and the main storage device 1 is temporarily interrupted, so that a gap is created in the memory reply data from the main storage device, and the register 4
The operation instruction to the channel device which has been waiting in the above can be transferred.

[0039]

As described above, according to the present invention,
In consideration of the frequency of use of the update data bus, there is an effect that a data transfer device with a short waiting time for issuing an operation instruction and a low overrun probability can be realized.

The reason is that, in the present invention, when the operation instruction to the channel device and the data transfer compete with each other and the operation instruction is waiting, if the frequency of use of the update data bus is less than a certain value, the operation is temporarily stopped. This is because the reception of a memory request is suppressed, a gap is created in data transfer, and an operation instruction can be issued.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Main storage device 2 Channel control device 3 Microprogram control unit 4 Register 5 Register 6 Selector 7 Data reception buffer 8 Priority determination circuit 9 Waiting display circuit 10 Memory request stop instruction issuing circuit 11 Comparator 12 Adder 20 _{1 to} 20 _n channel device 21 data transfer buffer 22 data transfer control circuit 23 counter 24 data reception buffer 31 up data bus 32 down data bus 33 _{1 to} 33 _{n up} data bus use request signal 34 _{1 to} 34 _{n up} data bus use permission signal 35 _{1 to} 35 _n Counter output signal

Claims (4)

(57) [Claims] A data transfer between a plurality of channel devices connected via a bus and a main storage device is controlled via a channel control device. Each of the channel devices is incremented by one when a memory request is issued. A counter that counts down by one upon request reception, wherein the sum of the count values of the counters of the respective channel devices is equal to or less than a predetermined value, and an operation instruction from the channel control device to the channel device is When waiting due to contention with the memory reply data to the channel device read from the main storage device, the channel control device temporarily suspends the reception of the memory request from each of the channel devices, and It creates a gap in the data, especially that it has to issue an operation instruction Data transfer how to. 2. A channel control device for controlling data transfer between a plurality of channel devices connected via a bus and a main storage device, comprising: memory reply data from the main storage device to the plurality of channel devices; In a data transfer device for transferring operation instruction data from the channel control device to the channel device via the bus, each channel device is counted up by one each time a memory request occurs, and the memory request is A counter that counts down by one each time it is accepted by the channel control device; and a unit that sends out the value of the counter to the channel control device, wherein the channel control device issues the channel device issued by a microprogram control unit. Operation instruction to memory Waiting display means for displaying that a wait is in progress due to contention on the down data bus with the data, an adder for summing the values of the counters of the respective channel devices, and the value of the adder is predetermined. A comparator that outputs a detection signal as active when it detects that it is smaller than the constant, and the operation instruction is waiting, and when the output of the comparator is active, a memory request from each of the channel devices is A data transfer device comprising: a memory request reception inhibiting unit for temporarily stopping reception. 3. The memory request data from each of the channels to the channel control device is transmitted via an up data bus, and the memory reply data and operation instruction from the channel control device to each of the channels are transmitted via a down data bus. 3. The data transfer device according to claim 2, wherein the data transfer is performed. A first storage unit for storing the memory reply data read from the main storage device, a second storage unit for storing an operation instruction for the channel device; And a selector for selecting one of the outputs of the second storage unit and outputting the selected data to the down data bus. If there is valid memory reply data in the first storage unit, the memory reply data is prioritized and the operation is performed. 4. The data transfer device according to claim 3, wherein the instruction is performed in the second storage unit.