JPH05251867A - Manufacture of multi-layered circuit board - Google Patents

Manufacture of multi-layered circuit board

Info

Publication number
JPH05251867A
JPH05251867A JP8487092A JP8487092A JPH05251867A JP H05251867 A JPH05251867 A JP H05251867A JP 8487092 A JP8487092 A JP 8487092A JP 8487092 A JP8487092 A JP 8487092A JP H05251867 A JPH05251867 A JP H05251867A
Authority
JP
Japan
Prior art keywords
hole
circuit
holes
plating
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8487092A
Other languages
Japanese (ja)
Inventor
Kenshirou Fukusato
健志郎 福里
Satoshi Isoda
聡 磯田
Tokisada Takeda
時定 竹田
Hiroyoshi Yokoyama
博義 横山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lincstech Circuit Co Ltd
Original Assignee
Hitachi AIC Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi AIC Inc filed Critical Hitachi AIC Inc
Priority to JP8487092A priority Critical patent/JPH05251867A/en
Publication of JPH05251867A publication Critical patent/JPH05251867A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To shorten the manufacturing time as a whole, improve productivity, and lower the manufacturing cost by laminating a insulated resin sheet to which the metal foil is fixed with a hole provided in advance in order to reduce the time for boring process. CONSTITUTION:On the surface of an inner layer circuit board 3, there is laminated an insulated resin sheet 6 to which a metal foil is fixed with a hole 9 provided in advance. Then, a plating layer 13 is formed in the hole 9 by a plating process. Further, an outer layer circuit 15 is formed to manufacture a multi- layered circuit board.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は多層配線板の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board.

【0002】[0002]

【従来の技術】多層配線板は、例えば、次の通りに製造
している。すなわち、中心の基板に内層回路を形成した
両面銅張り積層板を用いる。そしてこの積層板の両面に
ガラスクロス樹脂含浸布からなるプリプレグを積層す
る。次に、このプリプレグの表面に、回路を形成した銅
張り積層板、プリプレグ及び銅箔を順次積層する。積層
後、積層板やプリプレグ等の左右に設けてある基準用の
穴にピンを立てて位置合わせをし、プレスして加熱加圧
する。プレス後、多層板に板を当てる。そしてこの板が
動かないように端部をテープ等で固定する。この状態
で、ドリルやレーザーを用いて表面の銅箔から1層下の
回路まで非貫通の穴を形成する。その後、ドリル等を用
いて貫通穴を形成する。貫通穴を形成後、当て板を外し
て、無電解銅めっき処理及び電気銅めっき処理をし、各
穴内にめっき層を形成する。次に、テンティングにより
表面の銅箔をエッチングして回路を形成する。
2. Description of the Related Art A multilayer wiring board is manufactured, for example, as follows. That is, a double-sided copper-clad laminate having an inner layer circuit formed on the central substrate is used. Then, a prepreg made of a glass cloth resin-impregnated cloth is laminated on both sides of this laminated plate. Next, a circuit-formed copper-clad laminate, a prepreg, and a copper foil are sequentially laminated on the surface of the prepreg. After the lamination, pins are set up in the reference holes provided on the left and right of the laminated plate, prepreg, etc., and aligned, pressed, and heated and pressed. After pressing, the board is applied to the multilayer board. Then, fix the end with tape or the like so that this plate does not move. In this state, a non-through hole is formed from the copper foil on the surface to the circuit one layer below using a drill or a laser. Then, a through hole is formed using a drill or the like. After forming the through holes, the contact plate is removed, and electroless copper plating treatment and electrolytic copper plating treatment are performed to form a plating layer in each hole. Next, the copper foil on the surface is etched by tenting to form a circuit.

【0003】[0003]

【発明が解決しようとする課題】製造時間を短縮するた
めには、穴開け工程において、複数枚の多層板を重ねて
行えばよい。しかし、この状態では貫通穴は形成できて
も、非貫通穴を形成することはできない。従って、穴開
けは一枚毎に行わなければならず、作業に時間が掛か
り、生産性が低く、製造コストを低下する妨げとなって
いる欠点がある。
In order to reduce the manufacturing time, it is sufficient to stack a plurality of multi-layer boards in the punching step. However, in this state, although the through hole can be formed, the non-through hole cannot be formed. Therefore, there is a drawback that the holes have to be formed one by one, the work takes time, the productivity is low, and the manufacturing cost is hindered.

【0004】本発明の目的は、以上の欠点を改良し、製
造時間を短縮して生産性を向上できるとともに、製造コ
ストを低下できる多層配線板の製造方法を提供するもの
である。
An object of the present invention is to provide a method for manufacturing a multilayer wiring board, which is capable of improving the above drawbacks, shortening the manufacturing time and improving the productivity, and reducing the manufacturing cost.

【0005】[0005]

【課題を解決するための手段】本発明は、上記の目的を
達成するために、内層回路基板の表面に、穴を設けた金
属箔付きの絶縁樹脂シートをラミネートする工程と、こ
の工程後にめっき処理をして前記穴内にめっき層を形成
する工程と、この工程後に外層回路を形成する工程とを
行う多層配線板の製造方法を提供するものである。
In order to achieve the above object, the present invention provides a step of laminating an insulating resin sheet with a metal foil provided with holes on the surface of an inner layer circuit board, and plating after this step. It is intended to provide a method for manufacturing a multilayer wiring board, which comprises a step of performing a treatment to form a plating layer in the hole and a step of forming an outer layer circuit after this step.

【0006】絶縁樹脂シートとしては、エポキシ樹脂や
エポキシ化ポリブタジエン樹脂、フェノール樹脂、変性
ポリアミドイミド樹脂、変性ポリイミド樹脂等の熱硬化
性樹脂を主成分とし、ポリブタジエンやスチレンブタジ
エンゴム、アクリロニトリルゴム、フェノキシ樹脂等の
柔軟性を有する高分子化合物及び無機充填剤を配合した
もの等を用いる。そしてこの絶縁樹脂シートに銅箔を積
層した後、予め穴開け機を用いて穴を開ける。
The insulating resin sheet is mainly composed of a thermosetting resin such as an epoxy resin, an epoxidized polybutadiene resin, a phenol resin, a modified polyamideimide resin or a modified polyimide resin, and is made of polybutadiene, styrene butadiene rubber, acrylonitrile rubber or phenoxy resin. For example, a compound containing a flexible polymer compound and an inorganic filler is used. Then, after laminating a copper foil on this insulating resin sheet, holes are made in advance using a hole making machine.

【0007】また、穴内のめっき層は、無電解めっき処
理及び電解めっき処理を順次行って形成する。
The plating layer in the hole is formed by sequentially performing electroless plating treatment and electrolytic plating treatment.

【0008】[0008]

【作用】内層回路基板の表面に、予め穴を設けた片面金
属箔付きの絶縁シートを積層しているために、非貫通穴
を形成する工程を省略できる。従って、穴開け工程で
は、貫通穴のみを形成すればよく、一度に複数枚を処理
でき、生産性が上がる。
Since the insulating sheet with the one-sided metal foil in which the holes are provided in advance is laminated on the surface of the inner layer circuit board, the step of forming the non-through holes can be omitted. Therefore, in the punching step, only the through holes need to be formed, a plurality of sheets can be processed at one time, and the productivity is increased.

【0009】[0009]

【実施例】以下、本発明を実施例に基づいて説明する。 実施例1:中心の基板には、図1(イ)に示す通り、内
層に2層の回路1を設け、外側の両面に銅箔2を張り付
けた内層2層回路入り両面銅張り積層板3を用いる。こ
の積層板3には、端に予め基準用の穴4を設けておく。
そして銅箔2表面をエッチングして、図1(ロ)に示す
通り、回路5を形成する。回路5を形成後、この回路5
表面を酸化還元処理する。
EXAMPLES The present invention will be described below based on examples. Example 1: As shown in FIG. 1 (a), a central substrate is provided with a two-layer circuit 1 on an inner layer, and copper foils 2 are attached to both outer surfaces of the inner layer. To use. This laminated plate 3 is provided with a reference hole 4 at its end in advance.
Then, the surface of the copper foil 2 is etched to form a circuit 5 as shown in FIG. After forming the circuit 5, this circuit 5
The surface is subjected to redox treatment.

【0010】また、片面金属箔付きの絶縁樹脂シート6
は、図1(ハ)に示す通り、厚さ200μmの絶縁樹脂
シート7の片面に、このシート7に接する面を粗化した
銅箔8を積層し、温度160℃、圧力2〜5kg/cm2
60分間プレスし、加熱加圧し、500mm×1000mm
角に形成したものとする。そしてこのシート6に横型小
径穴開け機により、0.2φの穴9を開ける。穴9開け
後、200mm×500mm角に断裁するとともに、両端部
に基準用の穴10を形成する。
An insulating resin sheet 6 with a metal foil on one side is also provided.
As shown in FIG. 1C, a copper foil 8 having a surface in contact with the sheet 7 is laminated on one surface of an insulating resin sheet 7 having a thickness of 200 μm, and the temperature is 160 ° C. and the pressure is 2 to 5 kg / cm. Press for 2 minutes for 60 minutes, heat and pressurize, 500mm × 1000mm
It shall be formed in the corner. Then, a hole 9 of 0.2φ is made in this sheet 6 by a horizontal small-diameter punching machine. After the hole 9 is formed, it is cut into a 200 mm × 500 mm square, and the reference holes 10 are formed at both ends.

【0011】次に、図1(ニ)に示す通り、両面銅張り
積層板3にこのシート6を積層する。この際、シート6
に設けた穴9を積層板3に設けた回路5の上に配置す
る。なお、回路5表面を酸化還元処理しているため、密
着性が良好になる。積層後、積層板3とシート6に設け
た基準用の穴4及び10にピン11を立てて位置決めす
る。そして、プレスして加熱加圧し、積層板3にシート
6を密着する。
Next, as shown in FIG. 1D, the sheet 6 is laminated on the double-sided copper-clad laminate 3. At this time, sheet 6
The hole 9 provided in the circuit board 5 is arranged on the circuit 5 provided in the laminated plate 3. Since the surface of the circuit 5 is subjected to the redox treatment, the adhesion is good. After stacking, the pins 11 are set up in the reference holes 4 and 10 provided in the laminate 3 and the sheet 6 and positioned. Then, the sheet 6 is pressed and heated and pressed to bring the sheet 6 into close contact with the laminated plate 3.

【0012】プレス後、図1(ホ)に示す通り、ドリル
等によりシート6及び積層板3を貫通する穴12を形成
する。貫通穴12を形成後、スミア処理をしてスミアを
除去する。
After the pressing, as shown in FIG. 1 (e), holes 12 penetrating the sheet 6 and the laminated plate 3 are formed by a drill or the like. After the through hole 12 is formed, smearing is performed to remove the smear.

【0013】スミア処理後、無電解銅めっき処理及び電
解銅めっき処理をして、図1(ヘ)に示す通り、非貫通
穴9及び貫通穴12内に各々銅めっき層13及び14を
形成する。
After smearing, electroless copper plating and electrolytic copper plating are performed to form copper plating layers 13 and 14 in the non-through holes 9 and the through holes 12, respectively, as shown in FIG. ..

【0014】銅めっき層13及び14を形成後、図1
(ト)に示す通り、テンティング法によりシート7表面
の銅箔8を処理して、外層回路15を形成する。
After forming the copper plating layers 13 and 14, FIG.
As shown in (g), the outer layer circuit 15 is formed by treating the copper foil 8 on the surface of the sheet 7 by the tenting method.

【0015】外層回路15を形成後、図1(チ)に示す
通り、はんだレジスト印刷をして、はんだレジスト層1
6を形成する。
After the outer layer circuit 15 is formed, solder resist printing is performed to form the solder resist layer 1 as shown in FIG.
6 is formed.

【0016】次に、上記実施例1及び従来例につき、層
間密着性及び銅箔の引き剥し強さを求め、熱衝撃試験を
行った。
Next, for the above-mentioned Example 1 and the conventional example, the interlayer adhesion and the peel strength of the copper foil were determined and a thermal shock test was conducted.

【0017】従来例の製造方法は次の通りとする。 従来例1:図2(イ)に示す通り、両面に回路21を形
成した両面銅張り積層板22を2枚、ガラスクロス樹脂
含浸布のプリプレグ23を介して積層するとともに、反
対側にも各々同材質のプリプレグ24及び25を重ね
る。さらに、このプリプレグ24及び25には各々銅箔
26及び27を重ねる。そして、積層板22、プリプレ
グ23〜25、銅箔26及び27に各々設けた基準穴2
8〜33にピン34を通して、互いに位置合わせをす
る。位置合わせ後、プレスして加熱加圧し、互いに密着
させる。プレス後、図2(ロ)に示す通り、ドリルによ
り、最外層の回路から1層下の層まで、0.2φの穴3
5を開ける。また、ドリルにより、各層を貫通する穴3
6を開ける。穴35及び36を開けた後、実施例1と同
じ方法で無電解銅めっき処理及び電解銅めっき処理をし
て穴内にめっき層を形成する。さらに、実施例1と同一
の方法により最外層の回路及びはんだレジスト層を形成
する。
The manufacturing method of the conventional example is as follows. Conventional Example 1: As shown in FIG. 2 (a), two double-sided copper-clad laminates 22 each having a circuit 21 formed on both sides thereof are laminated via a prepreg 23 of a glass cloth resin impregnated cloth, and the opposite sides are also laminated with each other. The prepregs 24 and 25 of the same material are piled up. Further, copper foils 26 and 27 are overlaid on the prepregs 24 and 25, respectively. Then, the reference holes 2 provided in the laminated plate 22, the prepregs 23 to 25, and the copper foils 26 and 27, respectively.
Align pins 8 to 33 with each other through pins 34. After alignment, press and heat and press to bring them into close contact with each other. After pressing, as shown in Fig. 2 (b), with a drill, from the circuit of the outermost layer to the layer one layer below, a hole 3 of 0.2φ is formed.
Open 5 Also, a hole 3 that penetrates each layer with a drill
Open 6 After forming the holes 35 and 36, electroless copper plating and electrolytic copper plating are performed in the same manner as in Example 1 to form a plating layer in the holes. Further, the outermost circuit and the solder resist layer are formed by the same method as in the first embodiment.

【0018】また、層間密着性、銅箔引き剥し強さ及び
熱衝撃試験の各評価及び回路パターンは次の通りとす
る。
The interlayer adhesion, copper foil peeling strength, and thermal shock test evaluations and circuit patterns are as follows.

【0019】i)層間密着性 温度260℃のはんだ槽に試料をディップし、密着不良
部分にふくれが発生した時間を測定する。また、回路パ
ターンには、JIS−C5012多層プリント板用複合
テストパターン9を用いる。
I) Interlayer adhesion The sample is dipped in a solder bath at a temperature of 260 ° C., and the time at which swelling occurs in the poor adhesion area is measured. As the circuit pattern, the JIS-C5012 multilayer printed board composite test pattern 9 is used.

【0020】ii)銅箔引き剥し強さ 表面銅箔の一部を予め剥し、この剥した部分をピンで止
め、オートグラフを用いて、5mm/分の速さで剥し、そ
の時のcm当りの荷重を求めた。また、回路パターンは層
間密着性に用いたのと同じパターンとする。
Ii) Copper foil peeling strength A portion of the surface copper foil is peeled off in advance, the peeled portion is fixed with a pin, and peeled off at a speed of 5 mm / min using an autograph. The load was calculated. The circuit pattern is the same as that used for interlayer adhesion.

【0021】iii)熱衝撃試験 JIS−C5012の温湿度サイクル65℃、93%、
4Hrと25℃、80%、1Hrを繰り返し、貫通する
穴のめっき層の抵抗が初期値に対して10%まで上昇す
るサイクル数を求めた。また、回路パターンはJIS−
C5012多層プリント板用複合テストパターンLを用
いる。
Iii) Thermal shock test JIS-C5012 temperature and humidity cycle 65 ° C., 93%,
By repeating 4 Hr, 25 ° C., 80%, and 1 Hr, the number of cycles at which the resistance of the plated layer of the through hole increased to 10% of the initial value was determined. The circuit pattern is JIS-
A composite test pattern L for C5012 multilayer printed board is used.

【0022】測定結果は表1の通りとなった。The measurement results are shown in Table 1.

【表1】 [Table 1]

【0023】表1から明らかな通り、実施例1によれば
従来例1と同等の結果が得られる。また、層間密着性及
び銅箔引き剥し強さについてはJIS規格値を十分に満
足する。
As is clear from Table 1, according to Example 1, the same result as that of Conventional Example 1 can be obtained. Further, the interlayer adhesion and the peel strength of the copper foil sufficiently satisfy the JIS standard values.

【0024】また、本発明と従来例とについて、層間の
絶縁抵抗の変化を測定した。本発明の実施例及び従来例
の製造条件は次の通りとする。
The change in insulation resistance between layers was measured for the present invention and the conventional example. The manufacturing conditions of the example of the present invention and the conventional example are as follows.

【0025】実施例2:実施例1において、回路パター
ンにJIS−C5012多層プリント板用複合テストパ
ターンMを用いるとともに、絶縁樹脂シートの厚さを1
00μmとする以外は、同一の条件で製造する。
Example 2 In Example 1, the composite test pattern M for JIS-C5012 multilayer printed board was used as the circuit pattern, and the thickness of the insulating resin sheet was set to 1
It is manufactured under the same conditions except that the thickness is set to 00 μm.

【0026】実施例3:実施例2において、絶縁樹脂シ
ートの厚さを200μmとする以外は、同一の条件で製
造する。
Example 3: The procedure of Example 2 was repeated except that the insulating resin sheet had a thickness of 200 μm.

【0027】従来例2:従来例1において、ガラスクロ
ス樹脂含浸布のプリプレグの厚さを100μmとする以
外は、同一の条件で製造する。
Conventional Example 2: In Conventional Example 1, the glass cloth resin-impregnated cloth is manufactured under the same conditions except that the thickness of the prepreg is 100 μm.

【0028】従来例3:従来例1において、ガラスクロ
ス樹脂含浸布のプリプレグの厚さを200μmとする以
外は、同一の条件で製造する。
Conventional Example 3: Manufactured under the same conditions as in Conventional Example 1, except that the thickness of the prepreg of the glass cloth resin-impregnated cloth is 200 μm.

【0029】そして試験は、試料を温度85℃、湿度8
5%RHの雰囲気中に、回路にDC100Vを印加し
て、1000時間放置する。また、絶縁抵抗はDC25
0Vを印加して1分値で測定した。
Then, the test was conducted with the sample at a temperature of 85 ° C. and a humidity of 8
DC100V is applied to the circuit in an atmosphere of 5% RH and left for 1000 hours. Insulation resistance is DC25
0 V was applied and the value was measured for 1 minute.

【0030】測定結果は表2の通りになった。The measurement results are shown in Table 2.

【表2】 [Table 2]

【0031】表2から明らかな通り、実施例2及び実施
例3によれば、従来例2及び従来例3とほぼ同一の絶縁
抵抗が得られる。特に、厚さの薄い方の実施例2は従来
例2よりも優れた結果が得られた。
As is apparent from Table 2, according to the second and third embodiments, the same insulation resistance as that of the second and third conventional examples can be obtained. In particular, the thinner example 2 obtained better results than the conventional example 2.

【0032】[0032]

【発明の効果】以上の通り、本発明の製造方法によれ
ば、予め穴を設けた金属箔付きの絶縁樹脂シートをラミ
ネートしているため、穴開け工程での処理時間を短縮で
き、全体として製造時間を短くでき、生産性が向上し、
製造コストを低下できる多層配線板が得られる。また、
本発明の製造方法によれば、必ずしもガラスクロス樹脂
含浸布を用いなくてもよい。従って、レーザーにより穴
開けした場合に、ガラス糸が残りめっき処理後に穴の形
状が悪くなったり、めっきが付着しなかったりすること
なく、不良を低減でき信頼性の高い多層配線板が得られ
る。さらに、ドリルにより穴開けする場合に、比較的に
切削の抵抗力の高いガラスクロス樹脂含浸布を用いる必
要があるときは、ドリルの寿命を長くでき、ドリルを交
換する作業が少なくてすむためより生産性が向上しコス
トを低減できる多層配線板が得られる。
As described above, according to the manufacturing method of the present invention, since the insulating resin sheet with the metal foil in which the holes are provided in advance is laminated, the processing time in the perforating step can be shortened, and as a whole. Manufacturing time can be shortened, productivity is improved,
A multilayer wiring board that can reduce the manufacturing cost can be obtained. Also,
According to the manufacturing method of the present invention, it is not always necessary to use the glass cloth resin-impregnated cloth. Therefore, when holes are drilled by a laser, the glass thread remains and the shape of the holes does not deteriorate after the plating treatment, or the plating does not adhere, and it is possible to reduce defects and obtain a highly reliable multilayer wiring board. Furthermore, when drilling with a drill, if it is necessary to use a glass cloth resin impregnated cloth that has relatively high cutting resistance, the life of the drill can be extended and less drill replacement work is required. A multilayer wiring board with improved productivity and reduced cost can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の製造工程の図面を示す。FIG. 1 shows a drawing of a manufacturing process according to an embodiment of the present invention.

【図2】従来例の製造工程の図面を示す。FIG. 2 shows a drawing of a manufacturing process of a conventional example.

【符号の説明】[Explanation of symbols]

3…内層2層回路入り両面銅張り積層板、6…片面金属
箔付きの絶縁樹脂シート、 9…穴、 13…銅めっき
層、15…外層回路。
3 ... Inner layer, double-sided copper clad laminate with circuit, 6 ... Insulating resin sheet with one side metal foil, 9 ... Hole, 13 ... Copper plating layer, 15 ... Outer layer circuit.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 横山 博義 栃木県芳賀郡二宮町大字久下田413番地 日立エーアイシー株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyoshi Yokoyama 413 Kushimoda, Ninomiya-cho, Haga-gun, Tochigi Prefecture Hitachi AIC Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 内層回路基板の表面に、穴を設けた金属
箔付きの絶縁樹脂シートをラミネートする工程と、この
工程後にめっき処理をして前記穴内にめっき層を形成す
る工程と、この工程後に外層回路を形成する工程とを行
う多層配線板の製造方法。
1. A step of laminating an insulating resin sheet with a metal foil provided with holes on the surface of an inner layer circuit board, a step of plating after this step to form a plating layer in the holes, and this step A method of manufacturing a multilayer wiring board, the method further comprising the step of forming an outer layer circuit later.
JP8487092A 1992-03-07 1992-03-07 Manufacture of multi-layered circuit board Pending JPH05251867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8487092A JPH05251867A (en) 1992-03-07 1992-03-07 Manufacture of multi-layered circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8487092A JPH05251867A (en) 1992-03-07 1992-03-07 Manufacture of multi-layered circuit board

Publications (1)

Publication Number Publication Date
JPH05251867A true JPH05251867A (en) 1993-09-28

Family

ID=13842838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8487092A Pending JPH05251867A (en) 1992-03-07 1992-03-07 Manufacture of multi-layered circuit board

Country Status (1)

Country Link
JP (1) JPH05251867A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4845543A (en) * 1983-09-28 1989-07-04 Hitachi, Ltd. Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4845543A (en) * 1983-09-28 1989-07-04 Hitachi, Ltd. Semiconductor device and method of manufacturing the same

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