JPH05259643A - Manufacture of multilayer wiring board - Google Patents
Manufacture of multilayer wiring boardInfo
- Publication number
- JPH05259643A JPH05259643A JP8976692A JP8976692A JPH05259643A JP H05259643 A JPH05259643 A JP H05259643A JP 8976692 A JP8976692 A JP 8976692A JP 8976692 A JP8976692 A JP 8976692A JP H05259643 A JPH05259643 A JP H05259643A
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- JP
- Japan
- Prior art keywords
- circuit
- layer
- sheet
- treatment
- subjected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は多層配線板の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board.
【0002】[0002]
【従来の技術】多層配線板は、例えば、次の通りに製造
している。すなわち、中心の基板に内層回路を形成した
両面銅張り積層板を用いる。そしてこの積層板の両面に
ガラスクロス樹脂含浸布からなるプリプレグを積層す
る。次に、このプリプレグの表面に、回路を形成した銅
張り積層板、プリプレグ及び銅箔を順次積層する。積層
後、積層板やプリプレグ等の左右に設けてある基準用の
穴にピンを立てて位置合わせをし、プレスして加熱加圧
する。プレス後、多層板に板を当てる。そしてこの板が
動かないように端部をテープ等で固定する。この状態
で、ドリルやレーザーを用いて表面の銅箔から1層下の
回路まで非貫通の穴を形成する。その後、ドリル等を用
いて貫通穴を形成する。貫通穴を形成後、当て板を外し
て、無電解銅めっき処理及び電気銅めっき処理をし、各
穴内にめっき層を形成する。次に、表面の銅箔をエッチ
ングして回路を形成する。2. Description of the Related Art A multilayer wiring board is manufactured, for example, as follows. That is, a double-sided copper-clad laminate having an inner layer circuit formed on the central substrate is used. Then, a prepreg made of a glass cloth resin-impregnated cloth is laminated on both sides of this laminated plate. Next, a circuit-formed copper-clad laminate, a prepreg, and a copper foil are sequentially laminated on the surface of the prepreg. After the lamination, pins are set up in the reference holes provided on the left and right of the laminated plate, prepreg, etc., and aligned, pressed, and heated and pressed. After pressing, the board is applied to the multilayer board. Then, fix the end with tape or the like so that this plate does not move. In this state, a non-through hole is formed from the copper foil on the surface to the circuit one layer below using a drill or a laser. Then, a through hole is formed using a drill or the like. After forming the through holes, the contact plate is removed, and electroless copper plating treatment and electrolytic copper plating treatment are performed to form a plating layer in each hole. Next, the copper foil on the surface is etched to form a circuit.
【0003】[0003]
【発明が解決しようとする課題】製造時間を短縮するた
めには、穴開け工程において、複数枚の多層板を重ねて
行えばよい。しかし、この状態では貫通穴は形成できて
も、非貫通穴を形成することはできない。従って、穴開
けは一枚毎に行わなければならず、作業に時間が掛か
り、生産性が低く、製造コストを低下する妨げとなって
いる欠点がある。In order to reduce the manufacturing time, it is sufficient to stack a plurality of multi-layer boards in the punching step. However, in this state, although the through hole can be formed, the non-through hole cannot be formed. Therefore, there is a drawback that the holes have to be formed one by one, the work takes time, the productivity is low, and the manufacturing cost is hindered.
【0004】本発明の目的は、以上の欠点を改良し、製
造時間を短縮して生産性を向上できるとともに、製造コ
ストを低下できる多層配線板の製造方法を提供するもの
である。An object of the present invention is to provide a method for manufacturing a multilayer wiring board, which is capable of improving the above drawbacks, shortening the manufacturing time and improving the productivity, and reducing the manufacturing cost.
【0005】[0005]
【課題を解決するための手段】本発明は、上記の目的を
達成するために、内層回路基板の表面に、絶縁樹脂層と
接着剤層とからなる穴を設けた複合層シートをラミネー
トする工程と、この工程後にめっき処理をして前記穴内
にめっき層を形成するとともに外層回路を形成する工程
とを行う多層配線板の製造方法を提供するものである。In order to achieve the above object, the present invention is a process for laminating a composite layer sheet having holes made of an insulating resin layer and an adhesive layer on the surface of an inner layer circuit board. And a step of performing a plating treatment after this step to form a plated layer in the hole and an outer layer circuit, and to provide a method for manufacturing a multilayer wiring board.
【0006】絶縁樹脂層としては、エポキシ樹脂やエポ
キシ化ポリブタジエン樹脂、フェノール樹脂、変性ポリ
アミドイミド樹脂、変性ポリイミド樹脂等の熱硬化性樹
脂を主成分とし、ポリブタジエンやスチレンブタジエン
ゴム、アクリロニトリルゴム、フェノキシ樹脂等の柔軟
性を有する高分子化合物及び無機充填剤を配合したもの
等を用いる。そしてこの絶縁樹脂層と接着剤層とを積層
して複合層シートを形成した後、予め穴開け機を用いて
このシートに穴を開ける。The insulating resin layer contains a thermosetting resin such as an epoxy resin, an epoxidized polybutadiene resin, a phenol resin, a modified polyamideimide resin or a modified polyimide resin as a main component, and contains polybutadiene, styrene butadiene rubber, acrylonitrile rubber or phenoxy resin. For example, a compound containing a flexible polymer compound and an inorganic filler is used. Then, the insulating resin layer and the adhesive layer are laminated to form a composite layer sheet, and then a hole is punched in advance using a punching machine.
【0007】[0007]
【作用】内層回路基板の表面に、予め穴を設けた絶縁樹
脂層と接着剤層とからなる複合層シートを積層している
ために、非貫通穴を形成する工程を省略できる。従っ
て、穴開け工程では、貫通穴のみを形成すればよく、一
度に複数枚を処理でき、生産性が上がる。Since the composite layer sheet including the insulating resin layer and the adhesive layer, which are preliminarily provided with holes, is laminated on the surface of the inner layer circuit board, the step of forming the non-through holes can be omitted. Therefore, in the punching step, only the through holes need to be formed, a plurality of sheets can be processed at one time, and the productivity is increased.
【0008】[0008]
【実施例】以下、本発明を実施例に基づいて説明する。 実施例1:中心の基板には、図1(イ)に示す通り、内
層に2層の回路1を設け、外側の両面に銅箔2を張り付
けた内層2層回路入り両面銅張り積層板3を用いる。そ
して銅箔2表面をエッチングして、図1(ロ)に示す通
り、回路4を形成する。その後、この回路4表面を酸化
還元処理する。EXAMPLES The present invention will be described below based on examples. Example 1: As shown in FIG. 1 (a), a central substrate is provided with a two-layer circuit 1 on an inner layer, and copper foils 2 are attached to both outer surfaces of the inner layer. To use. Then, the surface of the copper foil 2 is etched to form a circuit 4 as shown in FIG. Then, the surface of the circuit 4 is subjected to redox treatment.
【0009】また、複合層シート5は、図1(ハ)に示
す通り、厚さ180μmの絶縁樹脂フィルム6と厚さ2
0μmの接着剤フィルム7とを積層して全体の厚さを2
00μmとしたもので、予め0.2φの穴8を設けてあ
る。The composite layer sheet 5 has an insulating resin film 6 having a thickness of 180 μm and a thickness of 2 as shown in FIG.
0 μm adhesive film 7 is laminated to make the total thickness 2
The diameter is set to 00 μm, and a hole 8 having a diameter of 0.2φ is provided in advance.
【0010】次に、図1(ニ)に示す通り、両面銅張り
積層板3にこの複合層シート5を真空ラミネータでラミ
ネートする。この際、複合層シート5に設けた穴8を積
層板3に設けた回路4の上に配置する。なお、回路4表
面を酸化還元処理しているため、密着性が良好になる。Next, as shown in FIG. 1D, the composite layer sheet 5 is laminated on the double-sided copper-clad laminate 3 with a vacuum laminator. At this time, the holes 8 provided in the composite layer sheet 5 are arranged on the circuit 4 provided in the laminate 3. Since the surface of the circuit 4 is subjected to the redox treatment, the adhesion is good.
【0011】ラミネート後、図1(ホ)に示す通り、ド
リル等により複合層シート5及び積層板3を貫通する穴
9を形成する。貫通穴9を形成後、スミア処理をしてス
ミアを除去する。After laminating, as shown in FIG. 1 (e), a hole 9 penetrating the composite layer sheet 5 and the laminated plate 3 is formed by a drill or the like. After forming the through hole 9, smearing is performed to remove the smear.
【0012】スミア処理後、ジーダー処理及び無電解め
っき処理を行い、図1(ヘ)に示す通り、非貫通穴8及
び貫通穴9に各々めっき層10及び11を形成する。After the smearing treatment, a jider treatment and an electroless plating treatment are performed to form plating layers 10 and 11 in the non-through holes 8 and the through holes 9, respectively, as shown in FIG.
【0013】めっき層10及び11を形成した後、図1
(ト)に示す通り、エッチング処理をして、外層回路1
2を形成する。After forming the plating layers 10 and 11, FIG.
As shown in (g), the outer layer circuit 1 is subjected to etching treatment.
Form 2.
【0014】外層回路12を形成後、図1(チ)に示す
通り、はんだレジスト印刷をして、はんだレジスト層1
3を形成する。After the outer layer circuit 12 is formed, solder resist printing is performed as shown in FIG.
3 is formed.
【0015】次に、上記実施例1及び従来例1につき、
層間密着性及び銅箔の引き剥し強さを求め、且つ熱衝撃
試験を行った。Next, with respect to the first embodiment and the conventional example 1,
The interlayer adhesion and the peel strength of the copper foil were determined, and a thermal shock test was conducted.
【0016】従来例1の製造方法は次の通りとする。 従来例1:図2(イ)に示す通り、両面に回路21を形
成した両面銅張り積層板22を2枚、ガラスクロス樹脂
含浸布のプリプレグ23を介して積層するとともに、反
対側にも各々同材質のプリプレグ24及び25を重ね
る。さらに、このプリプレグ24及び25には各々銅箔
26及び27を重ねる。そして、積層板22、プリプレ
グ23〜25、銅箔26及び27に各々設けた基準穴2
8〜33にピン34を通して、互いに位置合わせをす
る。位置合わせ後、プレスして加熱加圧し、互いに密着
させる。各プリプレグ23〜25の厚さは200μmと
する。プレス後、図2(ロ)に示す通り、ドリルによ
り、銅箔26及び27から以下の回路21まで、0.2
φの穴35を開ける。また、ドリルにより、各層を貫通
する穴36を開ける。穴35及び36を開けた後、図2
(ハ)に示す通り、無電解銅めっき処理及び電解銅めっ
き処理をして穴35及び36内に各々めっき層37及び
38を形成する。さらに、図2(ニ)に示す通り、エッ
チング処理により外層回路39を形成する。そしてはん
だレジスト印刷をしてはんだレジスト層40を形成す
る。The manufacturing method of Conventional Example 1 is as follows. Conventional Example 1: As shown in FIG. 2 (a), two double-sided copper-clad laminates 22 each having a circuit 21 formed on both sides thereof are laminated via a prepreg 23 of a glass cloth resin impregnated cloth, and the opposite sides are also laminated with each other. The prepregs 24 and 25 of the same material are piled up. Further, copper foils 26 and 27 are overlaid on the prepregs 24 and 25, respectively. Then, the reference holes 2 provided in the laminated plate 22, the prepregs 23 to 25, and the copper foils 26 and 27, respectively.
Align pins 8 to 33 with each other through pins 34. After alignment, press and heat and press to bring them into close contact with each other. The thickness of each prepreg 23 to 25 is 200 μm. After pressing, as shown in FIG. 2B, a copper foil 26 and 27 up to the following circuit 21 is 0.2.
Drill a hole 35 of φ. Moreover, a hole 36 penetrating each layer is opened by a drill. After drilling holes 35 and 36, FIG.
As shown in (c), electroless copper plating and electrolytic copper plating are performed to form plating layers 37 and 38 in the holes 35 and 36, respectively. Further, as shown in FIG. 2D, the outer layer circuit 39 is formed by etching. Then, solder resist printing is performed to form the solder resist layer 40.
【0017】また、層間密着性、銅箔引き剥し強さ及び
熱衝撃試験の各評価及び回路パターンは次の通りとす
る。The interlayer adhesion, copper foil peeling strength, and thermal shock test evaluations and circuit patterns are as follows.
【0018】i)層間密着性 温度260℃のはんだ槽に試料をディップし、密着不良
部分にふくれが発生した時間を測定する。また、回路パ
ターンには、JIS−C5012多層プリント板用複合
テストパターンGを用いる。I) Interlayer adhesion The sample is dipped in a solder bath at a temperature of 260 ° C., and the time at which swelling occurs in the poor adhesion portion is measured. As the circuit pattern, the JIS-C5012 multilayer printed board composite test pattern G is used.
【0019】ii)銅箔引き剥し強さ 表面銅箔の一部を予め剥し、この剥した部分をピンで止
め、オートグラフを用いて、5mm/分の速さで剥し、そ
の時のcm当りの荷重を求めた。また、回路パターンは層
間密着性に用いたのと同じパターンとする。Ii) Copper foil peeling strength A portion of the surface copper foil was peeled off in advance, the peeled portion was fixed with a pin, and peeled at a speed of 5 mm / min using an autograph. The load was calculated. The circuit pattern is the same as that used for interlayer adhesion.
【0020】iii)熱衝撃試験 JIS−C5012の温湿度サイクル65℃、93%、
4Hrと25℃、80%、1Hrを繰り返し、貫通する
穴のめっき層の抵抗が初期値に対して10%まで上昇す
るサイクル数を求めた。また、回路パターンはJIS−
C5012多層プリント板用複合テストパターンLを用
いる。Iii) Thermal shock test JIS-C5012 temperature / humidity cycle 65 ° C., 93%,
By repeating 4 Hr, 25 ° C., 80%, and 1 Hr, the number of cycles at which the resistance of the plated layer of the through hole increased to 10% of the initial value was determined. The circuit pattern is JIS-
A composite test pattern L for C5012 multilayer printed board is used.
【0021】測定結果は表1の通りとなった。The measurement results are shown in Table 1.
【表1】 [Table 1]
【0022】表1から明らかな通り、実施例1によれば
従来例1と同等の結果が得られる。また、層間密着性及
び銅箔引き剥し強さについてはJIS規格値を十分に満
足する。As is clear from Table 1, according to Example 1, the same result as that of Conventional Example 1 can be obtained. Further, the interlayer adhesion and the peel strength of the copper foil sufficiently satisfy the JIS standard values.
【0023】また、本発明と従来例とについて、層間の
絶縁抵抗の変化を測定した。本発明の実施例2及び従来
例2の製造条件は次の通りとする。なお、測定に用いた
回路パターンは、実施例及び従来例ともJIS−C50
12多層プリント板用複合テストパターンMとする。The changes in the insulation resistance between the layers of the present invention and the conventional example were measured. The manufacturing conditions of Example 2 of the present invention and Conventional Example 2 are as follows. The circuit patterns used for the measurement are JIS-C50 in both the example and the conventional example.
A composite test pattern M for a 12-layer printed board is used.
【0024】実施例2:実施例1において、複合層シー
トを厚さ80μmの絶縁樹脂フィルムに厚さ20μmの
接着剤フィルムを積層し、厚さ100μmとする以外
は、同一条件とする。Example 2 The same conditions as in Example 1 were used except that the composite layer sheet was laminated to an insulating resin film having a thickness of 80 μm and an adhesive film having a thickness of 20 μm so as to have a thickness of 100 μm.
【0025】従来例2:従来例1において、ガラスクロ
ス樹脂含浸布のプリプレグの厚さを100μmとする以
外は、同一の条件とする。Conventional Example 2: Same conditions as in Conventional Example 1 except that the thickness of the prepreg of the glass cloth resin-impregnated cloth is 100 μm.
【0026】そして試験は、試料を温度85℃、湿度8
5%RHの雰囲気中に、回路にDC100Vを印加し
て、1000時間放置する。また、絶縁抵抗はDC25
0Vを印加して1分値で測定した。Then, the test was conducted with the sample at a temperature of 85 ° C. and a humidity of 8
DC100V is applied to the circuit in an atmosphere of 5% RH and left for 1000 hours. Insulation resistance is DC25
0 V was applied and the value was measured for 1 minute.
【0027】測定結果は表2の通りになった。以下余
白。The measurement results are shown in Table 2. The margin below.
【表2】 [Table 2]
【0028】表2から明らかな通り、実施例1及び実施
例2によれば、従来例1及び従来例2とほぼ同一の絶縁
抵抗が得られる。特に、厚さの薄い方の実施例2は従来
例2よりも優れた結果が得られた。As is clear from Table 2, according to Examples 1 and 2, almost the same insulation resistance as that of Conventional Example 1 and Conventional Example 2 can be obtained. In particular, the thinner example 2 obtained better results than the conventional example 2.
【0029】[0029]
【発明の効果】以上の通り、本発明の製造方法によれ
ば、予め穴を設けた絶縁樹脂層と接着剤層とからなる複
合層シートをラミネートしているため、穴開け工程での
処理時間を短縮でき、全体として製造時間を短くでき、
生産性が向上し、製造コストを低下できる多層配線板が
得られる。また、本発明の製造方法によれば、必ずしも
ガラスクロス樹脂含浸布を用いなくてもよい。従って、
レーザーにより穴開けした場合に、ガラス糸が残りめっ
き処理後に穴の形状が悪くなったり、めっきが付着しな
かったりすることなく、不良を低減でき信頼性の高い多
層配線板が得られる。さらに、ドリルにより穴開けする
場合に、比較的に切削の抵抗力の高いガラスクロス樹脂
含浸布を用いる必要があるときは、ドリルの寿命を長く
でき、ドリルを交換する作業が少なくてすむためより生
産性が向上しコストを低減できる多層配線板が得られ
る。As described above, according to the manufacturing method of the present invention, since the composite layer sheet consisting of the insulating resin layer and the adhesive layer, which are preliminarily provided with holes, is laminated, the processing time in the punching step is increased. Can be shortened, the manufacturing time can be shortened as a whole,
A multilayer wiring board having improved productivity and reduced manufacturing cost can be obtained. Further, according to the manufacturing method of the present invention, it is not always necessary to use the glass cloth resin-impregnated cloth. Therefore,
When holes are drilled with a laser, glass threads remain and the shape of the holes does not deteriorate after the plating treatment, or the plating does not adhere, and it is possible to reduce defects and obtain a highly reliable multilayer wiring board. Furthermore, when drilling with a drill, if it is necessary to use a glass cloth resin impregnated cloth that has relatively high cutting resistance, the life of the drill can be extended and less drill replacement work is required. A multilayer wiring board with improved productivity and reduced cost can be obtained.
【図1】本発明の実施例の製造工程の図面を示す。FIG. 1 shows a drawing of a manufacturing process according to an embodiment of the present invention.
【図2】従来例の製造工程の図面を示す。FIG. 2 shows a drawing of a manufacturing process of a conventional example.
3…両面銅張り積層板、 5…複合層シート、 6…絶
縁樹脂フィルム、7…接着剤フィルム、 8…穴、 1
0,11…めっき層、12…外層回路。3 ... Double-sided copper-clad laminate, 5 ... Composite layer sheet, 6 ... Insulating resin film, 7 ... Adhesive film, 8 ... Hole, 1
0, 11 ... Plating layer, 12 ... Outer layer circuit.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 横山 博義 栃木県芳賀郡二宮町大字久下田413番地 日立エーアイシー株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyoshi Yokoyama 413 Kushimoda, Ninomiya-cho, Haga-gun, Tochigi Prefecture Hitachi AIC Co., Ltd.
Claims (1)
着剤層とからなる穴を設けた複合層シートをラミネート
する工程と、この工程後にめっき処理をして前記穴内に
めっき層を形成するとともに外層回路を形成する工程と
を行う多層配線板の製造方法。1. A step of laminating a composite layer sheet having a hole formed of an insulating resin layer and an adhesive layer on the surface of an inner layer circuit board, and a plating treatment is performed after this step to form a plating layer in the hole. And a step of forming an outer layer circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8976692A JPH05259643A (en) | 1992-03-13 | 1992-03-13 | Manufacture of multilayer wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8976692A JPH05259643A (en) | 1992-03-13 | 1992-03-13 | Manufacture of multilayer wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05259643A true JPH05259643A (en) | 1993-10-08 |
Family
ID=13979831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8976692A Pending JPH05259643A (en) | 1992-03-13 | 1992-03-13 | Manufacture of multilayer wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05259643A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0744884A2 (en) * | 1995-05-23 | 1996-11-27 | Hitachi Chemical Company, Ltd. | Process for producing multilayer printed circuit board |
-
1992
- 1992-03-13 JP JP8976692A patent/JPH05259643A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0744884A2 (en) * | 1995-05-23 | 1996-11-27 | Hitachi Chemical Company, Ltd. | Process for producing multilayer printed circuit board |
EP0744884A3 (en) * | 1995-05-23 | 1997-09-24 | Hitachi Chemical Co Ltd | Process for producing multilayer printed circuit board |
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