JPH05250873A - Semiconductor integration circuit - Google Patents

Abstract

PURPOSE:To hold substrate potential when a control signal is an active level and an oscillation frequency is high the substrate potential is held to required potential and to reduce current consumption by providing the switching circuit of an oscillator signal between a first and a second inverters. CONSTITUTION:The switching circuit 3 is provided between the first inverter IV3 and the second inverter IV4. The switching circuit 3 is constituted of transfer gates TG1, TG2 and the inverter IV6. When the control signal RAS becomes the active level, the gate TG2 is conducted and the gate TG1 is not conducted and the output signal OSC of an oscillator 1 is transmitted to the IV4 directly. Then, since the OSC signal with a short rise and fall is entered the second inverter IV4 directly even though rise and fall intervals due to the inverters IV2, IV3 become long, the intervals of a high level, a low level become long and the substrate potential VBB is held to required potential and penetration current, as well is reduced and current consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit such as a memory circuit including a substrate potential generation circuit.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit of this type, as shown in FIG. 4 as an example, an odd number of stages (three stages in this example) of inverters composed of vertically stacked four-stage P-channel and N-channel transistors are formed in a ring shape. P-channel and N-channel transistors Q1 to Q3 connected in parallel with three-stage transistors of four vertically-stacked transistors that are turned on when the control signal RAS becomes an active level (low level). , Q4 to Q6, and control signal RA
When S is at an active level, it has a first frequency, and when S is at an inactive level, it has a second frequency signal (OS) lower than the first frequency.
C) and the first inverters IV2 and IV for shaping the output signal OSC of the oscillator circuit 1.
3, a second inverter IV4 that shapes the output signals of the first inverters IV2 and IV3, an inverter IV5, capacitors C1 and C2 and P-channel transistors Q7 and Q8, and an output signal of the second inverter IV4. And a substrate potential generating section 2 for generating a substrate potential VBB by converting the voltage into a direct current.

Next, the operation of this semiconductor integrated circuit will be described. FIG. 5 is a waveform diagram of signals at various parts for explaining the operation of the semiconductor integrated circuit.

When the control signal RAS is at a high inactive level, the transistors Q1 to Q3 and Q4 to Q6 are off, so that the oscillation circuit is a ring type oscillation circuit having three inverters each having four stages stacked vertically. And oscillate.

When the control signal RAS becomes the active level of low level, the transistors Q1 to Q3 and Q4 to Q6 are turned on, and the three stages of the four vertically stacked transistors are short-circuited by the transistors Q1 to Q3 and Q4 to Q6. Therefore, the on-resistance of the P-channel and N-channel transistors forming each inverter becomes small, and the oscillation circuit 1 oscillates at a higher frequency than when the control signal RAS is at the inactive level.

The output signal OSC of the oscillator circuit 1 is
The waveform is shaped by the second inverters IV2, IV3, IV4 and then input to the substrate potential generation unit 2 to be converted into a direct current,
It is supplied to the substrate as the substrate potential VBB.

When the control signal RAS is at the inactive level, the internal circuit is in a non-operating state. Therefore, the oscillation frequency of the oscillator circuit 1 is lowered to reduce power consumption, and when it is at the active level, the oscillation frequency is increased. Then, a desired substrate potential VBB is obtained.

[0008]

In this conventional semiconductor integrated circuit, the output signal OSC of the oscillation circuit 1 is supplied to the substrate potential generating section 2 through a plurality of stages of inverters IV2 to IV4, and the control signal RAS is at an active level. At this time, the oscillation frequency is increased to obtain the substrate potential when the internal circuit is in the operating state. Therefore, since the frequency characteristics of the inverters IV2 to IV4 do not change, the rise time and the fall time do not change,
When the oscillation frequency becomes higher, the period for which the low level and the high level are kept becomes shorter, which makes it difficult to keep the substrate potential VBB at a desired potential. Further, since the rising and falling periods are longer than the low-level and high-level periods, there is a drawback that the through-current flows through the inverters (eg, IV4 and IV5) on the subsequent stage for a long time, resulting in an increase in current consumption. .

An object of the present invention is to provide a semiconductor integrated circuit capable of maintaining a substrate potential at a desired potential when a control signal is at an active level and reducing current consumption.

[0010]

A semiconductor integrated circuit according to the present invention generates a signal having a first frequency when a control signal is at an active level and outputs a signal having a second frequency lower than the first frequency when the control signal is at an inactive level. An oscillator circuit that generates a signal, a first inverter that shapes the output signal of the oscillator circuit, and when the control signal is at an active level, the output signal of the oscillator circuit is selected and output, and an inactive level is output. In this case, a switching circuit that selects and outputs the output signal of the first inverter, a second inverter that shapes the output signal of the switching circuit, and a substrate potential by converting the output signal of the second inverter into DC. And a substrate potential generating section for generating.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor integrated circuit shown in FIG. 4 in that the first inverters IV2, IV
Between the output terminal of the inverter IV3 of V3 and the input terminal of the second inverter IV4, when the control signal RAS is at the active level (low level), the output signal OSC of the oscillation circuit 1
Is selected and output, and the switching circuit 3 for selecting and outputting the output signal of the first inverter IV3 when it is at the inactive level (high level) is inserted.

The switching circuit 3 has its input terminal connected to the output terminal of the first inverter IV3 and its output terminal connected to the input terminal of the second inverter IV4 so as to be rendered conductive when the control signal RAS is at the inactive level. Become the first transfer gate TG
1 and an input end of the oscillator circuit 1 is connected to the output end (OSC) of the oscillator circuit 1 and an output end thereof is connected to the input end of the second inverter IV4 to be in a conductive state when the control RAS is at an active level. And these transfer gates T
It has a configuration including an inverter IV6 that supplies an inverted signal of the control signal RAS to G1 and TG2.

Next, the operation of this embodiment will be described.
FIG. 2 is a waveform diagram of signals at various parts for explaining the operation of this embodiment.

When the control signal RAS is at the inactive level,
Since the transfer gate TG1 is conductive and the transfer gate TG2 is non-conductive, the circuit is the same as that of the conventional example. At this time, since the internal circuit is in a non-operating state, no problem occurs.

When the control signal RAS becomes the active level, the transfer gate TG2 becomes conductive and the transfer gate TG1 becomes nonconductive, so that the output signal OSC of the oscillation circuit 1 is directly input to the inverter IV4. Therefore, even if the rising and falling periods of the first inverters IV2 and IV3 are long, what is input to the second inverter IV4 is the output signal OSC of the oscillation circuit 1 whose rising and falling periods are short. Therefore, the high-level and low-level periods are longer than the rising and falling periods, and the substrate potential VB
B can be maintained at a desired potential, and the inverter IV
The through current of IV4, IV5, etc. is also reduced, and the current consumption can be reduced.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the switching circuit 3a masks the output signal of the first inverter IV3 to an inactive level when the control signal RAS is at the active level and outputs the masked signal. When the NAND type first logic gate G1 that passes the output signal of the inverter IV3 and the control signal RAS are inactive levels, the output signal OSC of the oscillation circuit 1 is masked and output as an inactive level, and when it is in the active level. Is N that allows the output signal OSC of the oscillation circuit 1 to pass through.
An AND-type second logic gate G2 and a NAND-type third logic gate G3 for integrating the output signals of the first and second logic gates G1 and G2 and transmitting the integrated signals to the input terminal of the second inverter IV4. Although the configuration is different, the function thereof is exactly the same as that of the first embodiment although the configuration is different, and therefore further description will be omitted.

[0020]

As described above, according to the present invention, when the control signal is at the active level, the output signal of the oscillation circuit is directly transmitted to the second inverter without passing through the first inverter, and when the control signal is at the inactive level. By transmitting the signal to the second inverter through the first inverter, the control signal becomes the active level and holds the high level and the low level of the signal input to the second inverter when the oscillation frequency is high. Since the period can be extended, there is an effect that the substrate potential can be kept at a desired potential and current consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.

FIG. 5 is a waveform diagram of signals of respective parts for explaining the operation of the semiconductor integrated circuit shown in FIG.

[Explanation of symbols]

 1 Oscillation circuit 2 Substrate electric potential generation part 3,3a Switching circuit C1, C2 Capacitor G1-G3 Logic gate IV1-IV6 Inverter Q1-Q8 Ton transistor TG1, TG2 Transfer gate

Claims (3)

[Claims] 1. An oscillator circuit which generates a signal having a first frequency when a control signal is at an active level and a signal which has a second frequency lower than the first frequency when the control signal is at an inactive level, and an oscillator circuit of the oscillator circuit. A first inverter that shapes the waveform of the output signal; and, when the control signal is at the active level, selects and outputs the output signal of the oscillation circuit; and when the control signal is at the inactive level, selects the output signal of the first inverter. A switching circuit for outputting the output signal of the switching circuit, a second inverter for shaping the output signal of the switching circuit, and a substrate potential generating section for converting the output signal of the second inverter into a direct current to generate a substrate potential. A characteristic semiconductor integrated circuit. 2. A first switching circuit having an input terminal connected to an output terminal of a first inverter and an output terminal connected to an input terminal of a second inverter, and being in a conductive state when a control signal is at an inactive level. And a second transfer gate whose input end is connected to the output end of the oscillating circuit and whose output end is connected to the input end of the second inverter so that it becomes conductive when the control signal is at an active level. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is provided. 3. The switching circuit masks the output signal of the first inverter to make it inactive when the control signal is at the active level, and outputs it, and outputs the output signal of the first inverter when it is at the inactive level. A first logic gate to pass therethrough; and a second logic gate to mask the output signal of the oscillation circuit when the control signal is at the inactive level and output it as an inactive level, and to pass the output signal of the oscillation circuit at the active level. 2. The semiconductor integrated circuit according to claim 1, further comprising: a logic gate and a third logic gate for integrating output signals of the first and second logic gates and transmitting the integrated signals to an input terminal of the second inverter. circuit.