KR100222397B1 - Clock buffer device - Google Patents

Abstract

Disclosed is a clock buffer device capable of maintaining low power consumption even at high frequencies using a digital tuning scheme. The present invention provides a clock buffer device for generating an output clock signal from an input clock signal having a rising edge and a falling edge, wherein the output clock is detected at the falling edge of the input clock signal while detecting the rising edge of the input clock signal. First signal generating means for determining a time for which the signal maintains a high impedance state; Second signal generating means for detecting the falling edge of the input clock signal and determining the time for which the output clock signal maintains the high impedance state at the rising edge of the input clock signal; Means for amplifying the first signal and the second signal; The present invention provides a clock buffer device including an output terminal transistor configured to generate an output clock signal in response to changes of the amplified first and second signals. According to the present invention, the low power consumption characteristics can be maintained even at a high frequency clock, and even if the characteristics of the transistor such as the waveform generator are changed according to the process conditions or the temperature conditions, the final stage output transistors are all turned "off" to short-circuit current. Can be prevented.

Description

Clock buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock buffer device, and more particularly, to a clock buffer device capable of maintaining low power consumption even at a high frequency by using a digital tuning method.

In high performance high capacity integrated circuit chips, internal clock signals are distributed throughout the chip to control the timing of the chip as a function of the external system clock. In general, this internal clock signal is generated by the clock buffer device from an external clock and distributed to circuits in the chip. A typical clock buffer device includes a large inverter that receives an external clock signal and transmits it to two output transistors. The output transistor transmits an internal clock signal to a clock distribution network in a chip.

FIG. 1 is a circuit diagram according to an example of the related art using an analog tuning method for such a clock buffer device.

When an input clock is applied on the left side In of FIG. 1, the waveform is converted by the waveform generator 110 which converts the pulse width of the input into two types. The two waveform conversions are respectively made by inverters connected in series (s1p and s2p, s1n and s2n in FIG. 1). The waveform formed by the upper waveform generator s1p → s2p is input to the output PMOS driver 130 to improve the current driving capability, and then is input to the gate of the PMOS Mp outputting the final output signal to control the final output. . On the other hand, the waveform formed by the lower waveform generator (s1n → s2n) is input to the output NMOS driver 120 to improve the current driving capability, and then input to the gate of the NMOS (Mn) for outputting the final output signal to the final output To control. The final output signal is output by the final output stage 140 which is CMOS.

FIG. 2 is a diagram showing waveforms at respective parts of the circuit shown in FIG. Hereinafter, the circuit of FIG. 1 will be described in more detail with reference to FIG. 2.

(A) is the waveform of the input clock, (b) is the output waveform of the inverter s1p, (c) is the output waveform of the inverter s2p which is the final output waveform of the upper waveform generator, and (d) is the inverter ( output waveform of s1n), (e) is output waveform of inverter s2n which is the final output waveform of lower waveform generator, (f) is output waveform of output PMOS driver, (g) is output waveform of output NMOS driver, (h ) Is a diagram showing the waveform of the output clock passing through the output inverter over time.

According to the conventional circuit, by using the modified clock signal as shown in Figs. 1F and 1G as the gate input signal of the PMOS and NMOS, respectively, the PMOS and NMOS are " off " High impedance) "state. In the high impedance state, as shown in (h) of FIG. 2, when the waveform of the output clock is transitioned, the gate inputs of the NMOS and PMOS become 0 (high) and 1 (low), respectively, and the power supply voltage (Vdd) ) And ground potential (GND) are not transmitted to the output of the clock buffer. This is an output state of the tri-state, and is shown as part of a thick line in FIG. 1 (h).

In this way, the short-circuit current path is cut off, thereby reducing the power consumption of the final stage inverter. Here, the short-circuit current means a current flowing through the path Vdd → Mp → Mn → GND in the transition intermediate region when an inverter composed of PMOS and NMOS transistors having the same gate input signal transitions the output signal of the output stage drivers 120 and 130. do.

On the other hand, unlike the circuit of Figure 1 when the clock buffer consisting of a typical inverter chain, the power consumption is expressed by the following equation (1).

[Equation 1]

Ptotal = Psc + Pbuf + Pload

Here, Ptotal represents total power used in the clock buffer, Psc represents short circuit current, Pbuf represents power consumed by the parallel capacitor of the transistor, and Pload represents power consumed by the load.

On the contrary, since the short-circuit current does not flow in the final output stage, the power consumption in the circuit shown in FIG. 1 is represented by Equation 2 below.

[Equation 2]

Ptotal = Psc-0.3Psc + Pbuf + Pload

In the equation (2), 0.3Psc is a gain portion generated because a short circuit current does not flow in the final output stage unlike a clock buffer composed of a general inverter chain, and the circuit shown in FIG. 1 has a power gain of 0.3Psc.

However, in order to maintain the above-mentioned advantages of the clock buffer circuit as shown in FIG. 1, the pulse width of the signal transmitted to the gate of the final output terminal 140 must be accurately adjusted as the high frequency clock is used. It is difficult to control only by the size of the transistor of 110). Further, even if the transistor size is properly tuned once, if the characteristics of the transistor of the waveform generator 110 change in an undesired direction for reasons of manufacturing process, for example, when the gate input signal of the final output terminal 140 transitions to NMOS (Mn). In the case where both the region " on " and the PMOS Mp are changed in a direction that lasts longer than the general inverter chain, the clock buffer circuit of FIG. 1 consumes more power than the clock buffer composed of the general inverter chain. In other words, the conventional clock buffer circuit shown in Fig. 1 operates well while exhibiting low power consumption characteristics, such as design intention, at low frequency clocks, but it is difficult to maintain low power consumption characteristics at high frequencies of about 100 MHz or more due to the above technical problem. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a clock buffer device capable of maintaining low power consumption even at a high frequency clock.

Another object of the present invention is to provide a buffer device capable of maintaining low power consumption even when the characteristics of a transistor constituting the clock buffer device change depending on process conditions and temperature conditions.

1 is a circuit diagram showing an example of an analog tuning clock buffer device according to the prior art;

FIG. 2 is a diagram showing waveforms at respective parts of the circuit shown in FIG. 1; FIG.

3 is a circuit diagram according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11: NAND gate

17: NOR gate

Mp, 23: PMOS

Mn, 24: NMOS

110: waveform generator

120: output terminal NMOS driver

130: output terminal PMOS driver

140: output stage inverter

Clk: Input Clock

Clkout: Output Clock

The present invention for realizing the above object is a clock buffer device for generating an output clock signal from an input clock signal having a rising edge (rising edge) and a falling edge (falling edge),

First signal generating means for detecting the rising edge of the input clock signal and determining a time at which the output clock signal maintains a high impedance state at the falling edge of the input clock signal;

Second signal generating means for detecting the falling edge of the input clock signal and determining the time for which the output clock signal maintains the high impedance state at the rising edge of the input clock signal;

Means for amplifying the first signal and the second signal;

It provides a clock buffer device comprising an output terminal transistor for generating an output clock signal in response to the change of the amplified first signal and the second signal.

In the present invention,

The first signal generating means includes a NAND gate having an input of each of the input clock signal and the output signal of the second signal generating means and a first inverter connected thereto.

Preferably, the second signal generating means comprises a NOR gate having each of the input clock signal and the output signal of the first signal generating means as an input, and a second inverter connected thereto. More preferably, it is a CMOS (complementary MOS) consisting of a PMOS having the first signal as the gate input and an NMOS having the second signal through the amplifying means as the gate input.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. This embodiment is not intended to limit the scope of the invention, but is presented by way of example only.

FIG. 3 is a circuit diagram according to an embodiment of the present invention. When the operation of the circuit is observed in terms of signal change, it may be represented as shown in Table 1 below.

TABLE 1

Transition stage (a) (b) (c) (d) (e) (f) (g) (h) Input clock (Clk) 0 0 → 1 One One One 1 → 0 0 0 Node 14 0 0 0 0 → 1 One One 1 → 0 0 Node 20 0 0 0 → 1 One One One One 1 → 0 PMOS (23) off off off Off → on On On On → off off NMOS (24) On On On → off off off off off Off → on Output Clock (Clkout) 0 0 0 → hZ hZ → 1 One One 1 → hZ hZ → 0

In Table 1, transition steps (a) to (h) indicate the passage of time in that order, and hZ indicates a high impedance state.

Referring to Table 1, the circuit of FIG. 3 will be described below.

In the circuit of Fig. 3, the first inverter 13 is connected to the NAND gate 11 having the input clock signal Clk and the signal of the node 20 which is the output terminal of the second inverter 19 as an input, and the first The signal of the node 14, which is the output terminal of the inverter 13, enters the input of the NOR gate 17 together with the input clock Clk. The signal at node 14 then enters the gate input of PMOS 23 at the final output stage via third inverter 15 and the NMOS signal at final output stage via fourth inverter 21. Enter the gate input of 24 to generate an output clock signal Clkout.

As shown in transition step (b) of Table 1, when the input clock is a rising edge, i.e., when the signal transitions from 0 to 1, the transition step (c) thus corresponds to the node which is the output terminal of the second inverter 19. The signal at 20 also transitions from 0 to 1, causing the NMOS 14 to be " off ". The PMOS 23 remains in the " off " state because node 14 is holding a zero signal. Therefore, the output clock signal Clkout of the transition step (c) transitions from 0 to the high impedance state, starts from the power supply voltage Vdd of FIG. 3, passes through the PMOS 23 and the NMOS 24 in turn, and then the ground potential. Short circuit current flowing to (GND) is prevented.

Similarly, when the input clock is a falling edge, i.e., when the signal transitions from 1 to 0, as shown in transition step (f) of Table 1, the transition stage (g) accordingly output stage of the first inverter 13 The signal at in node 14 also transitions from 1 to 0, causing PMOS 23 to " off ". The NMOS 24 remains in the " off " state because the node 20 is holding a signal of one. Therefore, the output clock signal Clkout of the transition step (g) is transitioned from 1 to the high impedance state, starting from the power supply voltage Vdd of FIG. 3 and passing through the PMOS 23 and the NMOS 24 in turn, and then the ground potential ( Short-circuit current flowing to GND) is prevented.

In other words, the circuit digitally tunes the signals input to the gate inputs of the PMOS 23 and the NMOS 24 at the final output stage, and puts both the PMOS 23 and the NMOS 24 in the " off state " The short circuit current at the time of signal transition can be prevented.

Since the above signal changes are all digital, the input signal of the output gate can be precisely controlled regardless of the characteristics of the transistor such as the waveform generator constituting the clock buffer device according to the process conditions or the temperature conditions. .

When the clock buffer device using the digital tuning method as described above is used, the low power consumption characteristics, which are advantages of the conventional clock buffer device only in the low frequency clock, can be maintained even at the high frequency clock, and transistors such as waveform generators and the like can be used. Even if the characteristics of the circuit change according to the process conditions or the temperature conditions, the short-circuit current can be prevented by turning off the final output transistors.

Claims (3)

A clock buffer device for generating an output clock signal from an input clock signal having a rising edge and a falling edge, First signal generating means for detecting the rising edge of the input clock signal and determining a time at which the output clock signal maintains a high impedance state at the falling edge of the input clock signal; Second signal generating means for detecting the falling edge of the input clock signal and determining the time for which the output clock signal maintains the high impedance state at the rising edge of the input clock signal; Means for amplifying the first signal and the second signal; And an output terminal transistor configured to generate an output clock signal in response to changes in the amplified first and second signals. The method of claim 1, wherein the first signal generating means comprises a NAND gate having a respective input signal of the input clock signal and the output signal of the second signal generating means and a first inverter connected thereto. And the second signal generating means comprises a NOR gate having each of the input clock signal and the output signal of the first signal generating means as an input and a second inverter connected thereto. The clock buffer device according to claim 1, wherein the output transistor is a CMOS comprising a PMOS having the amplified first signal as a gate input and an NMOS having the amplified second signal as a gate input.

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