JPH05244103A - Sampling frequency converter - Google Patents

Abstract

PURPOSE:To reduce error of a data interpolation, and also, to generate data of local sampling frequency being different from an input sampling frequency and having high stability. CONSTITUTION:A clock generator 2 is synchronized with a sampling frequency fs1, generates a clock frequency nfs1 of a frequency of (n) folds, and a digital filter 1 calculates (n) pieces of interpolation data DIn synchronized with the clock frequency nfs1. A counter 4 generates a clock frequency fs2 by dividing the clock frequency nfs1 into (n), and a comparator 5 compares phases of the clock frequency fs2 and a local sampling frequency f1, applies a leading signal Ps or a lagging signal Ds to the counter 4 and controls the count. A retainer 3 latches interpolation data DIn, based on the clock frequency fs2' and an output retainer 6 executes resampling of an output of the retainer 3, based on the sampling frequency f1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a sampling frequency converter of an audio signal processing device. In particular, the present invention relates to a sampling frequency converter that inputs digital audio data and generates digital audio data having a sampling frequency different from the input sampling frequency.

[0002]

2. Description of the Related Art Conventionally, a sampling frequency converter once converts input digital audio data into analog audio data and samples the converted analog audio data at a different sampling frequency that requires it.
A first method for newly generating digital audio data,
A second method of using a digital filter to perform linear interpolation with the least common multiple of two sampling frequencies different from each other to generate data of the required sampling frequency,
A third method was used in which digital filters were connected in cascade to generate doubled sampling data and to generate data at a required sampling frequency.

[0003]

However, in such a conventional sampling frequency converter, when the analog voice data of the first method is once restored, S / N (signal-to-noise) due to the accumulation of quantization noise is generated. Ratio), deterioration of quality due to aging of constituent elements, and deterioration of quality due to increase of adjustment points of analog circuit.

When the digital filter of the second method is used, the least common multiple of two sampling frequencies different from each other is previously determined, which means that the predetermined relationship (nf _s1 = m) between the two sampling frequencies is previously determined.
Since there is f ₁ ), there is a drawback that only the value can be converted.

Further, when the digital filters of the third method are connected in cascade, the number of connected stages is different due to the increase in the delay amount due to the cascade connection and the relationship between two different frequencies. However, there is a drawback that the circuit becomes large as well as being impossible.

The present invention solves the above-mentioned drawbacks by reducing the error of data interpolation, generating audio data having a local sampling frequency different from the input sampling frequency, and converting the sampling frequency with high stability. It is an object of the present invention to provide a sampling frequency converter capable of

[0007]

SUMMARY OF THE INVENTION According to the present invention, there is provided a clock generator which generates a first clock frequency of n times in synchronization with an input sampling frequency, and an audio data which is input to the first clock frequency. A first digital filter for calculating synchronized n pieces of interpolation data, a counter for dividing the first clock frequency by n to generate a second clock frequency, and an output second clock frequency of the counter. A comparator for comparing the phase with an input local sampling frequency and outputting a phase control signal, the counter including means for controlling the count based on the phase control signal, and the output second clock frequency of the counter A holder for latching the output interpolation data of the first digital filter based on the above, and the output of this holder for the local sampling Characterized by comprising a resampling unit for resampling on the basis of the ring frequency.

A second digital filter for removing noise from the output of the resampling means based on the local sampling frequency can be provided.

[0009]

The clock generator is synchronized with the input sampling frequency and generates the first clock frequency n times higher. The first digital filter inputs audio data and calculates n pieces of interpolation data synchronized with the first clock frequency. The counter divides the frequency of the first clock signal by n to generate a second clock frequency. The comparator compares the phase of the output second clock frequency of the counter with the input local sampling frequency and outputs a phase control signal. The counter controls counting based on the output phase control signal of the comparator. The holder latches the output interpolation data of the first digital filter based on the output second clock frequency of the counter. The resampling means resamples the output of the retainer based on the local sampling frequency.

The second digital filter can remove noise from the output of the resampling means based on the local sampling frequency.

As described above, it is possible to reduce an error in data interpolation, generate voice data having a local sampling frequency different from the input sampling frequency, and perform sampling frequency conversion with high stability.

[0012]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a sampling frequency converter according to an embodiment of the present invention. In FIG. 1, a sampling frequency converter includes a clock generator 2 that generates a clock frequency nf _s1 as a first clock frequency that is n times as high as an input sampling frequency in synchronization with the sampling frequency f _s1 , and audio data D _in Is input to calculate the n pieces of interpolation data DI _n synchronized with the clock frequency nf _s1 , and the digital filter 1 is used as a first digital filter, and the clock frequency nf _s1 is divided by n to obtain the second clock frequency as the clock frequency f. A comparator 5 that compares the phase of the counter 4 that generates _s2 with the output clock frequency f _s2 of the counter 4 and the local sampling frequency f ₁ that is input and outputs the lead signal P _S or the delay signal D _s as a phase control signal. with the door, the counter 4 is based on the output lead signal P _s or delayed signal D _s of the comparator 5 counts It comprises means for controlling the output clock frequency f of the counter 4
Output interpolation data DI of digital filter 1 based on _S2
It is provided with a holder 3 for latching _n , and an output holder 6 as resampling means for resampling the output of the holder 3 based on the local sampling frequency f ₁ .

The operation of the sampling frequency converter having such a configuration will be described.

[0014] In FIG 1, the audio data D _in sampled at the sampling frequency f _s1 is supplied to the clock generator 2 and the digital filter 1 to generate an n times the clock frequency nf _s1 synchronized with the sampling frequency f _s1 . The digital filter 1 includes a clock generator 2
The n pieces of interpolation data DI _n (however, one of the n pieces may use the input voice data D _in ) in synchronization with the clock frequency nf _s1 are calculated and supplied to the holder 3. In addition, the clock frequency nf from the clock generator 2
_s1 is supplied to the counter 4, the counter 4 generates a clock frequency f _s2 synchronized with the sampling frequency f _s1, the retainer 3 on the basis of the clock frequency f _s2 to one of the data of the interpolated data DI _n data input Hold.

On the other hand, the clock frequency f _s2 is supplied to the comparator 5 and compared in phase with the local sampling frequency f ₁ . The comparator 5 compares the phases of the clock frequency f _s2 and the local sampling frequency f ₁ and advances the signal P _S or the delay signal D _S (for example, the clock frequency f _s2 advances with respect to the local sampling frequency f _1). When it is present, it advances, or when it is late, it outputs a delay) and supplies it to the counter 4. The counter 4 displays the advance signal P _S
When the delay signal D _S arrives, the counting is delayed, and when the delay signal D _S arrives, the counting is advanced. As a result, the clock frequency f _s2 and the local sampling frequency f ₁ are approximately in phase. For this reason, the output of the holder 3 held at the clock frequency f _s2 changes in a phase substantially close to the local sampling frequency f ₁ , and the output holder 6 re-latches at the local sampling frequency f _1. And output data D _O can be obtained.

FIG. 2 is a block diagram of a sampling frequency converter according to another embodiment of the present invention. Through a digital filter 7 the output of the output retainer 6 as shown in FIG. 2, the digital audio data synchronized by performing filtering on the local sampling frequency f _1, the local sampling frequency f ₁ which removes unnecessary noise components D
You can get _out .

[0017]

As described above, according to the present invention, it is possible to reduce the error of the data interpolation, generate the audio data of the local sampling frequency different from the input sampling frequency, and perform the sampling frequency conversion with high stability. It has an excellent effect.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a sampling frequency converter according to an embodiment of the present invention.

FIG. 2 is a block diagram of a sampling frequency converter according to another embodiment of the present invention.

[Explanation of symbols]

1 Digital filter 2 Clock generator 3 Retainer 4 Counter 5 Comparator 6 Output retainer 7 Digital filter D _in Audio data D _O Output data D _out Digital audio data D _S Delay signal P _s Lead signal f ₁ Local sampling frequency nf _s1 , f _s2 clock frequency

Claims (2)

[Claims] 1. An n synchronized with an input sampling frequency
A clock generator that generates a first clock frequency that is double the frequency; a first digital filter that calculates n pieces of interpolation data that are synchronized with the first clock frequency based on input audio data; Of the counter which divides the clock frequency of n by n to generate the second clock frequency, and a comparator which compares the phase of the output second clock frequency of this counter with the input local sampling frequency and outputs a phase control signal. The counter includes means for controlling the count based on the output phase control signal of the comparator, and holds the output interpolation data of the first digital filter based on the output second clock frequency of the counter. And the resampling that resamples the output of this holder based on the local sampling frequency Sampling frequency converter characterized by comprising a stage. 2. The sampling frequency converter according to claim 1, further comprising a second digital filter for removing noise from the output of the resampling means based on the local sampling frequency.