JPH06338801A - Sampling frequency converter - Google Patents

Abstract

PURPOSE:To obtain a sampling frequency converter with simple circuit configuration and capable of reducing a noise due to re-sampling. CONSTITUTION:A clock generator 1 outputs a clock CLK1 of (n) times a first sampling frequency before conversion. An over-sampling signal generator 2 outputs over-sampling data DS of (m) times the first sampling frequency from input digital voice data DI. A counter 3 counts the clock CLK1 for n/m times. An interpolator 4 operates interpolation data DM at every clock CLK1 based on the over-sampling data and the output value (x) of the counter 3. A re- sampler 5 performs the sampling of the interpolation data DM by a clock CLK2 of sampling frequency. Thereby, since the re-sampling of data equivalent to the one to which the sampling by the clock CLK1 is applied can be performed, digital voice data with high precision can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling frequency converter for converting digital audio data sampled at a certain sampling frequency into digital audio data having another sampling frequency.

[0002]

2. Description of the Related Art Conventionally, there is a sampling frequency converter that converts digital audio data sampled at a certain sampling frequency into digital audio data at another sampling frequency. There is a method in which the input digital audio data is once converted into an analog audio signal and the analog audio signal is sampled again to generate new digital audio data. Another method is to perform oversampling on the input digital audio data and resample the oversampling data.

When digital audio data is sampled at the re-sampling frequency as it is, a data slip occurs and the same data is sampled twice or data is lost, resulting in large distortion in continuous data and output as noise. Will end up. In other words, the reason for oversampling is to reduce this noise, and there is an advantage that the configuration can be inexpensive. Then, assuming that the sampling frequency of the input digital audio data is 48 kHz, it is 8 times as high as 3
Oversampling of about 84 kHz is usually performed.

[0004]

Since the conventional sampling frequency converter has resampled as described above, the method of once converting into an analog signal deteriorates the S / N ratio due to the accumulation of quantization noise. However, there have been problems such as deterioration of sound quality due to aging of constituent elements, and deterioration of quality due to increase in adjustment points of analog circuits. Also, in the method of performing oversampling, even when the oversampling of about 8 times is performed, when a single sound in the audible band is heard, noise at the time of data slipping is heard, and when trying to generate the oversampling data of 8 times or more, a high speed IC is used. However, there is a problem that the circuit scale increases and becomes complicated. In order to solve the above problems, it is an object of the present invention to provide a sampling frequency converter having a simple circuit configuration and capable of reducing noise due to re-sampling.

[0005]

According to the present invention, there is provided a clock generator which outputs a clock having a first constant multiple of a first sampling frequency, and a second constant multiple oversampling data from input digital data. An oversampling signal generator, a counter for counting a predetermined number of clocks output from the clock generator based on the first constant and the second constant, and an output from the clock generator based on the oversampling data and the output of the counter It has an interpolator that calculates the interpolated data for each of the generated clocks, and a resampler that samples the interpolated data output from the interpolator at the second sampling frequency.

A clock generator that outputs a clock that is a first constant multiple of the first sampling frequency, and an oversampling signal generator that outputs second constant multiple oversampling data from the input digital data, The clock output from the clock generator is the first constant and the second constant.
A counter that counts a predetermined number based on the constant of the, a holder that holds the output of the counter and outputs it at each clock of the second sampling frequency, and a second sampling that is based on the oversampling data and the output of the holder. And an interpolator that calculates output digital data for each frequency clock.

[0007]

According to the present invention, the oversampling signal generator generates the second constant-multiplied oversampling data from the input digital data. Then, based on the output of the counter that counts the oversampling data and the clock of the first constant multiple of the first sampling frequency output from the clock generator, the interpolated data is output to the clock of the clock generator by the interpolator. The re-sampler samples the interpolated data at the second sampling frequency. Further, the output of the counter is held by the holder and is output for each second sampling frequency, and the output of the counter is output for each clock of the second sampling frequency based on the oversampling data and the output of the holder by the interpolator. The data is calculated.

[0008]

1 is a block diagram of a sampling frequency converter showing an embodiment of the present invention, and FIG. 2 is a diagram showing the operation timing of this sampling frequency converter. In FIG. 1, 1 is a clock generator that outputs a clock that is n times (first constant times) the first sampling frequency of the input digital audio data.
Is an oversampling signal generator that outputs m times (second constant times) oversampling data from the input digital audio data, and 3 counts the clock output from the clock generator 1 by a predetermined number n / m times. A counter 4 calculates the interpolated data for each clock output from the clock generator 1 based on the output of the oversampling data and the counter 3, and 5 indicates the interpolated data output from the interpolator 4. It is a resampling device that samples at a second sampling frequency.

DI is input digital audio data, D
S is oversampling data output from the oversampling signal generator 2, DM is interpolation data output from the interpolator 4, DO is output digital audio data output from the resampler 5, and CLK1 is clock generation. Bowl 1
The clock, CLK2, output from the
Is a sampling frequency, and x is an output value of the counter 3. Further, FIG. 2 is a diagram showing the operation timing of this sampling frequency converter in which the first constant n is eight times the second constant m.

Next, the operation of such a sampling frequency converter will be described. The clock generator 1 is n times the sampling frequency f of the input digital audio data DI (m to be described later).
Clock CLK with a frequency nf
1 is output. Then, the oversampling signal generator 2 receives the clock CL from the input digital audio data DI.
The m (for example, 8 or 16) times oversampling data DS synchronized with K1 is output.

Therefore, the first constant n is equal to 8 of the second constant m.
If doubled, the oversampling data DS is shown in FIG.
It is output every 8 clocks of CLK1 as shown in (b). This oversampling data DS is
For example, input digital audio data DI of several hundred samplings
It is the data obtained by interpolating from.

Then, the counter 3 uses the clock CLK1.
Is counted n / m times, that is, from 0 to n / m−1, and this is output as an output value x. Now n / m
Is 8, the counter 3 outputs the output value x as shown in FIG.
As a result, 0 to 7 are repeatedly output.

Next, the oversampling signal generator 2
In the oversampling data DS output from the above, if the current data is DSj and the data one sampling before is DSj-1, as shown in FIG. 2B, the interpolator 4 which is a linear interpolator outputs the data DSj. , DSj-1 and the output value x of the counter 3 to generate the interpolated data DM as the clock CLK1.
The following equation is calculated every 1 clock.

DM = {1-x / (n / m)} × DSj−1 + {x / (n / m)} × DSj (1) For example, n / m is 8 and the current counter 3 Output value x of 2
Then, the interpolation data DM2 output from the interpolator 4 at this time is calculated by the following equation. DM2 = (1-2 / 8) × DSj-1 + (2/8) × DSj = (3/4) × DSj-1 + (1/4) × DSj (2)

Then, the interpolator 4 outputs the interpolated data DM calculated in this way for every one clock of the clock CLK1. That is, the interpolator 4 is a predetermined multiple of n for each data of the oversampling signal generator 2.
/ M times the data will be generated.

Next, the resampler 5 resamples the interpolated data DM output from the interpolator 4 with the clock CLK2. This means that the input digital audio data DI having the first sampling frequency has been converted into the output digital audio data DO having the second sampling frequency.

Therefore, by linearly interpolating the once oversampled data, the clock CL is substantially
When K1 is over-sampled, for example, when m is 16 and n is 16 times m, data equivalent to that obtained by over-sampling 256 times can be obtained. By re-sampling this data, the accuracy is high. Digital voice data can be obtained.

Further, the interpolator of the embodiment shown in FIG.
Although data calculation is performed by LK1, it may be configured to perform this at the second sampling frequency. FIG. 3 is a block diagram of a sampling frequency converter showing another embodiment of the present invention.
Reference numeral 4a denotes an interpolator that calculates interpolation data for each clock CLK2 that is the second sampling frequency based on the output of the oversampling data DS and a later-described holder, and 6 holds the output value x of the counter 3. It is a holder that outputs every clock CLK2.

The operation of this sampling frequency converter is basically the same as the example of FIG. 1, but the holder 6 outputs the output value x of the counter 3 to the clock CLK2 whose frequency is the second sampling frequency. Output for each. Therefore, the interpolator 4a calculates and outputs the interpolated data, that is, the output digital audio data DO for each clock CLK2 in the same manner as in the example of FIG. 1, so that the same effect can be obtained with a simpler circuit. .

[0020]

According to the present invention, the oversampling data obtained by oversampling the input digital data is linearly interpolated into the interpolated data of a predetermined number of times, so that the first sampling frequency is substantially equal to the first sampling frequency. Since data equivalent to that obtained by performing oversampling at a frequency that is a constant multiple of is obtained, a simple circuit configuration can be achieved and noise due to re-sampling can be reduced.

Further, by providing the holder, only the counter operates at a high speed, and if the interpolator calculates the output digital data at the speed of the second sampling frequency lower than the clock of the clock generator. Since it is good, the circuit structure can be made more stable and at a lower cost.

[Brief description of drawings]

FIG. 1 is a block diagram of a sampling frequency converter showing an embodiment of the present invention.

FIG. 2 is a diagram showing operation timing of the sampling frequency converter of FIG.

FIG. 3 is a block diagram of a sampling frequency converter showing another embodiment of the present invention.

[Explanation of symbols]

 1 Clock Generator 2 Oversampling Signal Generator 3 Counter 4 Interpolator 5 Resampler 6 Holder

Claims (2)

[Claims] 1. A sampling frequency converter for converting digital data sampled at a first sampling frequency into digital data sampled at a second sampling frequency, wherein: A clock generator that outputs a clock that is a constant multiple of 1, an oversampling signal generator that outputs second constant multiple oversampling data from the input digital data, and a clock that is output from the clock generator as a first A counter that counts a predetermined number based on a constant and a second constant; an interpolator that calculates interpolation data for each clock output from the clock generator based on the output of the oversampling data and the counter; And a resampler for sampling the interpolated data output from the interpolator at a second sampling frequency. Frequency converter. 2. A sampling frequency converter for converting digital data sampled at a first sampling frequency into digital data sampled at a second sampling frequency, wherein: A clock generator that outputs a clock that is a constant multiple of 1, an oversampling signal generator that outputs second constant multiple oversampling data from the input digital data, and a clock that is output from the clock generator as a first A counter that counts a predetermined number based on a constant and a second constant, a holder that holds the output of the counter and outputs it for each clock of the second sampling frequency, and based on the output of the oversampling data and the holder. And an interpolator that calculates output digital data for each clock of the second sampling frequency. Number converter.